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Metal-Oxide Semiconductor
(MOS) Field Effect Transistors
MOS DEVICE
FUNDAMENTALS
Professor A. K. Majumdar
Computer Science and Engineering
Department Indian Institute of
Technology, Kharagpur
NMOS enhancement mode transistor
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Induced Channel in NMOS
Transistor
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Current – Voltage characteristics
of NMOS transistors
Enhancement mode NMOS transistor with
VGS>0 showing induced channel
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NMOS Transistor Analysis Contd
NMOS Transistor Analysis
•
•
•
•
•
vn(x) = - μn E(x) = μn dV/dx
μn = Mobility of electrons
Hence IDS = - μn Q(x)W dV/dx
Substituting for Q(x),
IDS dx = μn COX W[VGS– V(x) – Vth] dV
Integrating
• IDS= μn COX W/L[(VGS - Vth ) - VDS /2 ] VDS
• IDS = ηn [(VGS - Vth ) - VDS /2 ] VDS
• Induced Channel Charge / Unit Area
Q(x) = - COX [ VGS – V(x) – Vth]
Where COX = εOX/ tOX capacitance per unit
area due to gate oxide
Drain current IDS = vn(x) Q(x)W
vn(x) = drift velocity of electron
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NMOS Transistor Analysis in
Linear Region
NMOS Transistor Analysis in
Linear Region
• kn =μn COX = μn εOX/ tOX is called process
transconductance parameter
• ηn = kn(W/L) is called gain factor
• For small VDS , VDS2 /2 can be ignored and
IDS depends linearly on VDS
• Rlinear = 1/ (ηn (VGS - Vth))
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• Transconductance of NMOS transistor
• gm = (dIDS/ dVGS)│ VDS = constant
In linear region
gm = ηn VDS
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NMOS Transistor Analysis
Saturation Region
• The drain-to-source current-voltage dependence for a
NMOS transistor is given by the following equations
• IDS = 0
• IDS = ηn/2.(VGS – Vth)2
for 0 < VDS – Vth < VDS (saturation)
ηn = (μnεox/tox).W/L
where μn is the mobility of electron, εox is the permittivity
of the oxide material, and tox is the thickness of the
oxide.
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Current – Voltage Relationship of
PMOS Transistor
• In saturation region, the transistor does
not operate as a perfect current source,
i.e. IDS is not independent of VDS
• As VDS is increased beyond (VGS– Vth)
effective channel length decreases.
• Since IDS α 1/L, reduction in effective
channel length increases IDS
• More accurate representation
• IDS = ηn/2.(Vgs – Vth)2 ( 1 + λVDS)
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for VDS < Vth (off)
• IDS = ηn(VGS – Vth – VDS/2)VDS for VGS > Vth and VGS – Vth≥ VDS (linear)
Channel Length Modulation
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Current – Voltage Relationship of
NMOS Transistor
• VDS ≥ VGS – Vth
• Channel is pinched off
• Assuming voltage difference over induced
channel from source to pinch off point fixed at
VGS – Vth
• IDS = ηn /2 (VGS – Vth)2
• In saturation region, MOS transistor acts as a
constant current source.
• Transconductance in saturation region
• gm = ηn (VGS – Vth)
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• Cut off VGS > Vth
ƒ IDS = 0
• Linear Region: VGS ≤ Vth and VDS > VGS – Vth
ƒ
IDS = ηp(VGS – Vth – VDS/2)VDS
• Saturation region VGS ≤ Vth, and VDS < VGS–Vth
ƒ IDS = ηp/2.(VGS–Vth)2
where the gain factor
ηp = (μpεox/tox).W/L and μp is mobility of holes
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Lateral diffusion of source and
drain regions
MOSFET Capacitances
Lateral diffusion = Ld
Effective channel length Leff = L -2 Ld
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MOS transistor gate capacitances for three
operating regions
Capacitance
CGB
CGS
CGD
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NMOS Inverter
Cutoff Linear
Saturation
CoxW Leff
0
0
Cox W Ld CoxW Ld + ½ CoxW Leff CoxW Ld + 2/3 CoxW Leff
Cox W Ld CoxW Ld + ½ CoxW Leff CoxW Ld
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Pull Up and Pull Down transistors
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Current Voltage Characteristics of
NMOS Inverter
• The depletion mode transistor is a pull up
device. It is always on (Vgs = 0)
• The enhancement mode transistor is the
pull down device.
• With no current drawn from output, current
in both pull up and pull down transistors
must be same.
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NMOS Inverter
NMOS Inverter
• The points of intersection of the pull up (for Vgs =0 )
and pull down curves give points on the transfer
characteristics for the inverter
• As Vin exceeds VTpd (pull down transistor threshold)
current will flow and Vout falls. Further increase in Vin
will cause pull down transistor to be out of saturation
and will behave as resistor
• Pull up device is initially resistive when pull down is
turned on
• The point at which Vin = Vout is called Vinv
• Vinv can be shifted by variation of ratios of pull up and
down resistances – determined by the length to
width ratio of the transistor.
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• With NMOS Depletion Mode transistor
• High Dissipation: When VIN is high current
flows through both the devices.
• Output switching: occurs when Vin
exceeds Vthpd
• During fall 1→ 0 transition, pull up offers
lower resistance to charge capacitive load.
• Degrades 0 value : Low output value is
determined by pull down resistance.
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CMOS INVERTER
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CMOS Inverter
N Well
VDD
VDD
PMOS
2λ
Contacts
PMOS
In
Out
In
Out
Metal 1
Polysilicon
NMOS
NMOS
GND
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CMOS Fabrication
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CMOS Fabrication
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Current Voltage Characteristics
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CMOS INVERTER - CONTD
CMOS INVERTER –VOLTAGE
TRANSFER CHARACTERISTICS
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CMOS Inverter Characteristics
• Region R1: 0 < Vin < Vthn, NMOS transistor is off, PMOS
device operates in the linear region.
• Region R2: Vthn< Vin< VDD - |Vthp| and Vin + |Vthp| < Vout
≤ VDD, NMOS transistor in saturation, and PMOS transistor
still in the linear region.
• Region R3: Vthn<Vin<VDD - |Vthp| and Vin - Vthn ≤ Vout ≤
Vin + |Vthp|, both the transistors are in saturation.
• Region R4: Vthn < Vin< VDD – |Vthp| and Vout < Vin - Vthn,
NMOS transistor is in the linear region and PMOS
remains in saturation.
• Region R5: VDD – |Vthp| < Vin < VDD, PMOS transistor in
cut-off, NMOS in the linear region.
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Current – Voltage Relationship of NMOS
transistor : VGSn = Vin , VDSn = Vout
VGSp = - (VDD – Vin), VDSp = - (VDD – Vout)
ηp = (μp ε/tox) (W/L)n
ηn = (μn ε/tox) (W/L)n
Cut-off (Vin > VDD - |Vthp|)
: IDS = 0
Saturation (Vin ≤ VDD - |Vthp|) and (Vout ≤ Vin +|Vthp|)
:IDS = ηp/2(VGSn – |Vthp|)2
Saturation ( Vthn ≤ Vin, Vout > Vin – Vthn):
IDS = ηn/2(VGSn – Vthn)2
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: IDS = 0
Linear (Vin ≤ VDD - |Vthp|) and (Vout >Vin +|Vthn|)
: IDS = ηn(VGSp – |Vthp| –VDSp/2)VDSp
Linear (Vin – Vthn ≥ Vout) :
IDS = ηn(VGSn – Vthn – VDSn/2)VDSn
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Current – Voltage Relationship of PMOS
transistor
Static Analysis of CMOS Inverter
Cut-off (Vin ≤ Vthn)
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Static Analysis of CMOS InverterContd
Static Analysis of CMOS InverterContd
•
•
•
•
VOH = VDD
VOL = 0
Vinv = [ Vthn + (1/√β)(VDD + Vthp)] / (1 + 1/√β)
β = ηn/ηp
=[μn(εox/tox)n (W/L)n ]/ [μp(εox/tox)p(W/L)p]
• for β = 1,
• (W/L)n / (W/L)p = μp/μn ≈ 1/2.5
• (W/L)p ≈ 2.5 (W/L)n
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•
•
•
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•
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VIL = (2Vout + Vthp – VDD + βVthn) / (1 + β)
β = 1, and Vthn = │Vthp│
VIL = 1/8 (3VDD +2 Vthn)
VIH = [VDD + Vthp + β(2 Vout + Vthn)] / (1 + β)
with β = 1, and Vthn = │Vthp│,
VIH = (5VDD – 2Vthn) /8
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Switching Characteristics of a
CMOS Inverter
NOISE MARGINS
• NML = VIL – VOL = VIL
• NMH = VOH – VIH = VDD – VIH
Parasitic capacitances in a cascaded CMOS
inverter
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Propagation delay times and rise and fall
times of an inverter
Switch model of a static CMOS inverter
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Propagation Delay Estimation
CMOS inverter equivalent circuit during
high-to-low and low-to-high output
transitions
• High to Low Transition
• τpHL = τpHL1 + τpHL2
• τpHL1 = the period during which Vout drops
from VDD to VDD – Vthn.
• τpHL1 = 2 CLVthn / ηn (VDD – Vthn)2
• τpHL2 = the period during which Vout drops
from VDD – Vthn to VDD /2.
⎡ ⎛
4V thn
CL
⎢ ln ⎜ 3 −
− V thn ) ⎣ ⎜⎝
V DD
• τpHL2 = η n (V DD
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Propagation Delay Estimation –
Contd.
CL
⎡ 2|Vthp |
⎢
ηp(VDD−|Vthp |)⎣⎢(VDD−|Vthp |)
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Typical input - output and load
capacitor current waveforms in a
CMOS inverter
• Low to High Transition
• τpLH =
⎞⎤
⎟⎟ ⎥
⎠⎦
⎛ 4|Vthp | ⎞⎤
⎟⎥
+ ln⎜⎜3−
VDD ⎟⎠⎦⎥
⎝
• For τpHL = τpLH , (W/L)p ≈ 2.5 (W/L)n
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Power Dissipation in CMOS Inverter
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Dynamic Power Consumption
• Dynamic Power Consumption
Charging and Discharging Capacitors
• Short Circuit Currents
Short Circuit Path between Supply Rails during Switching
E-charge = CL VDD2
• Leakage
E-discharge = ½ CL VDD2
Leaking diodes and transistors
Average Power dissipation
PAvg= 1/T CL VDD2 = CL VDD2 f
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Switching Power Dissipation in
CMOS Inverter
Switching Power Dissipation - Contd
•
•
•
•
fmax = 1/2τp
Power Delay Product,
PDP = Pavg τp
For f = fmax, PDP = CL VDD2 fmax τp
= ½ CL VDD2
Note: average switching power dissipation of a CMOS
inverter is independent of transistor sizes and
characteristics provided there is full voltage swing
• When node transition rate is slower than clock rate
• PAvg = α T CL VDD2 f
• where α T is the node transition factor (effective number
of power consuming transition per cycle)
• Energy Delay Product
EDP = PDP τp = ½ CL VDD2 τp
¾ Analysis is valid when output node of the gate
undergoes one transition (0 to VDD) in a clock cycle.
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Short Circuit Current in CMOS Inverter
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Short Circuit Current
• Short circuit current is large if output load
capacitance is low and input rise/fall time is large.
• To reduce short circuit power dissipation
¾
input/output rise and fall times should be
of same order = τ
¾ PAvg(short-circuit) = 1/12[k τ f (VDD- Vthn -|Vthp|)3]
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ReverseReverse-Biased Diode Leakage
Sub Threshold Leakage
GATE
p+
p+
N
Reverse Leakage Current
+
V
- dd
IDL = JS × A
qVbias/kT
Reverse leakage Current of a p-n junction Ireverse= A JS(e
Reverse saturation current Density JS = 10-100 pA/μm2
-
1)
at 25 deg C for 0.25μm CMOS,
JS doubles for every 9 deg C!
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Advantages of CMOS Inverter
Technology Scaling
• The high and low output voltages are equal to Vdd and
ground respectively so that the voltage swing is the
same as the supply voltage..
• The logic levels are not dependent on the relative device
sizes and hence the size of the transistors can be
minimized.
• There is always a finite resistance between the output
and either Vdd or ground in the steady state. The inverter
can, therefore, be designed to have a low input
impedance, making it less sensitive to noise.
• The CMOS inverter has a very high input resistance and
draws no dc input current as the gate of a MOS
transistor is virtually a perfect insulator.
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Constant-Voltage
Scaling
2
A/κ
κCox
Cg/κ
ηκ
κCox
Cg/κ
ηκ
κE
IDSκ
Pκ
3
PDκ
2
τ /κ
IDS/κ
2
P/κ
PD
τ /κ
L/κ
W/κ
tox /κ
Supply voltage VDD
Junction depth (Xj)
Threshold voltage (Vth)
Doping densities – ND (NA)
VDD /κ
Xj/κ
Vth/κ
NDκ (NAκ)
VDD
Xj/κ
Vth
2
2
NDκ (NAκ )
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COMPLEMENTARY CMOS DESIGN
VDD
In1
In2
PUN
PMOS Circuit
InN
In1
In2
InN
OUT= F(In1,In2,…InN)
…
Full
Scaling
2
A/κ
E
Full Scaling Constant-Voltage
Scaling
L/ κ
W/κ
tox /κ
Channel Length (L)
Channel Width (W)
Gate oxide thickness (tox)
…
Gate Area
(A = WL)
Oxide capacitance (Cox)
Gate capacitance Cg (= CoxWL)
Transconductance/Gain factor (η)
Electric field (E)
Drain current (IDS)
Power dissipation (P)
Power density ( PD = P/area)
Gate delay (τ)
Parameter
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Effects of scaling on MOS
transistor characteristics
Parameter
• Full Scaling (Constant Field Scaling)
• Constant Voltage Scaling
PDN
NMOS Circuit
Static Complementary CMOS Circuit
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COMPLEMENTARY CMOS NAND GATE
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CMOS NAND GATE
• With both input A =1, and B = 1
• PMOS pull up transistors are in cut off.
• NMOS pull down transistors create
conducting path.
• For other input combinations one of the
pull up PMOS transistors will be on and
NMOS network will be cut- off
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Lumped parameter switching model of a
two input CMOS NAND gate
CMOS NAND GATE
•Delay is dependent on
the input pattern :
tpLH =0.69 Rp/2 CL
for low to high
output transition
when both inputs
go low.
tpLH = 0.69 Rp CL
when one input
goes low.
tpHL = 0.69 * 2 Rn
CL for low to high
transition of both
inputs.
• Taking (W/L) to be same for each type of
transistors, i.e. (W/L)n,A = (W/L)n,B and
(W/L)p,A = (W/L)p,B
Vinv = [Vthn + 2 sqrt(ηp / ηn) (VDD – |Vthp|)] /
(1+ 2 sqrt(ηp / ηn))
• Assuming Vthn = |Vthp| , for Vinv = VDD/2,
one should select ηn = 4 ηp .
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¾ To have same pull-down delay as the minimum sized inverter the
NMOS devices in the PDN of the NAND gate should be twice as wide.
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CMOS TWO INPUT NAND GATE LAYOUT
4-Input NAND gate
Stick Diagram
Elmore Delay Model:
tpHL = 0.69 Rn(C1+2C2+3C3+4CL)
•Propagation delay deteriorates rapidly as a function of
fan-in – quadratically
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Layout
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CMOS NOR GATE
2-input NOR gate
• VOL = 0 and VOH =VDD
• Switching Threshold Computation
ƒ Assume (W/L) to be same for each type of
transistors, i.e. (W/L)n,A = (W/L)n,B and
(W/L)p,A = (W/L)p,B
ƒ both input voltage switch simultaneously, i.e.
VA = VB
ƒ Neglect body effect for PMOS transistors
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CMOS NOR GATE
XOR Gate
• At switching Threshold VA = VB = Vout = Vinv
• NMOS transistors are in saturation (since VGS=
VDS)
• Lower PMOS transistor (with A-input) is in linear
region, the upper PMOS (B-input) is in saturation
• Vinv = [Vthn + sqrt(ηp /4 ηn) (VDD – |Vthp|)] /
(1+ sqrt(ηp /4 ηn))
• Assuming Vthn = |Vthp| , for Vinv = VDD/2, one
should select ηp = 4 ηn .
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CMOS realization of a switching function
F = (A+D) B + CD
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Features of Complementary CMOS Design
• No static power consumption
• High noise margins :
VOH = V DD , VOL = GND
• Low output impedance
• Very high input resistance
• Logic levels independent of relative
. device sizes
of the NMOS and PMOS transistors : ratioless
•With proper sizing , rise and fall times are of
same order
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Pass Transistor
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Pass Transistor
• NMOS pass transistor :
ƒ Passes 0 (low ) well but degrades 1 (high)
ƒ Maximum value of output is VDD – Vthn
• PMOS pass transistor
ƒ Passes 1 without any degradation
ƒ Low value is degraded to Vthp
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PASS TRNASISTOR LOGIC - PROBLEMS
PASS TRANSISTOR LOGIC
• NMOS
pass transistor passes 0V(VOL) correctly,
but degrades VOH to VDD –Vthn .
•PMOS pass transistor passes 1 i.e. VDD correctly
but degrades 0 to |Vthp|
•Signal level degradation can be remedied by
insertion of a CMOS inverter or by the usage of
suitable level restoration circuits.
• When the input A is high, Q1 is turned on and
input B is copied to the output Z.
• If A is low, the pass transistor Q2 is turned on and
passes 0 to Z.
• The transistor Q2 offers low impedance path to the
supply rails even when A is low.
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•Pass transistor gates should not be cascaded
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COMPLEMENTARY PASS TRANSISTOR LOGIC
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CMOS Transmission Gate Logic
• With
CMOS transmission gates : No signal degradation
• Equivalent resistance of a CMOS transmission gate is
almost independent of the output voltage.
• Compared to the corresponding static CMOS realization the
transmission gate realization would have speed advantage.
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CMOS transmission gate realization of XOR function.
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Six transistor CMOS transmission gate realization of the XOR function.
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DYNAMIC CMOS LOGIC OPERATION
Dynamic CMOS Design
¾The circuit operates in two phases, pre-charge and
evaluation, and the mode of operation is determined by
the clock signal CLK
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DYNAMIC CMOS DESIGN ADVANTAGES
¾ When CLK = 0, the output is pre-charged to VDD by the transistor Qp.
The evaluation NMOS transistor Qe remains off during this time thus
disabling the pull-down path.
¾ For CLK = 1, the evaluation Qe is turned on while the pre-charge
transistor Qp is turned off.
¾ The output is conditionally discharged depending upon the inputs
and the topology of the PDN - if the PDN is conducting, it would offer
a low resistance path between out and the ground. On the other
hand, if the PDN is turned off, the pre-charged value will remain
stored in the output capacitance CL .
¾ Once the node out is discharged, it cannot be charged again till the
next pre-charge begins. Thus during the evaluation phase the inputs
can make not more than just one transition.
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Dynamic CMOS realization of the Boolean function F=AB+BD+CD
¾The number of transistors required is (N + 2) in dynamic
CMOS as compared to 2N for static design.
¾The dynamic design is non-ratioed. The size of the CMOS
pre-charge transistor is not important for proper realization of
the gate and hence can be increased to improve the low-tohigh transition time.
¾The dynamic gates have reduced load capacitance
because of a fewer number of transistors and hence faster
switching speeds.
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CHARGE SHARING PROBLEMS WITH
DYNAMIC LOGIC
Charge sharing in a dynamic CMOS Circuit
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Cascading problem in dynamic CMOS gates
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DOMINO LOGIC
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DOMINO LOGIC OPERATION
REFERENCES
¾A static inverter (buffer) follows an n-type dynamic logic block.
¾ Pre-charge phase: CLK=Low, output of the dynamic gate is charged up to
VDD through Qp which is ON and Inverter output is Low.
¾Evaluation phase: CLK=High, Qp turns off, inverter output can change for
Low to High depending on the inputs – if PDN conducts, dynamic gate will
discharge and inverter output will become high, else output of dynamic gate
will remain charged (high) and the poutput of domino gate will remain low.
¾The inverter output voltage can make at most one transition from 0 to 1
during the evaluation phase.
1.
2.
3.
Rabaey J. M.,Chandrakasan A., and Nikolic B., “ Digital
Integrated Circuits”, Prentice- Hall of India, 2003.
Kang, Sung-Mo and Leblebici, Y.: CMOS Digital
Integrated Circuits, McGraw Hill Pub., 2003
Weste N.H.E and Eshraghlan, K: Principles of CMOS
VLSI Design, Pearson Education, 2004.
¾The buffer output can never make 1 to 0 transition during the evaluation
phase for any combination of the input values.
¾Hence a domino gate can only implement non-inverting logic.
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