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318-595 Electronic Design
Digital Design
Jeff Kautzer
Univ Wis Milw
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318-595 Electronic Design
Review: Digital Information
• Information is represented numerically using a binary number system
 An n bit number has digit weightings 2(n-1) 2(n-2) 2(n-3) ……. 21 20
 Example: 11010b = 24 + 23 + 21 = 26
 4 bit binary “nibbles” are abbreviated using hexidecimal
 1001b = 9h, 1010b = Ah, 1011b = Bh, ….. 1111b = Fh
• Logic 1: Represented by a high voltage level and/or forward current
• Logic 0: Represented by a low voltage level and/or reverse current
• Binary numbers are conveyed individually in time between two or
more digital devices.
• Devices have electrical limitations in drive, speed, distance, & fanout
• Devices may share the same wires/nodes using time based multiplexing
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Review: Basic 2 Input Logic Operators
Gates and their Demorgan Equivalents
Note: A Bubble implies logic inversion
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Review: Basic 2 Input X-OR Operators & Gates
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Review: Truth Tables, Karnaugh Maps
N=4
Grey
Code
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Example: Binary-7Segment Display Decoder
2 Types of Display
Configurations
Vcc
Common
Cathode
LEDS
Active High
Gnd
Common
Anode
LEDS
Active Low
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7 Segment Display
7- segment used to form digits 0-9
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Commercial TTL BCD-to-7-segment decoder/driver driving a
common-anode 7-segment LED display; 7447 segment
patterns for all possible input codes.
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Truth Table for Active High (Common Cathode Display Drive)
Hex Digits A-F not defined by this decoder.
All Segments OFF
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Truth Table Reduction
• Two lines can be combined if the same output is obtained but the input
variable values differ in only 1 bit position.
• The variable for which the value differs with no effect on output is
eliminated from the resulting expression.
DCB
DCB
CBA
DCB
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Combining Adjacent Cells (Min Terms) Reduces Logic Implementation
a = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD +
ABCD + ABCD
Karnaugh Map Combinations
AC
BD
• 8 Min Terms …. 8 Input OR Gate
• Min Term = 4 Input AND Gate
(plus ~4 Inversions)
• ~ 10 Gates
ACD
CD
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Additional Segment Maps
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Liquid-Crystal Displays
Liquid-crystal display: (a) basic arrangement; (b) applying a
switching voltage between the segment and the backplane turns
ON the segment. Zero voltage turns the segment OFF.
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Commerical Logic devices for driving an LCD segments and
full 7-segment displays
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Common XOR Reduction Patterns
(Alternating Columns, Quads, and Pairs, Checkerboards)
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Digital IC Technologies/Families
• Bipolar: Utilizes BJT’s exclusively as switching
elements. Originated by Fairchild/TI, families have
included STD, L, H, LS, S, ALS, AS and F
pp74xxx###P
Standard Part Numbering Scheme
Package Suffix (Plastic, Ceramic, DIP, SOJ, etc)
Generic Device Function Number (Ex. 244 Octal Driver)
Family Designation (Ex. ALS, AS, F, etc)
7 =Commercial (0-70C), 5 =Military (-55 to 125C or more)
Mfg Prefix (Ex. SN = Texas Inst, DM = Fairchild, etc)
Example
Function/Family
Package Options
For Family Examples see:
http://focus.ti.com/logic/docs/logicportal.tsp?templateId=5985&DCMP=TI
HomeTracking&HQS=Other+OT+home_p_logic
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Review: Schottky Diode
C
• PN Junction Si Diode Similar to std diode
• Low Forward Voltage Drop (~0.3V)
B
E
Schottky Transistor
• Schottky Diode from Collector to Base of NPN
switching transistor
• Vbc < Vf of Schottky Diode (~0.3V)
• Vce-sat (schottky) > Vce-sat (std BJT)
• Base-Collector Clamp prevents hard saturation
• Switches Faster as a result
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Digital IC Technologies/Families
• CMOS: Utilizes C-MOSFETs exclusively as switching
elements. Originated with 4000 series family (still
produced) followed with C, HC, HCT, AC, ACT, FCT, LV
& LVC
• Devices follow Bipolar part numbering scheme (except
for 4000 series)
• Characterized by
-Very low input current (leakage current)
- Symmetric Output drive currents
- Device size/process scales. Industry has moved
from 5um channels to less than 100nm channels in <
30 yrs
Example: HC, HCT Families
Function/Family
Package Options
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Other Digital IC
Semiconductor Technologies
• BiCMOS: Combination CMOS/BJT. Can
be implemented using Si but SiGe becoming
popular for mixed signal applications.
Families include: BC, BCT, FBT, ABT, ALB,
& LVT
• ECL/LVDS: Emitter Coupled Logic / Low
Voltage Differential Signaling. Si BJT or
CMOS devices that utilize differential
signaling with extremely low voltage swings.
Typically seen on the output from A/D
conversion circuits. Switching speeds >
60Mhz.
• GaAs: FET based devices with extremely
fast switching and delay characteristics. Ft >
10Ghz easily achievable. Costs > 20X that of
fast CMOS
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Other Aspects of Technology:
Component Life Cycle Phases
= Mean (Max) Sales of Unit Components per Unit Time
s = One Standard Deviation in Sales/Time
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Life Cycle of a Component
• Special Histogram of Production as Measure by
Component Sales/Time (# shipped/time)
• Concept Assumes Component Sales follow
monotonically increasing to peak, then
monotonically decreasing to obsolesence
• Life Cycle is Measured Relative to Peak of Sales
•
•
•
•
•
•
+/- 1s from Peak = Mature Product
-1s to –2s from Peak = Growth Product
-2s to –3s from Peak = Introductory Product
+1s to +2s from Peak = Declining Product
+2s to +3s from Peak = Phase Out Product
+3s and higher from Peak = Obsolete Product
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Life Cycle of Common Analog IC’s as predicted in late 1990’s
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Life Cycles of IC Processes
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Life Cycles of IC Process Voltages
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Life Cycle Phases of IC Packages
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Sustainability Aspects: Obsolescence
• For each component in a BOM, consider life cycles
• Example: Consider the previous LCP Data
–
–
–
–
Type (only for analog IC’s)
Process
Package
Voltage
• For each Aspect, Find +(2.5)s, +(3.5)s dates
• Use , s in years
• +2s to +3s from Peak = Phase Out Product
• +3s and higher from Peak = Obsolete Product
• Find worst case values (earliest of the four categories)
• Create a separate IC BOM table of obsolescence analysis
with above data
• ID all parts above the 2.5s, Separately ID all above 3.5s
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Obsolescence Table Example
• Sample calculations for a few suspect IC’s (Present Date p = 2000.8)
• In this case, the present date was subtracted from the window points and
any negative value means there is a potential issue
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Logic Signal Electrical Characteristics
• Finite Transition Time Zone
Driver must switch voltage thru
this zone within specified time or
risk causing linear operation of
receiver !
Typically < 1uS but varies with
logic family technology
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Logic Device Drive Parameters
Note: Sourced currents are always listed as a negative number by convention on data sheets
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Interpreting the Data Sheet
Vih, Vil
Ioh, Iol
Voh @ Ioh (note max Ioh)
Vol @ Iol (note max Iol)
Iih, Iil
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Device Output Structure Type 1: Totem Pole
Current Limiting Resistor
(reduced in modern devices)
Top Voh/Ioh Source Driver
(Switch to Vcc)
Bottom Vol/Iol Sink Driver
(Switch to Gnd)
Cross-over of Q4:Q5 – ON/OFF
may result in high current spike
from Vcc to Gnd
Octal and larger devices rated
for “Gnd Bounce” Volp.
Measure of Static output
disturbance when all other
outputs switch simultaneously.
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Device Output Structure Type 2: Open Collector/Drain
Current Limiting Resistor Removed
Top Voh/Ioh Source Driver Removed
Bottom Vol/Iol Sink Driver
Sink Trans Q5 acts as a switch to Gnd
No inherent Logic 1 voltage drive
Interface in 2 ways;
Note OC/OD Datasheets:
• Pullup resistor to Vcc to establish
logic 1 voltage level
May list Vce-sat for Vol, Ic max for Iol
max, Vce max (off).
• Switch current through load device
(Ex. Relay Coil, LED, Lamp, Solenoid,
etc)
Will NOT list Voh, Ioh values !
OC/OD Outputs will have very slow Logic 0 to 1 transition times !
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OC/OD outputs may be tied together, Wire-OR
Determining Pullup Resistor Limits
• Maximum R - Limited by Logic 1 condition: R must supply Vih @
Iih to receiver plus supply any leakage current to the driver OFF
transistors. Finite Current of Io flows thru R dropping voltage.
Usually use R < 100KW
• Minimum R - Limited by Logic 0 condition: Driver ON may cause
Vol as low as 0V, Driver must sync Io from Vcc thru pullup resistor
plus Iil source current from receiver. Total load current cannot
exceed Driver Iol current capacity. Usually use R> 1KW
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Device Output Structure Type 3 Tristateable
Current Limiting Resistor
(reduced in modern devices)
Top Voh/Ioh Source Driver
(Switch to Vcc)
Bottom Vol/Iol Sink Driver
(Switch to Gnd)
Q7/Q8 used to stop base
current to Q3/Q4 darlington
Turn off Source Driver
Q2 used for same purpose but
controls Sink Driver
E turns OFF Q4 and Q5
simultaneously
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Interpreting the Data Sheet
Vcc Supply Voltage Range
Normal Input Specs apply to Enable
Input (G)
Off State Output Leakage Currents
Logic Level Dependent
Icc Max Supply Current
Note: Occurs when outputs in Hi Z
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Multiplexing Drivers for Bus Operation
• Active Driver must provide
Iih/Iil currents to ALL receivers
plus all the OFF state leakage
currents of the other inactive
Drivers
• Must NOT have 2 or more
Drivers Active simultaneously.
Time Division multiplexing
(timing) analysis critical to long
term reliabililty of devices
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Standard vs Schmitt Trigger Input Functions
• Single Input Threshold Vth, Eliminates Undefined Transition Zone
• Input should also have minimum “hysteresis” to provide noise immunity
 As Vin increases thru Vth, Vth decreases by DV (Vhyst)
 As Vin decreases thru Vth, Vth increases by DV (Vhyst)
• Vth is typically 1.0 – 2.0 V, Vhyst should be > 200mV
• Schmitt Trigger should always follow OC/OD outputs or other slow rise
or fall time signals (Ex. Optocoupler Outputs, RC Reset Circuits, etc )
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Basic Combinatorial Timing Parameters
• TpHL(TpLH): Propagation Delay from High to Low (Low to High) Logic Level
Usually measured between the 10% and 90% total voltage transition points.
• Tpd or Tp: Propagation Delay usually stated as worst case of TpHL and TpLH.
• Tott or Tout: Output Transition Time. For many families (HC, HCT, etc), gate delays
are stated with separate specifications for logical output value generation (Tpd) plus
physical output voltage transition (Tott). Need to sum these for total prop delay !!
• TpzH(TpzL): Propagation Delay from High Impedance to High (Low) Logic Level
• TpHz(TpLz): Propagation Delay from High (Low) Logic Level to High Impedance
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