Download Input Offset Voltage

FILENAME: OPERATIONALAMPLIFER.DOC
DILLIAN WONG 03906165D
2017/5/6
THE HONG KONG POLYTECHNIC UNIVERSITY
Department of Electronic and Information
Engineering
EIE303
ELECTRONIC CIRCUIT II
(Laboratory report)
EN033
CHARACTERISTICS OF AN OPERATIONAL AMPLIFIER
STUDENT NAME:
STUDENT NO:
COURSE NO.:
WONG TANG PAAI
03906165D
42070- YR 2
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FILENAME: OPERATIONALAMPLIFER.DOC
DILLIAN WONG 03906165D
2017/5/6
CONTENT
1. TITLE
2. OBJECTIVE
3. APPARATUS
4. INTRODUCTION
5. THEORETICAL BACKGROUND
6. PROCEDURE
7. DATA MEASUREMENT AND ANALYSIS
8. FINDING
9. CONCLUSION
10. REFERENCE
◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆
1. TITLE
Characteristics of an Operational Amplifier
2. OBJECTIVE
To
1.
2.
3.
4.
5.
measure the
Input offset voltage
Input bias current
Common-mode rejection ratio (CMRR)
Slew rate
The peak output voltage swing
3. APPARATUS
1.
2.
3.
4.
5.
6.
Operational amplifier characteristics measurement circuits.
Operational amplifier (741)
Oscilloscope
Sine/Square wave generator
Digital multimeter
Twin DC power supply (0-18V variable)
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4. INTRODUCTION
The steady-state output of an ideal op-amp negative-feedback circuit is zero when the input
is zero. However, the practical op-amp output will have some dc voltage when the input is
zero. This output voltage is call output offset and it is an error voltage that is undesirable.
Output offset is due to two sources, one is input bias current, the other is input offset
voltage.
The input bias current of the amplifier is used for the biasing of the differential input-stage
transistors. The input offset voltage is the differential input voltage that must be applied
across the input of the op-amp in order to force the output voltage to zero. The output offset
voltage is caused by the mismatching between two input terminals.
Op-amp amplify mainly the difference between the signal applied to the two input terminals.
Due to components mismatches and nonidealities in current sources, op-amp also amplify
common-mode signals. Thus the output of the op-amp consists two parts, one is the
differential output and other is the common output. Usually, the common-mode gain is
much less than the differential-mode gain. The ratio of the differential-mode gain to the
common-mode gain is the common-mode rejection ratio (CMRR). For a ideal op-amp, it
should be infinite.
If a large-signal square wave is put into the input of an op-amp, there is a maximum speed
at which the output voltage can swing. The maximum rate of change in the output voltage is
called the slew rate. Slew rate determine the maximum undistorted output voltage. Slew
rate is caused by current limiting and the saturation of internal stage of an op-amp when a
high frequency, large amplitude signal is applied. The capacitor in the op-amp requires a
finite amount of time to charge and discharge. It will limit the speed of response of the
output.
Voltage clipping is the distortion in the op-amp output caused by the limiting of the
maximum output voltage of the op-amp. The maximum peak output voltage swing is limited
to approximately one volt less than the power-supply voltages.
5. THEORETICAL BACKGROUND
INPUT OFFSET VOLTAGE
This is the differential d.c. input voltage VOS required to provide zero output voltage with no
signal and at zero source resistance. Hence the internal offset at the amplifier input is VOS
and the standard circuit used for measuring VOS is shown in Fig.1 from which it can be
shown that
R1
VOS  
Vo …………………………………(1)
R1  R f
Where VO is the d.c. output voltage.
INPUT BIAS CURRENTS
Small but non-zero bias currents are present at the inputs to an operational amplifier. These
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currents can be measured using the circuit switch S1 open and S2 closed the input bias
current to the inverting terminal is forced to flow through the large 10MΩ resistor Rg and the
corresponding d.c. output voltage is VO = IB1Rg. Similarly when S2 is open and S1 is closed VO
= IB2Rg. and for both S1 and S2 open VO=(IB1-IB2)Rg. The Input offset current IOS is defined
as IOS = (IB1- IB2).
COMMON MODE REJECTION RATION (CMRR)
The common mode rejection ratio (CMRR) is defined as CMRR = Ad/Ac where Ad and Ac are
the difference mode and common mode gains respectively. The circuit shown in Fig.4. is
employed for measuring the CMRR. The voltage between the inverting terminal and
non-inverting terminal is
Vd=V1 – V2 …………………………………(3)
For superposition, the voltage V1 is
R2
R1
V1  VS
 VO
R1  R2
R1  R2
and it can be shown that
R2
V2  VS
R1  R2
R1
Vd  V1  V2  VO
…………………………………(4)
R1  R2
let Vc = Common-mode voltage,
V  V2
R2
R1
 VS
 VO
then VC  1
2
R1  R2
( R1  R2 )2
VO  AdVd  ACVC  AdVO
R1
R2
R1
 AC (VS
 VO
)
R1  R2
R1  R2
( R1  R2 )2
as R1=100Ω, R2=100kΩ
R1
VO  AdVO
 ACVS
R1  R2
Ad
V
R1
 1  AC S
R1  R2
VO
Ad R1  R2 VS

AC
R1 VO
CMRR  1001
VS
 (6)
VO
6. PROCEDURE
(1) Connect up the circuit shown in Fig.1 and measure the d.c. Output voltage. The input
offset voltage is found from equation (1).
(2) Use the circuit shown in Fig.2 and measure the d.c. Outputs voltages in each of the
following cases:
S1 is open and S2 is closed.
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S2 is open and S1 is closed
S1 and S2 are both open
From these outputs determine IB1, IB2 and IOS from the theory outlined in section (b)
(3) Connect up the circuit shown in Fig.4 and set the input voltage VS to 5Vp-p. Measure the
output voltages at frequencies: 10Hz, 100Hz, 1kHz, 10kHz
Determine the corresponding CMRRs using equation (6)
(4) Apply an 8kHz square-wave pulse train to the input of the circuit shown in Fig.5, and set
Vcc=15V. Adjust the magnitude of the input pulses until the output saturates on both
the positive and negative output voltage swings. Measure the slopes of the linear
regions corresponding to the positive and negative voltage swings for both the rise and
fall regions of the output voltage. The lowest slope is the slew rate and is usually
expressed in (Volts/μsec).
(5) Apply a 1kHz signal to the input of the circuit shown in Fig.5 and adjust its magnitude
until clipping of the output voltage is observed.
Measure the corresponding peak to peak values of the output voltages at the onset of
clipping for Vcc = 6V, 9V, 12V, 15V and 18V respectively and plot these voltages as a
function of Vcc. The loading is provided by the 10kΩ feedback resistor.
7. DATA MEASUREMENT AND ANALYSIS
(1) DETERMINATION OF THE INPUT OFFSET VOLTAGE
The input offset voltage is the differential voltage the supplied across the input of the
op-amp. Apply no input to the op-amp, we find the output with dc voltage is :
VO=-0.82V (by measure)
R1
 100
Vo 
(0.82)  819V .
Thus we have input offset voltage VOS  
R1  R f
100  100k
When this voltage is apply to the non-inverting input, we output will be forced to zero
voltage.
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(2) DETERMINATION OF THE INPUT OFFSET CURRENT
S1 is open and S2 is closed.
Non-inverting input is grounded; assume the differential input signal is virtually zero for
any output voltage. We have
VO = IB1Rg., where IB1 is inverting bias current
By measure we find
VO =0.385V
ie
IB1= 0.385/10M = 38.5nA
S2 is open and S1 is closed
Inverting input is equal the output voltage; non-inverting input thus also equal the
output voltage with sign negative. This time we have
VO = -IB2Rg., where IB2 is non-inverting bias current
By measurement we find
ie.
VO =-0.395V
IB2= -0.395/10M = -39.5nA
/*
VO = (IB1- IB2)Rg.
V
 0.395
I B 2  I B1  O  38.5n 
 77nA
Rg
10M
I OS  I B1  I B 2  38.5n  77n  38.5nA
*/
S1 and S2 are both open
In this case, we can consider the combination of two the above cases, (S2 is open and
S1 is closed, S1 and S2 are both open). By superposition, we have
VO = (IB1- IB2)Rg.
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By measure we find
VO  0.01V
V
 0.01
I OS  O 
 1nA
Rg
10M
ie.
Input offset current IOS = 1nA.
(3) COMMON-MODE REJECTION RATIO
Set the input voltage VS = 5Vp-p fixed, change the signal frequency and record the
corresponding output voltage. Using the equation derived in previous section to calculate
the common-mode rejection ratio.
V
CMRR  1001 S
VO
By measurement, we have where (VS = 5Vp-p )
Frequency(Hz)
VO(p-p)
CMRR
10
2
2502.5
100
1.7
2944.1
1k
1.6
3128.1
10k
1.4
3575
From the list we find the CMRR will increase with the increase of the input frequency. Which
is in contrary of the normally result. The reason is the circuit configuration difference in two
cases; normal case and this experiment case.
The CMRR will decrease if there is no feedback path. The differential voltage frequency
increase and it differential-mode gain will decreases, because of the internal compensation
capacitor need a finite time to charge up and discharge. The common-mode output voltage
approximately equal in both high and low input frequency, as the cause of the
common-mode output voltage is due to the finite voltage in emitter junction of the
differential voltage amplifier in the IC 741 input stage. Thus, the CMRR will decrease with
the increase of the input frequency in case of no feedback circuit.
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In the circuit illustrate in Fig4, the feedback circuit is included. It will expand the bandwidth
of the amplifier, and the external feedback circuit in this case determines the gain of the
amplifier. The gain of the amplifier is largely reduced, and the slew rate (the rate of change
of output voltage in a unit of time) keeps uncharged, thus it provides more time for the
internal capacitor of the 741 to operates. Output voltage should lesser reduced with the
increasing of the frequency. Because of the CMRR in this case is a function of the external
resistance. By the derivation of the CMRR equation, we see the output decrease the CMRR
will increase. To sum up, CMRR increase with frequency is because of the feedback circuit.
(4) DETERMINATION OF THE SLEW RATE
Apply a large square wave signal to the input of an op-amp, there is a maximum rate of
change of the output voltage swing. Adjust the magnitude of the input signal until the
output have the maximum swings. Slew rate is the change of voltage with respect to time.
by measure, I find the output voltage draw above. The slew rate is the slope of the output
swing in the linear regions.
ie.
slew rate = 15/28μ = 0.51V/μs
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(5) EFFECT OF THE VOLTAGE CLIPPING
Voltage clipping is the distortion in the op-amp output caused by the limiting of the
maximum output voltage of the op-amp. Apply a 1kHz signal to the input of the circuit above.
Set the difference values of the supply voltage, adjust the magnitude of the input signal that
we have a maximum swing in the output.
By measurement, we have
Vcc
Vi(p-p)
VO(p-p)
6V
1.4V
5V
9V
2V
15V
12V
2.2V
22V
15V
3.7V
28V
18V
4V
34V
MATHLAB SCRIPT
>>
>>
>>
>>
>>
>>
>>
VCC=[6,9,12,15,18]
VO=[5,15,22,28,34]
plot(VCC,VO)
xlabel('VCC/V')
ylabel('VO/V')
Title('The peak ouput voltage swings')
grid
From the graph above, we find the maximum output voltage will be limited by the supply
voltage. For large supply voltage, there is a large output voltage swing.
8. FINDING
In this experiment, the measurement result of operational amplifier is listed as following
Op-amp characteristics
Input offset voltage
0.8mV
Input bias current
39nA
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Input offset current
1nA
Slew rate
0.51V/μs
2017/5/6
(Not make sense)!!!!!! Should be 20nA
9. CONCLUSION
The effect of the input offset voltage, will causes the op-amp not ideal for a wide range of
difference input signal. To eliminate the effect, we need a extra circuit to compensate the
effect. However, the input offset voltage for the same type of op-amps may not be the same
in amplitude and polarity. The mass production of the op-amp cannot assure the same input
offset voltage. It causes the circuit designed more complex. To reduce the output offset
voltage, we need to have circuit at the input terminal. This will give the input offset voltage
to the input and produce the zero output voltage. Some Op-amp may contain the offset null
pin for the user to adjust the output offset voltage. It is a compensation network contains a
variable resistor. By varying the values of the resistance, it is trying to remove the mismatch
between inverting and non-inverting input terminals of the op-amp. When the output
voltage is zero; the op-amp is then said to be nulled or balanced.
Consider the circuit in Fig 5, assume the op-amp is ideal; that is CMRR = infinite, Gain =
infinite and input offset voltage equal to zero. By measure, we have IB1 = 38.5nA. Because
the two input of the op-amp is virtually grounded. V0 = IB1 x 10kΩ = 38.5n x 10k = 0.385mV
When the operating frequency is increased the CMRR of the operational amplifier normally
decreases; but the results in experimental procedure show the contrary. The reason is the
circuit configuration difference in two cases; normal case and this experiment case.
The CMRR will decrease if there is no feedback path. The differential voltage frequency
increase and it differential-mode gain will decreases, because of the internal compensation
capacitor need a finite time to charge up and discharge. The common-mode output voltage
approximately equal in both high and low input frequency, as the cause of the
common-mode output voltage is due to the finite voltage in emitter junction of the
differential voltage amplifier in the IC 741 input stage. Thus, the CMRR will decrease with
the increase of the input frequency in case of no feedback circuit.
In the circuit illustrate in Fig4, the feedback circuit is included. It will expand the bandwidth
of the amplifier, and the external feedback circuit in this case determines the gain of the
amplifier. The gain of the amplifier is largely reduced, and the slew rate (the rate of change
of output voltage in a unit of time) keeps uncharged, thus it provides more time for the
internal capacitor of the 741 to operates. Output voltage should lesser reduced with the
increasing of the frequency. Because of the CMRR in this case is a function of the external
resistance. By the derivation of the CMRR equation, we see the output decrease the CMRR
will increase. To sum up, CMRR increase with frequency is because of the feedback circuit.
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10. REFERENCE
1.
Op-amps and linear integrated circuits, Fourth Edition, Ramakant A. Gayakwad,
Prentice-Hall
2.
Understanding IC operational amplifer, Roger Melen and Harry Garland, Howard W.
Sams & Co, Inc
3.
Linear Electronic circuits and systems, G.D.Bishop, The Macmillan press LTD
4.
Lecture Note of Electronic circuit II, Prof. Michael Tse, Polytechnic university.
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