Download presentation

A 3GHz Switching DC-DC Converter
Using Clock-Tree Charge-Recycling
in 90nm CMOS
with Integrated Output Filter
Mehdi Alimadadi, Samad Sheikhaei,
Guy Lemieux, Shahriar Mirabbasi, Patrick Palmer
University of British Columbia (UBC)
Vancouver, BC, Canada
Motivation
• Power-limited CPU performance
– Trend: > 4 CPU cores on one chip
• Solution?
P  C  f V
2
– Dynamic Voltage and Frequency Scaling (DVFS)
- Each core scaled differently based on load
– Need multiple supply voltages on-chip
2
Motivation
• How to supply multiple voltages?
Our approach …
– Global voltage distribution (high Vdd)
– Local voltage regulation (on-chip, low Vdd)
Support for …
– Coarse-grain voltage islands (e.g., CPU cores)
– Fine-grain voltage islands (e.g., ALU, FPU, …)
 On-chip “local” voltage regulation
3
Problem Definition
• On-chip “local” voltage regulation
• Constraints
– On-chip components, “standard” CMOS
– Scaled down voltage  buck converters
• Shrink L, C to fit on-chip
– Efficiency trade-off
• Local regulator consumes power
• Local regulator saves power by DVFS

 consumption < savings
4
Summary Results
• On-chip DC-DC buck (step-down) converter
– Standard 90nm CMOS
– 1V input, 0.5~0.7V output, 100mA
– Up to 158% effective efficiency
• Over 100% !!!???
– By recycling charge thrown away in clock tree
• High-speed operation
– 3GHz CPU clock  3GHz buck converter
• Monolithic L and C (converter area 0.27mm2)
– Unique ZVS delay circuit improves efficiency
5
Switch Mode Power Supply
• CMOS inverter as power switches in buck
converter
Vdd
Vgate
Vinv
Vin +
-
S
D
L
IL
S
Vout
C
Vgate
Vinv
R
L
IL
Vout
C
R
D
6
Clock and SMPS Merging
• CPU clock: 3GHz clock and large Cclk
CLK in
Vclk
CLK in
Vclk
Cclk
Cclk
• SMPS: large Mp, Mn drive chain
Mp
CLK in
CLK in
Mp
Lf
Lf
Vout
Cf
Mn
Cf
Vout
Rload
Rload
Mn
7
Clock and SMPS Merging
• Combine the driver circuits
CLK in
Vclk
Cclk
Mp
Lf
CLK in
Vout
Cf
Rload
Mn
8
Key Contribution: CHARGE RECYCLING
CLK in
Vclk
Cclk
• Benefits
– Shared driver chain
– Cclk added to SMPS
Lf
Vout
Cf
Rload
• Note: NMOS drains Cclk, wastes charge!
• Delaying NMOS  ZVS recycles clock charge!
9
ZVS Detailed Operation
• ZVS delay circuit D
– Delay only rising edge of Vn
– Implemented inside the clock chain
Vdd
Vp
Mp
Lf
Vclk
Cclk
Vn
Vout
Cf
Rload
Mn
GND
10
ZVS Detailed Operation (Mode 1)
• Mode 1 (0 < t < DTsw)
D = Duty cycle
Tsw = Switching period
– Mp is ON
– Current builds up in the inductor
– Cclk charges up
Vdd
Vp
Mp
Lf
Vclk
Cclk
Vn
Vout
Cf
Rload
Mn
GND
11
ZVS Detailed Operation (Mode 2)
• Mode 2 (DTsw < t < DTsw+Tzvs)
D = Duty cycle
Tsw = Period
Tzvs = ZVS delay
– Both power transistors are OFF
– Inductor current discharges Cclk
– Cclk charge is recycled to output load
Vdd
Vp
Mp
Lf
Vclk
Cclk
Vn
Vout
Cf
Rload
Mn
GND
12
ZVS Detailed Operation (Mode 3)
• Mode 3 (DTsw+Tzvs < t < Tsw)
D = Duty cycle
Tsw = Period
Tzvs = ZVS delay
– Mn turns ON when Vclk  0
• ZVS for Mn
– Inductor current decreases linearly
Vdd
Vp
Mp
Lf
Vclk
Cclk
Vn
Vout
Cf
Rload
Mn
GND
13
Detailed Operation
• ZVS delay circuit for Mn
– Delay rising edge of Vn
M3
Vdd
1
2
Vm
Vp
Mp
M4
3
Lf
Vclk
Cclk
Vout
Cf
Rload
M1
4
Vn
ZVS
Delay
Circuit
Mn
GND
M2
14
Detailed Operation
• Adaptive ZVS delay circuit for Mn
– Falling edges of Vp and Vn are synchronized
M3
Vdd
1
2
Vm
Vp
Mp
M4
Lf
Vclk
Cclk
Vout
Cf
Rload
M1
2
Vn
ZVS
Delay
Circuit
Mn
GND
M2
15
Implementation
• Chip 1mm2, converter 0.27mm2
16
Implementation
• Charge recycling of the clock tree capacitor
Combined SMPS
+ clock circuit
CLK in
Vclk
Lf
Cclk
Vout
Cf
Rload
Circuit 1, Pin1, Pout1
Reference clock circuit
CLK in
Circuit 2, Pin2
Cclk
17
Power Conversion Efficiency
Pout1 = output power (delivered to load)
Pin1 – Pin2 = incremental power to operate SMPS only
Pin1 = power of combined SMPS + clock circuit
Pin2 = power of reference clock circuit
160
140
Percent (%)
•
•
120
Efficiency (effective)
100
effective 
80
Pout1
 100
Pin1  Pin2
60
40
raw 
Efficiency (raw)
20
20
40
60
80
I out (mA)
100
Pout1
 100
Pin1
120
18
Comparative Results
This Work
[JSSC05]
[ISSCC06]
Buck
4-Phase Buck
2-Phase Buck
90nm CMOS
90nm CMOS
0.18µm SiGe
RF BiCMOS
3000
233
45
1.0
1.2 to 1.4
2.8
0.5 to 0.7
0.9 to 1.1
1.5 to 2
40 to 100
300 to 400
200
158 % (Vout=0.7V)
98 % (Vout=0.6V)
80 % (Vout=0.5V)
84 %
65 %
Filter inductor, Lf (nH)
0.32
6.8 (per phase)
11 (per phase)
Filter capacitor, Cf (pF)
350
2500
6000
On-chip
Off-chip L
On-chip
0.27
0.14 (excl. L & C)
27
Type
Technology
Switching freq, Fsw (MHz)
Input voltage, Vin (V)
Output voltage, Vout (V)
Output ripple (%-pp)
Output current, Iout (mA)
Effective efficiency
eff (%)
Off/on chip Lf, Cf
Converter area (mm2)
< 5 % (Vout=0.7V)
19
Contributions
• Key concepts
–
–
–
–
High switching frequency  saves area
Combined drivers  saves area and switching loss
Recycled charge  converter load discharges Cclk
Unique ZVS delay circuit  lower power loss
• Limitations
– Regulation needs variable duty cycle clock
• May introduce additional clock jitter
• Mostly suitable for edge-triggered blocks
(no latches)
20
References
[JSSC05] P. Hazucha, G. Schrom, H. Jaehong, B. A. Bloechel, P.
Hack, G. E. Dermer, S. Narendra, D. Gardner, T. Karnik, V.
De, and S. Borkar, “A 233MHz 80%-87% Efficient FourPhase DC-DC Converter Utilizing Air-Core Inductors on
Package,” IEEE J. Solid-State Circuits, vol. 40, pp. 838845, Apr., 2005.
[ISSCC06] S. Abedinpour, B. Bakkaloglu, and S. Kiaei, “A Multi-Stage
Interleaved Synchronous Buck Converter with Integrated
Output Filter in a 0.18µm SiGe Process,” ISSCC Dig. Tech.
Papers, pp. 356-357, Feb., 2006.
21