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Transcript
Technical Explanation SEMITOP® Revision: 03 Issue date: 2015-10-14 Prepared by: Marco Di Lella Approved by: R.Ramin, V.Demuth Keyword: SEMITOP, technical explanation, one screw mounting, no baseplate, pins for soldering, press-fit pins, 12mm height, flexibility, low inductance design, thermal paste, assembly, torque, washer, screw, heatsink, datasheet, laser marking, packaging, label, data matrix, RoHS, ESD, reliability 1 Introduction ...............................................................................................................................3 1.1 SEMITOP® key-features .........................................................................................................3 1.2 Customer advantages and benefits ..........................................................................................3 1.3 SEMITOP® news: Press-Fit terminals for solder free assembly to the PCB .....................................4 2 SEMITOP® Technical details .........................................................................................................5 2.1 Mechanical construction .........................................................................................................5 2.1.1 Tolerance system ............................................................................................................5 2.2 Product portfolio ...................................................................................................................7 2.3 Chip technologies ................................................................................................................ 10 2.4 SEMITOP® type designation system ....................................................................................... 11 3 Chip technologies and optimized operation frequency ................................................................... 12 3.1 IGBT technology characteristics ............................................................................................ 13 3.1.1 600V and 650V IGBTs.................................................................................................... 13 3.1.2 1200V IGBTs ................................................................................................................ 14 3.2 MOSFETs technology characteristic ........................................................................................ 16 3.2.1 Si MOSFETs .................................................................................................................. 16 3.2.2 SiC MOSFETs ................................................................................................................ 16 3.3 Inverse and Free-wheeling diodes ......................................................................................... 17 3.3.1 SEMIKRON CAL diodes ................................................................................................... 17 3.3.2 Fast switching diodes..................................................................................................... 17 3.4 Chip operating areas............................................................................................................ 18 3.4.1 IGBT Safe Operating Area (SOA) for turn-on and single pulse operation............................... 18 3.4.2 IGBT Reverse Bias Safe operating area (RBSOA) for periodic turn-off .................................. 19 3.4.3 IGBT Short Circuit Safe operating area (SCSOA) for non periodic turn-off of short circuits ...... 19 3.4.4 MOSFET Safe Operating Area (SOA) for single pulse operation ............................................ 20 3.4.5 Surge current characteristic of CAL diodes........................................................................ 21 4 SEMITOP® technology ............................................................................................................... 22 4.1 Baseplate-less basic technology ............................................................................................ 23 4.2 Thermal material data ......................................................................................................... 25 4.3 Definition and measurement of Rth ....................................................................................... 26 4.3.1 Test setup .................................................................................................................... 27 4.3.2 Principle of Rth measurement .......................................................................................... 27 4.3.3 Transient thermal impedance Zth .................................................................................... 27 4.4 Specification of the integrated temperature sensor .................................................................. 29 4.4.1 Electrical characteristic (NTC) ......................................................................................... 29 4.4.2 Electrical characteristic (PTC) ......................................................................................... 30 4.4.3 Electrical isolation ......................................................................................................... 31 5 Assembly instructions ............................................................................................................... 32 5.1 Heatsink specification .......................................................................................................... 32 5.2 Mounting surface................................................................................................................. 32 5.3 Assembling steps ................................................................................................................ 35 5.3.1 SEMITOP® with soldered terminals .................................................................................. 35 5.3.2 SEMITOP® with Press-Fit pins ......................................................................................... 36 5.3.3 Mounting process outline ............................................................................................... 36 © by SEMIKRON / Technical Explanation / SEMITOP® / 2015-10-14 PROMGT.1026/ Rev.3/ Template Technical Explanation Page 1/65 5.4 Thermal grease application ................................................................................................... 37 5.4.1 Standard thermal grease specification ............................................................................. 37 5.4.2 Pre-applied thermal paste specification ............................................................................ 37 5.5 Assembling on heatsink ....................................................................................................... 38 5.6 Matching SEMITOP® and the PCB .......................................................................................... 39 5.6.1 SEMITOP® with soldered terminals .................................................................................. 39 5.6.1.1 Soldering on PCB .......................................................................................................... 39 5.6.2 Connecting the PCB via press-fit pins............................................................................... 41 5.6.3 PCB starter kit .............................................................................................................. 44 5.6.3.1 Demo PCB board for GD topology, SEMITOP®4 soldered terminals ...................................... 44 5.6.3.2 Demo PCB board for DGDL topology, SEMITOP®4 soldered terminals ................................... 44 5.7 ESD protection .................................................................................................................... 45 6 Technologies ............................................................................................................................ 45 6.1 Principle of Press-Fit technology ............................................................................................ 45 6.2 Pin current capability ........................................................................................................... 46 6.2.1 Soldered terminals current capability ............................................................................... 46 6.2.2 Press-fit pins current capability ....................................................................................... 47 6.3 Tin whisker formation .......................................................................................................... 47 6.4 Thermal interface materials .................................................................................................. 48 7 Restriction of hazardous substances in electrical and electronic equipment (RoHS) ........................... 50 8 Laser marking .......................................................................................................................... 51 9 Packaging specification.............................................................................................................. 51 9.1 Packing box ........................................................................................................................ 51 9.2 Marking of packing boxes ..................................................................................................... 52 9.3 Storage and shelf life conditions ............................................................................................ 53 10 Reliability ................................................................................................................................ 54 10.1 Qualification test and special test .......................................................................................... 54 10.2 Lifetime calculation.............................................................................................................. 56 11 Support ................................................................................................................................... 58 11.1 Customer specific power modules .......................................................................................... 58 11.2 Add-on services .................................................................................................................. 59 11.3 SEMISEL simulation software ................................................................................................ 60 12 Caption of figures ..................................................................................................................... 61 13 Caption of tables ...................................................................................................................... 62 14 Caption of equations ................................................................................................................. 62 15 Symbols and Terms .................................................................................................................. 63 16 References .............................................................................................................................. 64 17 History .................................................................................................................................... 65 18 Disclaimer ............................................................................................................................... 65 © by SEMIKRON / Technical Explanation / SEMITOP® / 2015-10-14 Page 2/65 1 Introduction SEMITOP® was introduced in the market in the late 90’s with a few configurations, mainly single phase inverters, bridge rectifiers and thyristors. SEMITOP® is now a complete module family with four different housing sizes in order to fulfill the new application goals where performances, reliability, integration and costs are a must. 1.1 SEMITOP® key-features The most flexible module family: same electrical configuration can fit different housings according to the increasing current rating for a complete product line covering a continuous current up to 300A, 55kW output power PCB interface flexibility: SEMITOP® can be connected up the PCB via soldered terminals or press-fit pins. Two alternative interface solutions to meet customers’ process needs Excellent thermal management due to DBC ceramic without baseplate: this allows low operating temperatures and ensures high product lifetime Only one mounting screw for a fast and reliable assembly to the heatsink 12mm height module High insulation degree: 2.5kV/AC/1min, 3kV/AC/1s at 50Hz Dedicated to your application: 70 different topologies are today available for standard and customized solutions thus creating the most comprehensive configuration portfolio: CIBs, sixpacks, input bridge rectifiers, AC switches, PFC topologies (buck, boost, double boost, interleaved solutions), single arm of three-level inverter (NPC and TNPC types) and many custom solutions for different final applications Drives, UPS, solar, welding are the main SEMITOP® target markets for a power range up to 55kW Compact size for extremely reduced stray inductance patterns Integration of the latest chip technologies possible: fast IGBT technologies, fast switching diodes, MOSFET for high voltage, Silicon Carbide (later named SiC) Diodes and MOSFETs. 1.2 Customer advantages and benefits SEMITOP® is a module without baseplate, made by direct soldering of chips and power terminals on a ceramic substrate. The ceramic substrate is packaged with a plastic housing and the whole assembly is then fixed to the heatsink by a single mounting screw. Faster assembly process is therefore achieved compared to two lateral mounting screws. The single central mounting screw provides an even pressure distribution which guarantees low thermal resistance resulting in low junction temperature and high reliability. The product is today offered with two optional PCB interface connections: solder terminals or press-fit technology. Customers can therefore choose the right terminals to interface in order to optimize their production process and achieve fast time to market. Press-fit technology is the alternative solution to solder mounting and easy switch from soldered to solder free assembly to the PCB is possible thanks to the 100% pinout compatibility. Pins on the edges make PCB routing simple allowing for more internal space to fit the most complex topologies inside a very compact space. This extremely flexible architecture with a low inductance design approach, coupled with the latest Si and SiC chip technologies, make SEMITOP® the suitable platform to offer also customer specific solutions to achieve the new challenging requirements in different applications. Multiple paralleling on the same PCB is possible thanks to the 12mm height compatibility thus reducing the development time of the whole assembly and improving the time to market. © by SEMIKRON / Technical Explanation / SEMITOP® / 2015-10-14 Page 3/65 1.3 SEMITOP® news: Press-Fit terminals for solder free assembly to the PCB Latest market trends, especially in the UPS and solar application in the low-medium power range, highlighted the need for power modules with a more simple assembly process to the PCB. The new SEMITOP® Press-Fit version offers the following benefits: No solder equipment needed Reduced production time Assembly of module and driver in one step at room temperature Possibility for fast disassembly and re-use of power module or PCB SEMITOP® Press-Fit is a 100% compatible platform with SEMITOP® soldered version with the following characteristics: still 12mm height module same electrical and thermal performances of the soldered version same pinout of the existing SEMITOP® configurations; no need to change the PCB routing same consolidated production process assembly still one mounting screw module that reduces the assembly time respect to the competitors that offer two mounting clips more homogeneous pressure distribution for high thermal performances same consolidated and proved mounting procedure to the heatsink of the existing SEMITOP® The SEMITOP® Press-Fit is available inside SEMITOP®2,3,4 housings; target markets are UPS, solar, motor drives and welding. Figure 1: SEMITOP® Press-Fit family (left) and one single step PCB assembly concept (right) SEMITOP®4 SEMITOP®3 SEMITOP®2 All three housings have been tested according to the standard SEMIKRON qualification program with positive results. The platform is therefore released for mass production stage. More details about the Press-Fit pin technology can be found in the next sections and in the dedicated mounting instruction documentation available in the web. © by SEMIKRON / Technical Explanation / SEMITOP® / 2015-10-14 Page 4/65 SEMITOP® Technical details 2 SEMITOP® comes into the market in four different mechanical sizes and three different product lines: IGBT, DIODE & THYRISTOR and MOSFET (for low and high voltages). Both terminals for soldering and press-fit technology are available for any configuration. The whole SEMITOP® family is based on the same design concept and it is produced in the same production lines. The different mechanical sizes can be mixed in the same application since the SEMITOP® platform is a fully compatible 12mm height platform. 2.1 Mechanical construction SEMITOP® construction is quite simple. The chips are soldered to the ceramic substrate, and they are connected to the terminals by bonding wires. After pin soldering, assembly of DBC and housing is realized and then completely filled with Silicone-Gel. Figure 2: SEMITOP® mechanical construction Housing Chips Soldered temrinals Wire bonds 2.1.1 DBC substrate Tolerance system The SEMITOP® family has been designed according tolerances defined by ISO 2768-m. The value of tolerance depends on the value of the nominal dimension. For a defined "working grade", the greater is the nominal dimension, the greater is the corresponding tolerance. Following the values of tolerance from ISO 2768 m, according to the different dimensional ranges, SEMITOP® tolerances are: © by SEMIKRON / Technical Explanation / SEMITOP® / 2015-10-14 Page 5/65 Table 1: SEMITOP® tolerances according to the different dimensional ranges From 0.5 to 3 mm ±0.1 From 3 to 6 mm ±0.1 From 6 to 30 mm ±0.2 From 30 to 120 mm ±0.3 Dimensions for all SEMITOP® in the datasheets are according to the above mentioned tolerance system: Figure 3: SEMITOP® dimension example © by SEMIKRON / Technical Explanation / SEMITOP® / 2015-10-14 Page 6/65 2.2 Product portfolio Both SEMITOP® soldered version and Press-Fit version feature same housing sizes and same module height for a complete compatibility during mounting to the PCB. The following table shows the overall dimensions of SEMITOP® family: Table 2: SEMITOP® overall housing size dimensions Housing type Dimension in mm (LxWxH) Picture SEMITOP®1 31 x 24 x 12 Solder Press-Fit SEMITOP®2 40.5 x 28 x 12 SEMITOP®3 55 x 31 x 12 SEMITOP®4 60 x 55 x 12 SEMITOP® is a flexible architecture where high performing chip technologies can be placed in a very compact space. High application performances are therefore ensured thanks to the low inductance approach design that reduces the switching pattern stray inductance for the best chip commutation behavior. There are a lot of available configuration for a very comprehensive portfolio: 3-phase inverter up to 200A/600V-650V, 100A/1200V CIB configurations up to 100A/600V and 50A/1200V Single phase of three-level inverter (NPC) up to 150A/650V and 75A/1200V T-type three-level inverter (TNPC) up to 150A/1200V-100A/650V Mosfet configuration up to 300A 3-phase bridge rectifier up to 100A DC output current Many other configurations are possible © by SEMIKRON / Technical Explanation / SEMITOP® / 2015-10-14 Page 7/65 The following pictures show the SEMITOP® positioning inside SEMIKRON portfolio (picture4) and example of SEMITOP flexibility (picture5): Figure 4: SEMITOP® positioning inside SEMIKRON portfolio Figure 5: SEMITOP® flexibility: up to 55kW output power © by SEMIKRON / Technical Explanation / SEMITOP® / 2015-10-14 Page 8/65 The low inductance design approach and the compact size, make SEMITOP® the right platform to develop configuration based on the latest chip technologies to achieve the new challenging performance requirements: - Latest Si chip technologies IGBT and diodes for fast switching High voltage MOSFETS (600V and 650V) Figure 6: SEMITOP® available solutions with fast switching technologies Fast switching IGBT - Fast switching Diode Latest SiC chip technologies availability 650V and 1200V SiC diodes 1200V SiC MOSFETS Full SiC with or without SiC free-wheeling diode Hybrid solution Figure 7: SiC chip combinations and SEMITOP® SiC available configuration SK45MAHT12SCp SEMITOP®3 © by SEMIKRON / Technical Explanation / SEMITOP® / 2015-10-14 SK45MLET12SCP SEMITOP®3 Page 9/65 2.3 Chip technologies SEMITOP® is a flexible platform where the latest chip technologies can be integrated to offer the best in class performances for the new high performing configurations. Besides the standard Si chip technologies like IGBTs, diodes, thyristors and low voltage MOSFETs, it is possible to integrate also high voltage MOSFET and the newest SiC technology for diodes and MOSFETs. The wide chip offer allows an high degree of customization level, leading to the following matrix technology SEMITOP® availability: Table 3: Device technology matrix Chip type Technology IGBT Si Mosfet Si Mosfet SiC Diode Si Diode SiC Low voltage (from 40V up to 200V) √ 600V 650V 1200V √ √ √ √ √ √ √ √ √ √ √ √ Rectifier diodes and thyristors are available in Si technology, 1600V breakdown voltage rating and they are mainly used for rectification purposes. Based on the different inner construction technologies, different IGBT technologies are today available. These technologies are identified via dedicated names inside SEMIKRON: Table 4: IGBT technology matrix Fast Trench3 Trench3 Trench3 Trench3 Trench3 Trench4 Trench4 600V 065 066 Fast H5 type L5 type F5 type 650V 07E3 07F3 07Q5 07L5 07F5 Fast © by SEMIKRON / Technical Explanation / SEMITOP® / 2015-10-14 1200V 125 126 12T4 12F4 Page 10/65 2.4 SEMITOP® type designation system Table 5: SEMITOP® designation system SK 50 GD 06 6 E T p (1) (2) (3) (4) (5) (6) (7) (8) (1) SK = SEMIKRON product (2) Current size [A] = approx. nominal chip current (3) Circuit configuration description (4) Voltage grade • Thyristor/diode: VRRM [V]/100 • IGBT: VCE[V]/100 • MOSFET: VDS[V]/10 (5) Optional: chip generation • 5 = fast NPT technology • 6 = Trench3 technology 600V • E3 = Trench3 technology 650V • F3 = Fast Trench3 technology 650V • T4 = Trench4 technology • F4 = Fast Trench4 technology (6)/(7) • • • • • • Optional: extras e.g. F : fast diode T : temperature sensor E : open emitter I : current sensor UF : ultrafast diode SC : Silicon Carbide technology inside (8) p = Press-fit version © by SEMIKRON / Technical Explanation / SEMITOP® / 2015-10-14 Page 11/65 3 Chip technologies and optimized operation frequency Maximum allowable current, applied voltage and power dissipation define the maximum ratings for a device. These absolute maximum ratings have not to be exceeded if long life and reliability are to be attained. Ratings depend on used material, structure, design, mount and type of process. Therefore the close correlation between electrical properties and different ratings defines the electrical operating bounds of different devices, according to the following picture: Figure 8: Frequency range application for different modules The general trend is the higher I-V ratings the slower the possible switching frequency, hence increased junction temperature. High frequency low-power applications is dominated by MosFets or trench-gate IGBTs, high-power lowfrequency switching applications are dominated by thyristor. The IGBT combines both the voltage controlled properties of MosFet and the main features of bipolar transistors. The IGBT is suitable for numerous applications in power electronics, especially in pulse-width modulated servo and three-phases drives; it can also be used for UPS applications and other power applications requiring high switching repetition rates. The rapid development of power electronics technology is mainly driven by the new increasing requirements for energy saving leading to the use of renewable energy solutions or alternatives to fossil fuel systems. The main tasks for the next chip technologies development are mainly switching frequency increase, losses reduction, higher junction temperature range. The development directions will be mainly aimed at the research of new semiconductor materials (hence the introduction of SiC devices and maybe Gallium Nitride (GaN) devices in the future) and improvement of chip technologies like higher junction temperatures, chip size shrinking, improvement of inner structure (hence the introduction of different chip technologies with focused switching energy-voltage drop trade-off). Thanks to the already mentioned key-benefits, SEMITOP® is the leading platform to test first and then integrate the latest chip technologies; that’s why different chip technologies are today available inside SEMITOP® which combinations can allow customers to build up the most performing application. © by SEMIKRON / Technical Explanation / SEMITOP® / 2015-10-14 Page 12/65 3.1 3.1.1 IGBT technology characteristics 600V and 650V IGBTs Different 600V/650V reverse voltage IGBT chip technologies can be integrated inside SEMITOP® modules. In the following a comparison in terms of main IGBT parameters: Table 6: Comparison between available 600V/650V IGBT technologies Parameter/Series Si Technology 065 066 07E3 07F3 NPT ultrafast Trench3 Trench3 650V Trench3 Fast 650V 30 IC,nom [A] 30 30 Relative chip size at 100 60 rated current Max. operating Tj 125 150 [°C] VCE,sat @ 25°C and 2.10 1.50 IC,nom [V] Typ. Eon @ 25°c 0.45 0.48 and IC,nom [mJ] Typ. Eoff @ 25°C 0.65 0.77 and IC,nom [mJ] Pos. Temp. Coeff. Yes Yes VCE,sat Gate charge [nC] 140 167 SC capability Yes Yes *Boundary conditions : VCC=400V, RG=10Ω Source : available internet datasheets 30 07Q5 Trenchstop5 Ultrafast 650V 30 07L5 Trenchstop5 Fast 650V Low VCE,sat 30 60 60 40 52 150 150 150 150 1.50 1.95 1.65 1.07 0.48 0.66 0.20 0.77 0.44 0.10 1.35 Yes Yes Yes Yes 167 Yes 165 Yes 70 No 168 No 0.33 The comparison highlights the technological trend: size shrinking with increase of current density and higher operating junction temperature (from 125°C to 150°C). The following picture shows the latest technological positioning of the different IGBT technologies: Figure 9: 600V/650V IGBT technological positioning © by SEMIKRON / Technical Explanation / SEMITOP® / 2015-10-14 Page 13/65 EOFF-VCE,sat trade-off curve for the different technologies shows how the latest fast IGBT technologies are pushing for switching losses and conduction losses reduction at the same time in order to improve application performances: efficiency, filtering effort reduction, system volume reduction. Trenchstop5 technology represent one further step ahead respect to the Fast Trench3 with evident switching losses benefits. Improving the device performances in terms of losses reduction translates in a snappier behaviour during switching off. At the time of publication, TrenchStop5 IGBT technology is available in the market in three different technologies: H5 type (SK naming:Q5): it is a complement to the High Speed3 IGBT family. It provides very soft voltage rise during hard commutation at turn-off with low RG values and very high di/dt F5 type (SK naming: F5): this is the higher performance solution. It provides the higher efficiency but more design efforts are required during driving stage L5 type (SK naming: L5): this brand new family features the lowest conduction losses It is therefore possible to define the optimized frequency range of operation and the main target markets for the mentioned IGBT types according to the mentioned characteristics: Table 7: Comparison between available 1200V IGBT technologies Technology Main target markets SC capability Frequency range - 066/07E3 UPS Solar Power supply Motor drives YES Up to 20kHZ - 07F3 UPS Solar Power supply Welding YES - Up to 100kHz 07Q5 UPS Solar SMPS Welding NO 10-100kHz high speed 07L5 - UPS - Solar - Welding NO Low VCE,sat up to 20kHz The right technology choice depends on the customer boundary conditions and application requirements. At the time of publication, 065 and 066 technologies are in use. The new mentioned technologies are available inside SEMITOP® and can be considered for new designs. The old 065 is going to be replaced by the new performing fast technologies and therefore it has not been inserted in the above table. 3.1.2 1200V IGBTs Different 1200V reverse voltage IGBTs chip technologies can be integrated inside SEMITOP® modules. In the following a comparison in terms of main IGBT parameters: Table 8: Comparison between available 1200V IGBT technologies Parameter/Series Si Technology IC,nom [A] Relative chip size at rated current Max. operating Tj [°C] VCE,sat @ 25°C and IC,nom Typ. Eon @ 25°c and IC,nom Typ. Eon @ 25°C and IC,nom Pos. temp coeff VCE,sat Gate charge [nC] SC capability 125 NPT ultrafast 50 126 Trench3 50 12T4 Trench4 50 12F4 Trench4 Fast 50 100 70% 62% 62% 125 125 150 150 3.20 1.70 1.85 2.05 5.70 3.00 5.70 2.52 2.20 4.00 2.80 1.70 Yes 600 Yes Yes 470 Yes Yes Yes Yes Yes 1200V technologies confirm the same trend of the 600V/650V chips in terms of improvement in the inner and final application performances . The change from planar gate structure (125 technology) to the © by SEMIKRON / Technical Explanation / SEMITOP® / 2015-10-14 Page 14/65 trench gate structure brought big advantages as regards switching and conduction performances. The following table shows the 1200V trench gate structure technological positioning: Figure 10: 1200V IGBT Trench technology positioning According to the improvement of the last years, it is possible to define an optimized frequency range operation: Table 9: Comparison between available 1200V IGBT technologies Technology Main target markets SC capability Frequency range 126 - UPS - Solar - Motor drives YES Up to 20kHz 12T4 - UPS - Solar - Motor drives YES Up to 20kHz 12F4 - UPS - Solar - Welding YES Above 30kHz The right technology choice depends on the customer boundary conditions and application requirements. At the time of publication, all the technologies are in use. The new 12F4 technology is available inside SEMITOP® and can be considered for new designs. The old 125 is going to be replaced by the new performing fast 12F4 technology and therefore it has not been inserted in the above table. © by SEMIKRON / Technical Explanation / SEMITOP® / 2015-10-14 Page 15/65 3.2 3.2.1 MOSFETs technology characteristic Si MOSFETs Both low voltage types and high voltage types can be integrated inside SEMITOP® platform. At the time of publication, Superjunction MOSFET technology can be offered for application where 600V and 650V MOSFET are required. The present MOSFET portfolio offer is therefore like follows: Table 10: MOSFET portfolio Reverse blocking voltage [V] rds,on [mΩ], chip level, 25°C Technology 40 1.1 60 1.7 80 2.5 100 2.7 Optimos3 Optimos3 Optimos3 Optimos3 600 99 Super junction – CP series Recently Infineon developed the super junction MOSFET C7 series , 650V rated. The qualified CP series and the new C7 series can be considered for new designs; main target markets are boost converters in solar applications and welding configurations. 3.2.2 SiC MOSFETs There are applications that ask for very stringent requirements like extremely reduced switching energies or high switching frequency operation. This is mainly due to the need to have high efficiency conversion or to reduce the volume at system level via filter, cooling, fans and other equipment reduction. SiC MOSFET is the right technology to fulfil these stringent requirements thanks to some main benefits: Switching losses near to zero Very low temperature dependence of the switching losses State of the art SiC MOSFET feature mainly configurations with 1200V voltage class: this new technology is today offered inside SEMITOP® in two different electrical configurations: Table 11: SiC MOSFET portfolio Configuration Module name Housing Rating SK45MAHT12SCp SEMITOP3 Press-Fit -1200V/45mΩ SiC MOSFET -1200V/50A SiC Schottky diode SK45MLET12SCp SEMITOP3 Press-Fit -1200V/45mΩ SiC MOSFET For further details about SiC MOSFETs please refer to: “Silicon Carbide presentation”, 03-07-2015, Semikron presentation: http://www.skd.semikron.com/cps/rde/xchg/intranet_eng/hs.xsl/products_ps_sic.htm Module datasheets available in the web © by SEMIKRON / Technical Explanation / SEMITOP® / 2015-10-14 Page 16/65 3.3 Inverse and Free-wheeling diodes 3.3.1 SEMIKRON CAL diodes The free-wheeling diodes used inside SEMITOP® are mainly SEMIKRON CAL (Controlled Axial Lifetime) diodes, or HD CAL (High Density CAL) diodes. These fast, “super soft” planar diodes are characterised by the optimal axial profile of the charge carrier life-time, which was achieved in an implantation process using helium ions and basic carrier life-time setting. The main advantages are: Low peak reverse current and thus a lower inrush load current “Soft” decrease of the reverse current throughout the entire operating temperature range Robust performance when switching high di/dt Paralleling capability thanks to the negligible negative temperature coefficient and the small forward voltage VF spread The new “CAL4” diode series has been designed specifically for the new 650V IGBT series and the 1200V IGBT4 series. This new CAL diode series is able to ensure safe operation up to 175°C. SEMIKRON CAL diodes are able to operate up to 20kHz switching frequency depending on the application boundary conditions. 3.3.2 Fast switching diodes There are applications where there is need to push the frequency higher or to improve recovery performances. In this case hyper-fast high voltage silicon diodes or SiC diodes are needed. Hyper-fast Silicon diodes: based on the ultrathin wafer technology, the new RAPID1 family released by Infineon can be a valid option inside SEMITOP® for switching frequencies from 20kHz up to 40khZ (depending on the application operating conditions). Main diode advantages are: 1. Very low conduction losses 2. Low peak reverse recovery current 3. Low reverse recovery time 4. High softness factor RAPID1 is mainly designed for optimized forward voltage drop for the lowest conduction losses and today available only in 650V voltage class. Target markets are UPS, solar inverters and welding; they are especially integrated inside PFC topologies or inside the three-level inverters (neutral clamp diode position) and normally coupled with the H3/650V or H5/650V IGBT technologies. SiC diodes: they are unipolar devices so only one type of charge carrier is responsible for current transmission. No excess charge could appear as storage charge when the diode turns-off; it means that there is almost no reverse recovery current or “tail current”. These diodes feature therefore minimal switching losses owing to extremely reduced IGBTs’ Eon parameters and they are optimized for very high switching frequencies. The devices are rated for junction temperature up to 175°C with a very high thermal conductivity, resulting in lower thermal resistance performances. Chip sizes are very small, leading to small power modules. State of the art offer both 650V and 1200V voltage class diodes. Main target markets and application are listed in the following table: © by SEMIKRON / Technical Explanation / SEMITOP® / 2015-10-14 Page 17/65 Table 12: Main SiC markets and tasks Market Tasks Renewable Energy solar HF power supplies - Increase fsw - Reduce passive filter components - Increase efficiency Naturally high switching frequency Motor drives - Reduce power losses - Reduce cooling efforts - Reduce size and weight UPS - Increase fsw - Reduce passive filter components - Increase efficiency SiC diodes can be coupled as antiparallel diodes to the IGBT, so to build up so called “hybrid” solutions or to the SiC MOSFET to build up “full-SiC” solutions. For further details about SiC diodes please refer to: “Silicon Carbide presentation”, 03-07-2015, Semikron presentation: http://www.skd.semikron.com/cps/rde/xchg/intranet_eng/hs.xsl/products_ps_sic.htm and related product datasheets. 3.4 3.4.1 Chip operating areas IGBT Safe Operating Area (SOA) for turn-on and single pulse operation Safe operating area is defined as the voltage and current conditions over which the chip can operate without self-damage during switching-on. This curve is not present in datasheet but can be provided on demand. SOA curve is a graph that exhibits dependence of collector current from collector-emitter voltage for single pulse duration and junction temperature of the device. The safe operating area is the area under the considered curve. The SOA curve is limited by the following parameters: Maximum collector current (horizontal limit) Maximum collector-emitter voltage (vertical limit) In the following an example of SOA curve for module SK50GD066ETp is provided: Figure 11: IGBT Safe Operating Area (SOA) diagram © by SEMIKRON / Technical Explanation / SEMITOP® / 2015-10-14 Page 18/65 3.4.2 IGBT Reverse Bias Safe operating area (RBSOA) for periodic turn-off Reverse Bias Safe operating area is the SOA curve when the device is during turn-off state. This curve is also not present in datasheet but it can be provided on demand. Maximum VCES has not to be exceeded during turn-off. Due to the internal stray inductance, collectoremitter voltage to terminals is less than the collector-emitter voltage at chip level. This is the reason the curve is cut in the upper right corner respect to the curve at chip level. In the following an example of RBSOA curve for module SK50GD066ETp: Figure 12: IGBT Reverse Bias Safe Operating Area (RBSOA) diagram Tj ≤ 150°C VGE = -7/+15 V IC,nom = 50A Ts = 25°C tp ≤ 1 ms RG=16Ω IC module IC chip 3.4.3 IGBT Short Circuit Safe operating area (SCSOA) for non periodic turn-off of short circuits This is the SOA curve at short circuit condition. The diagram shows the limit for safe control of a short circuit. The curve is not inside the datasheets but it can be provided on demand. The picture shows SCSOA curve for module SK50GD066ETp. Figure 13: IGBT Short Circuit Safe Operating Area (SCSOA) diagram IC,nom = 50A © by SEMIKRON / Technical Explanation / SEMITOP® / 2015-10-14 Page 19/65 When turning off a short circuit, the high short-circuit current induces a voltage at the parasitic inductances in the commutation circuit; this voltage must not cause VCES to be exceeded. In order to limit the energy dissipation of the IGBT chips, short-circuit turn-off is subject to the following conditions: the short circuit has to be detected and turned off within max 10µs (6µs for 600V/650V Trench IGBT) the time between two short circuits has to be at least 1second the IGBT must not be subjected to more than 1000 short circuits during its total operation time the maximum chip temperature before a short circuit occurs is limited to 150°C the maximum voltage VCC decreases the prevailing –dic/dt maximum ratings must be controlled by the driver parameters if necessary, non-permissible increase in gate-emitter voltage during short-circuit turn-off will have to be prevented by clamping 3.4.4 MOSFET Safe Operating Area (SOA) for single pulse operation The MOSFET has to achieve almost rectangular characteristic iD=f(v) between VDD and ID during hard switching. The diagram indicates to what extent this may be realised during different operating states without risk of destruction. All the limitations mentioned for the IGBT curve can be applied to the MOSFET too. The curve is not inside the datasheet, but it can be provided on demand. Figure 14: MOSFET Safe Operating Area (SOA) diagram © by SEMIKRON / Technical Explanation / SEMITOP® / 2015-10-14 Page 20/65 3.4.5 Surge current characteristic of CAL diodes When the CAL diode operates as rectifier diode in a “IV-Q” application, it is necessary to know the ratio of the permissible overload on-state current IF(OV) to the surge on-state current IFSM as a function of the load period t and the ratio of VR/VRRM. VR denotes the reverse voltage applied between the sinusoidal half waves; VRRM is the peak reverse voltage. Figure 15: Diode Surge overload current vs. time © by SEMIKRON / Technical Explanation / SEMITOP® / 2015-10-14 Page 21/65 4 SEMITOP® technology SEMITOP® modules are made by direct soldering of the chips (IGBT, Mosfet, Diodes, Thyristors, SiC diodes and MOSFETs) and the power terminals on a ceramic substrate, typically Aluminium Oxide (Al2O3) or Aluminum Nitride (AlN) covered by a thin copper layer. The ceramic substrate is directly placed on the heatsink using only a thermal conductive material (typically Thermal Grease). Such a silicon material should fill all air gaps at the interface between the module and the heat sink. The housing is the basic part of SKiiP® technology in SEMITOP® modules: it has to guarantee that the ceramic substrate is evenly set on the heatsink in order to perform an homogenous heat exchange between module and the heatsink. The SEMITOP® plastic housing has to evenly pressure the substrate surface through the only one required screw for the mounting. Figure 16: SEMITOP® structure and concept of SKiiP technology The pressure concept brings the following advantages: Distributed pressure from the ceramic substrate (also called DBC) to heatsink without baseplate No stress on bonding connections No rigid large area connections between materials with different CTE (coefficient of thermal expansion) Different materials are contacted by a pressure system Any mechanical stress is absorbed by the structure itself © by SEMIKRON / Technical Explanation / SEMITOP® / 2015-10-14 Page 22/65 4.1 Baseplate-less basic technology SEMITOP® is a baseplate-free power module where dice are placed on a DBC substrate. This DBC substrate is made of a top side copper layer in direct contact with the chip, a ceramic layer that ensures insulation and a back side copper layer that goes in contact with the heatsink through a thermal grease layer. Modules with baseplate technology feature the system DBC substrate + chips soldered to a copper baseplate. The whole assembly is then in contact with the heatsink through a thermal grease layer. This technological difference brings to different thermal resistance paths as the following picture shows: Figure 17: Thermal resistance paths for a baseplate and a baseplate-less module ௧,ି௦ = ௧,ି + ௧,ି௦ By using a baseplate free module technology, there is a direct thermal path between chip junction and heatsink (Rth,j-s). A module with baseplate considers two thermal paths: junction-case (Rth,j-c) and casesink (Rth,c-s). Therefore maximum allowable DC current capability performances for a SEMITOP® module are always referred to the heatsink temperature. Attention has to be put when comparing SEMITOP® against module with baseplate in order to avoid misleading evaluations. As example, a 50A/3phase inverter application has been simulated comparing SEMITOP® against some competitors: © by SEMIKRON / Technical Explanation / SEMITOP® / 2015-10-14 Page 23/65 Table 13: IGBT performance comparison SEMITOP* Module height [mm] Module technology 12 No baseplate Competitor A* 12 No baseplate Competitor B* 12 No baseplate IC [A] at Tj,max and TS=25°C 60 IC [A] at IC [A] at Tj,max and Tj,max and TS=70°C TC=25°C 50(1) 70 (2) 45(3) Rth,j-s [K/W] Typical VCE,sat [V] at IC,nom and Tj=150°C 1,11 1,65 1,46 1,70 1,25 1,75 *Source: datasheet available in the web (1): current capability refers to the heatsink (2): current capability is referred to the case temperature in the datasheet (3): current capability is referred to heatsink but at 80°C In order to make the right performances comparison, it is needed to calculate the current capability at the same reference point. By referring all the calculations to the same heatsink reference point, the IGBT performances are as per below table: Table 14: IGBT performance comparison for the same reference point Module height [mm] IC [A] at Tj,max and TS=25°C IC [A] at Tj,max and TS=70°C Rth,j-s [K/W] SEMITOP* 12 60 50 1,11* Competitor A* 12 50 40 1,46* Competitor B* 12 54 44 1,25* *Source: datasheet available in the web SEMITOP® exhibits the best thermal and electrical performances for the same reference point with the lowest Rth,j-s value. The thermal resistance affects the maximum junction temperature and therefore the maximum output power. The picture shows the maximum output power vs switching frequency at the same switching conditions: Figure 18: Maximum output power as function of the switching frequency SEMITOP® allows a 5-20% higher output power over a wide frequency range © by SEMIKRON / Technical Explanation / SEMITOP® / 2015-10-14 Page 24/65 4.2 Thermal material data For thermal simulation purposes it is necessary to know the thermal material parameters as well as the typical thicknesses of the different layers in the package. The sketch in Fig. 19 and the Table 15 show the different layers of the package: Figure 19: SEMITOP® package sketch (cross section view) Table 15: Typical material data for SEMITOP® package Material Layer thickness [mm] Heat conductivity λ [W/(mK)] Thermal expansion coefficient (CTE) α [10-6 K] IGBT chip (“066”) Si 0.070 148 4.1 IGBT chip (“07F3”) Si 0.070 148 4.1 IGBT chip (“126”) Si 0.120 148 4.1 IGBT chip (“12T4”) Si 0.115 148 4.1 IGBT chip (“12F4”) Si 0.115 148 4.1 Diode chip Si 0.240 148 4.1 Rapid diode chip Si 0.050 148 4.1 SiC 0.235 370 4.0 MOSFET Si 0.175 148 4.1 MOSFET (“060”) Si 0.175 148 4.1 MOSFET (“120”) SiC 0.330 370 4.0 Chip solder SnAg alloy 0.115 70 15-30 DBC copper Cu 0.30* 394 17.5 DBC ceramic Al2O3 0.63* 24 8.3 DBC copper Cu 0.30* 394 17.5 Layer Shottky diode Thermal paste Customer specific Heatsink Customer specific ® *Valid for SEMITOP 1,2,3. *Ceramic thickness for SEMITOP®4 is 0.2/0.38/0.3 mm and for SEMITOP®4 Press-Fit is 0.4/0.5/0.4 The above table shows that a limited number of materials is used inside a SEMTOP® package and how these materials feature similar CTE values. © by SEMIKRON / Technical Explanation / SEMITOP® / 2015-10-14 Page 25/65 The below picture compares SEMITOP® materials and related CTEs with the ones used inside baseplate (modules or discrete solutions). The length of the bars indicate the CTE values; huge differences in length are an indication of considerable stress. Some main advantages become therefore evident: reduced thermo-mechanical stress. Big differences in the CTEs lead to mechanical stress causing ageing of connections when they are exposed to temperature changes; reduced risk of delamination effects and field failures; higher assembly reliability; better thermal cycling performances Figure 20: CTE comparison for different power modules 4.3 Definition and measurement of Rth The maximum junction temperature Tj under static and dynamic load conditions is very important for the power system layout, because it is a key factor for the lifetime of a power system. The SEMITOP® pressure contact technology thermally connects the DBC substrate to the heatsink; the case temperature Tc cannot be measured directly by a hole through the heatsink that allows the access to the module base. Therefore only the thermal resistance junction to heatsink Rth,j-s can be measured. The thermal resistance Rth,j-s describes the distribution of temperatures in a system as the reaction to an impressed power P according to the following equation: Equation 1: Rth,j-s as function of the temperature parameters and impressed power , = − Tj= junction temperature [°C] Ts= heatsink temperature [°C] P = impressed power [W] © by SEMIKRON / Technical Explanation / SEMITOP® / 2015-10-14 Page 26/65 4.3.1 Test setup The following picture shows the measure system for thermal resistance: Figure 21: System setup for Rth measurement The reference point TS is shifted to a position of 2mm underneath the module inside the heatsink. The distance of 2mm ensures that parasitic effects resulting from heatsink parameters (size, thermal conductivity etc.) are minimised and the disturbance induced by the thermocouple itself is negligible. At position of hotspot, the heatsink will be drilled towards the bottom of the module to 2mm below the module DBC base (hole diameter of Ø 2.5mm). A thermocouple can be introduced into this hole measuring the reference point Ts. This method is independent from the DBC layout and results in constant thermal resistance values for the same chip sizes and packaging technology. 4.3.2 Principle of Rth measurement For modules without a baseplate it is not possible to measure the thermal resistance Rth,j-c and Rth,c-s separately as the baseplate does not exist. The thermal resistance Rth,j-s is evaluated from the virtual junction temperature Tj. The following physical coherency is used: when operating with a small measurement current, bipolar semiconductor devices show a linear dependence of the voltage drop from the virtual junction temperature. The module is operated at a constant load current until thermal equilibrium is reached after 60 seconds. After reaching thermal equilibrium, the load current is switched off and a small current of 100mA is applied to the module. 4.3.3 Transient thermal impedance Zth Transient thermal impedance relates the junction temperature rise to a fixed dissipated power. According to EQ.1, by applying to the chip a step of fixed power value to dissipate and maintaining the heatsink temperature to a fixed value, by measuring the junction temperature variation in the time, it is possible to measure the thermal resistance rise during time until it reaches the steady state value Rth,j-s. For a given multilayer structure such as silicon chip, DBC and heatsink, thermal behavior can be modeled by using an electrical model (so called Cauer network): © by SEMIKRON / Technical Explanation / SEMITOP® / 2015-10-14 Page 27/65 Figure 22: Multilayer thermal structure and thermal equivalent Cauer network This network describes the real physical model of thermally relevant layers and it is described via two parameters: the thermal resistance and the thermal capacitance: Equation 2: Equation for thermal resistance and capacitance , = ∙ [k/W] (d = material thickness, λ = heat conductivity, A = heat flow area) , = ∙ [J/K] (s = heat storage characteristic, V = volume ) Based on measurements, a mathematical thermally equivalent model of the Cauer network can be derived (EQ.3) and it is described by the Foster network model (Fig. 23) Equation 3: Zth general equation for the Foster network , = , ⋅ (1 − ) n = number of RCs network Normally, a 4 parameters network model is used and therefore “n” is limited to 4. © by SEMIKRON / Technical Explanation / SEMITOP® / 2015-10-14 Page 28/65 Figure 23: Foster network In the following picture, an example of transient thermal profile obtained by using the EQ.3 for the IGBT and diode inside SK50GD066ETp is given: Figure 24: Example of thermal impedance profile Thermal impedance profile for SEMITOP® modules can be provided on demand. 4.4 Specification of the integrated temperature sensor SEMITOP® power modules are equipped with NTC (Negative Temperature Coefficient) or PTC (Positive Temperature Coefficient) sensors. To get the detailed information about type of temperature sensor, it is needed to refer to the module datasheet. The temperature sensor is a temperature dependent resistor which reflects the actual heatsink temperature. 4.4.1 Electrical characteristic (NTC) The standard “KG3B” temperature sensor exhibits a negative temperature coefficient characteristic with a nominal resistance value at 25°C of 5 kΩ±5%. The temperature-dependent resistance of the NTC sensor is described by the following equation: Equation 4: NTC general equation ⋅ ∙ మ భ R2 : resistance at absolute temperature T2 [K] R1 : resistance at absolute temperature T1 [K] B : B-value [K] (B25/85 = 3420 K) © by SEMIKRON / Technical Explanation / SEMITOP® / 2015-10-14 Page 29/65 The typical NTC characteristic is shown in the figure: Figure 25: Typical NTC sensor characteristic 4.4.2 Electrical characteristic (PTC) The standard “SKCS2 Temp 100B” temperature sensor with positive temperature coefficient characteristic exhibits a nominal resistance value at 25°C of 1kΩ±3%. The temperature-dependent resistance of the PTC sensor is described by the following equation: Equation 5: PTC general equation 1000 ∙ 1 ∙ 25 ∙ 25 A : 7.635∙10-3 [°C-1] B : 1.731∙10-5 [°C-2] The typical PTC characteristic is shown in the figure: Figure 26: Typical NTC sensor characteristic SEMIKRON recommends a measuring current range of 1mA≤IM≤3mA. © by SEMIKRON / Technical Explanation / SEMITOP® / 2015-10-14 Page 30/65 To realize a trip level by additional protection network, the recommended value for the trip temperature is about 115°C (air cooling), based on a heatsink with a standard thermal lateral spread. 4.4.3 Electrical isolation Inside the SEMITOP® the temperature sensor is mounted close to the IGBT – and diode dice onto the same substrate. The minimum distance between the copper conductors is ≥ 0.71 mm. Figure 27: Position of temperature sensor on DBC substrate Since the SEMITOP® module is filled with silicone gel for isolation purposes, the requirements for the specified isolation voltage (AC/2.5kV/1 min, AC/3kV/1s at 50Hz) are met and 100% tested. During short circuit failure and therewith electrical overstress, the bond wires could melt off and so produce an arc with high energy plasma. In this case the direction of plasma expansion is not predictable; the temperature sensor might be touched by plasma and exposed to a high voltage level. The safety grade “Safe electrical isolation” according to EN 50178 can be achieved by different additional means, described there in detail. Figure 28: Sketch of high energy plasma caused by melted off bond wire © by SEMIKRON / Technical Explanation / SEMITOP® / 2015-10-14 Page 31/65 5 Assembly instructions In order to achieve the best SEMITOP® performances, the following specifications have to be fulfilled. 5.1 Heatsink specification To obtain the maximum thermal conductivity, the underside of the module must be free of grease and particles. The heat sink must fulfil the following mechanical specifications: Flatness of heat sink area must be ≤50µm per 100mm (DIN EN ISO 1101) Roughness “Rz” ≤6,3µm (DIN EN ISO 4287) No steps Machined without overlaps Surface of heat sink should be free of grease, e.g. by cleaning the heat sink in a fat-dissolving solvent. A good indication is given by the DIN 53364, surface tension ≥ 32N/m. Tap holes must be free of turnings. The supplier of the heat sinks should choose adequate packaging to avoid contamination and mechanical damage during transport. Figure 29: Heatsink specification 5.2 Mounting surface The mounting surface of SEMITOP® module must be free from grease and particles. Fingerprints on the bottom side do not affect the thermal behavior. Due to the manufacturing process, the bottom side of the SEMITOP may exhibit scratches, holes or small marks. Discoloration on the bottom side do not affect the thermal behavior. Maximum allowed scratch characteristics that do not affect the thermal behavior are like the following: Figure 30: Scratch specification for SEMITOP® modules © by SEMIKRON / Technical Explanation / SEMITOP® / 2015-10-14 Page 32/65 It has to be noted that oxidation observed at time of manufacturing can be very different from what observed at customer’s inspection since it can be increased by environmental conditions during transportation, exposure to humidity and/or pollution and stocking of modules as customer’s warehouse. The following table describes the possible changes of copper appearance and will provide the instruments to consider a possible cosmetic issue as acceptable by incoming inspection from customer side. The acceptance criteria is based on internal measurements of module behavior (Rth,j-s) and functionality (including static, dynamic and reliability parameters) which proved that cosmetic issues do not affect module performances. The test results are available on request. Table 16: Cosmetic issue acceptance matrix Cosmetic issue description Picture Possible presence of scratches: SKI quality inspection check if there are scratches within the specified dimensions (depth < 300µm, width < 600 µm, roughness < 10 µm). Roughness is intended as maximum height of the scratch tip. Any number of scratches is allowed; each scratch must be within the copper. Only the modules within the mentioned specified limits are shipped Oxidized copper by flux used during soldering process, without any flux residues Oxidized copper by heat during pin soldering process © by SEMIKRON / Technical Explanation / SEMITOP® / 2015-10-14 Page 33/65 Oxidation in small discolored spots. There is no limit to the number of the discolored spots Copper discoloration without external contamination at the end of production process Dark copper discoloration on all the surface Piece showed rework by polishing of copper surface, which is allowed from SK working instructions (accepted from all customers) © by SEMIKRON / Technical Explanation / SEMITOP® / 2015-10-14 Page 34/65 5.3 5.3.1 Assembling steps SEMITOP® with soldered terminals SEMITOP® module can be assembled by either starting soldering the modules to the PCB and then fix the subsystem PCB+SEMITOP® to heat sink (figure 31, left), or fixing SEMITOP® to the heat sink and then solder to the PCB (figure 31, right) Figure 31: PCB assembly and heatsink assembly To avoid any damage to the SEMITOP®, it is important to respect important operative conditions during the main assembling steps such as the application of thermal grease, the soldering process and the assembly to the heat sink. Figure 32: Assembly steps for SEMITOP® module with soldered terminals © by SEMIKRON / Technical Explanation / SEMITOP® / 2015-10-14 Page 35/65 5.3.2 SEMITOP® with Press-Fit pins The PCB has to be fixed to the module through the press-in tool, heatsink surface must be prepared and recommended thickness of thermal grease must be stenciled onto the heatsink. Afterwards the whole system (module+PCB) can be fixed onto the heatsink. Figure 33: Assembly steps for SEMITOP® module with Press-Fit pins 5.3.3 Mounting process outline The following table compares the two SEMITOP® mounting process Table 17: Mounting process outline © by SEMIKRON / Technical Explanation / SEMITOP® / 2015-10-14 Page 36/65 5.4 Thermal grease application To avoid air gaps at the interface between the module and the heatsink a thermal grease must be applied. The function of the grease is to flow according to the shape of the interface, allowing a metal-tometal contact where it is possible, and filling the remaining gaps. This metal-to-metal contact can be ensured by using a standard thermal grease or by pre-applied thermal paste. 5.4.1 Standard thermal grease specification Recommended thermal grease material is Wacker-Chemie P 12. SEMIKRON recommends a hard rubber roller or a screen print for an even distribution of the grease. Table 18 shows the recommended average thickness of the applied grease layer: Table 18: Recommended average thermal grease thickness for SEMITOP® modules Module SEMITOP®1 SEMITOP®2 SEMITOP®3 SEMITOP®4 Thermal grease thickness (Wacker P12) 20 – 25 µm 30 – 35 µm 50 – 55 µm 40 – 45 µm SEMIKRON has qualified the SEMITOP® power modules under the above mentioned conditions. It is customer’s responsibility to qualify his own paste printing process as deviations from the recommended process may impact reliability or technical performance of the modules. Thickness of thermal paste can be checked by the use of a gauge from ELCOMETER (Elcometer Instruments GmbH, Ulmer Strasse 68, 73431 Aalen, Tel. +49-7361-528060: Sechseck-Kamm 5-150µm) shown below: Figure 34: Measuring gauge by ELCOMETER 5.4.2 Pre-applied thermal paste specification SEMITOP® is today offered with pre-applied thermal paste to simplify the module assembly process. The thermal paste is applied by SEMIKRON prior to delivery to the customer, thus eliminating this critical process step from the customer’s manufacturing process. In this way assembly is more efficient, reproducible and controllable. Main advantages are: Optimum thickness of thermal paste layer leading to lower thermal resistance High degree of process reliability using an automated and monitored screen-printing process © by SEMIKRON / Technical Explanation / SEMITOP® / 2015-10-14 Page 37/65 Figure 35: SEMITOP® with pre-applied thermal paste SEMIKRON offers SEMITOP® power module with Wacker P12 (silicon based) pre-applied thermal paste which thickness of layers is shown in the below picture for each module size. These thicknesses are obtained via a dedicated stencil process with a special pattern designed on this purpose: Table 19: Pre-applied thermal grease thickness with the use of a special pattern Module SEMITOP®2 SEMITOP®3 SEMITOP®4 Pre-applied Wacker 22 - 36 40 - 54 25 - 37 P12 thickness µm µm µm Storage conditions for the pre-applied thermal paste are: Table 20: Pre-applied thermal paste storage conditions tstg Tstg RTstg 5.5 Storage time Storage temperature Storage humidity Max. 18months -25°C … +60°C 10% … 95% Assembling on heatsink Once the SEMITOP® is placed onto the heatisnk , SEMIKRON recommends to tighten the screw with the corresponding mounting torque: Table 21: Mounting parameters for SEMITOP® Module SEMITOP®1 Screw Washer Mounting torque DIN 912-M-4x16 DIN 6798 Form A + DIN 125 1,5 Nm +0/-10% DIN 912-M-4x16 DIN 6798 Form A + DIN 125 2,0 Nm +0/-10% DIN 912-M-4x16 DIN 6798 Form A + DIN 125 2,5 Nm +0/-10% DIN 912-M-4x16 DIN 6798 Form A + DIN 7349 ® SEMITOP 2 SEMITOP®2 Press-Fit SEMITOP®3 SEMITOP®3 Press-Fit SEMITOP®4 SEMITOP®4 Press-Fit 2,6 Nm +/-5% SEMIKRON recommends: a torque wrench with automatic control. Electric power screwdriver is recommended over a pneumatic tool. The specified screw parameters are better adjustable and especially the final torque will be reached more smoothly. A limitation to the mounting torque screw velocity is recommended to allow the thermal paste to flow and distribute equally. If tightened with higher velocity the ceramic may develop cracks due to the inability of the paste to flow as fast as necessary and therefore causing an uneven surface. The maximum screw velocity should not exceed 250rpm if recommended Wacker P12 © by SEMIKRON / Technical Explanation / SEMITOP® / 2015-10-14 Page 38/65 paste is used. A soft level out (no torque overshoot) will reduce the stress even further and is preferable the above recommended screws and washers tighten the screws only once. After the mounting do not re-tighten the screws to the nominal mounting torque value. Due to relaxation of the housing and flow of thermal paste, the loosening torque is lower than the mounting torque. However, the construction of the housing, the washers and the adhesion of the thermal paste still ensure sufficient thermal coupling of the module to the heat sink Do not exceed the mounting torque because a further increase of the maximum mounting torque will not improve the thermal contact but could only damage the module 5.6 5.6.1 Matching SEMITOP® and the PCB SEMITOP® with soldered terminals Use plastic anchor pins in each corner on the top of the SEMITOP® for mechanical connection between PCB and SEMITOP®. To avoid mechanical stress to the soldering pins, the PCB has to be additionally supported (e.g. using spacers). Suggested hole diameter for the soldering pins and the mounting pins in the PCB is 2mm. It does not exist a limit to the number of SEMITOP® modules that could be assembled on the same PCB; many running applications (see figure 36) consist of many SEMITOP® modules on the same PCB and the customers never had any complaint. Figure 36: Example of running application with multiple SEMITOP® modules on the same PCB 5.6.1.1 Soldering on PCB SEMITOP® modules can be soldered to the PCB using the most common soldering process: Hand iron Wave soldering process Selective soldering equipment Independent on the soldering process used to solder SEMITOP® modules to the PCB, SEMIKRON recommends a thorough evaluation of the solder joints to ensure an optimal connection between SEMITOP® and the PCB. Figure 37 shows a profile of a good soldered joint. Notice that the solder forms a concave meniscus between pin and pad. This is an example of a properly formed meniscus and it is a result of good wetting during the soldering process. © by SEMIKRON / Technical Explanation / SEMITOP® / 2015-10-14 Page 39/65 Figure 37: Good soldered joint profile In both Figure 37 and Figure 38 it can also be seen that the soldering covers a good deal of the surface area of the pin and of the pad. This is also evidence of good wetting. It has to be noted that the soldering joint has a smooth surface with a silver color. This is the result of good immobilization of the joint during cooling as well as good cleaning of the board prior to soldering. All soldering connections should exhibit similar characteristics regardless whether they are soldered by hand iron or wave soldering process. Figure 38: Details The time required to create a robust connection depend on several parameters: PCB thickness: when increasing the PCB thickness, the heat dissipation capability of the PCB itself will be the higher, and thus it will require a longer soldering time Copper wire area: pins require large copper wire to minimize resistive power losses during the current flowing. Since copper has a good heat transmission coefficient, the size of these copper wires directly affects the soldering time necessary to heat the PCB pad. Hand iron power: power, tip size and working temperature of the hand iron affect the soldering time. These parameters have to be adjusted in order to keep the maximum temperature within the specified limit. Lead free solder alloys type: Sn content is the key leading component that affects the soldering time and temperature. Normally used lead free alloys are Sn96.5Ag3Cu0,5 or Sn99Cu0,7. SEMIKRON recommends that the soldering joints should be thoroughly checked to ensure a high quality soldering joint. If necessary, different parameters should be adjusted in order to optimize the process. A) Hand Soldering SEMIKRON recommends to not exceed the maximum temperature of 260°C for a soldering time of 10seconds especially when several terminations must be soldered.(CEI-EN 60068-2-20). B) Wave Soldering Profile SEMIKRON recommends: do not exceed the maximum wave soldering profile of figure 39; © by SEMIKRON / Technical Explanation / SEMITOP® / 2015-10-14 Page 40/65 the maximum preheating temperature has to be kept under or equal to the maximum storage temperature (125°C); do not exceed the maximum preheating time of 100seconds; during the soldering phase, do not exceed the maximum soldering time of 10 seconds at the maximum temperature of 245°C±5°C. Figure 39: Wave soldering profile SEMITOP® modules could be soldered by a deep soldering process; the important is to avoid to exceed the maximum soldering conditions stated in the previous items. 5.6.2 Connecting the PCB via press-fit pins Some requirements as regards the Plated Through Hole of the PCB need to be fulfilled according to international standard IEC 60352-5 in order to ensure the proper functioning. Semikron performed all the qualification tests following these values. The qualification test are done on a standard FR4 PCB and on a surface finish of immersion tin (I-Sn). The following table shows the specification of PTH for immersion tin plating: Table 22: Specification of PTH with I-Sn Recommended size of drill Drilled hole diameter Copper thickness in via Tin plating in via Final hole diameter Anular ring Thickness of PCB Min. Typ. 1.6mm Max. 1.575mm 25µm >0.5µm 1.39mm 100µm 1.6mm 1.6mm 1.625mm 1.45mm 1.54mm Not limited Other plating has to be tested on request. © by SEMIKRON / Technical Explanation / SEMITOP® / 2015-10-14 Page 41/65 In case of soldering of Press-Fit pins directly to the PCB, the following table shows the PTH specification for immersion tin plating : Table 23: Specification of PTH with I-Sn for soldering of Press-Fit pins to the PCB Drilled hole diameter Copper thickness in via Tin plating in via Anular ring Final hole diameter Thickness of PCB Min. 2.10mm 25µm 10µm 100µm Typ. 2.15mm Max. 2.25mm 2.00mm 0.8mm 1.6mm For mounting of the SEMITOP® Press-Fit to the PCB, the recommended hole diameter for the mounting post is according to the following table: Table 24: Specification of mounting hole diameter SEMITOP4® Press-Fit 3.6mm SEMITOP3® Press-Fit 2mm SEMITOP2® Press-Fit 2mm Mounting post Particular attention must be paid for those components that need to be placed close to module pins like resistors, capacitors or diodes. A minimum distance of 4mm is required between the edge of these components and the middle of PTH; this ensures enough space for the pressing tool during fixing of the PCB to the module. Figure 40: Distance between components and centre of PTH As the definition itself of press-fit module says, it is needed to press-in the module into the PCB for a perfect match. The available presses suitable for this process can be categorized as manual, force assisted manual, semiautomatic and fully automatic. For further details about the press-type characteristics, please refer to the SEMITOP® Press-Fit mounting instructions. SEMIKRON qualified the press-fit technology and process by using an electric press by KISTLER. A) Press-in process The press-fit technology works well when the right electrical contact between pin and PCB is ensured. The press-fit pins therefore have to be pressed in correct depth into the holes of the PCB: the centre of the © by SEMIKRON / Technical Explanation / SEMITOP® / 2015-10-14 Page 42/65 press-fit pin head has to be at least 0.5mm below the top surface and at least 0.5mm above the bottom surface of the PCB (refer to the following picture). Figure 41: Press-in depth in PCB The following parameters are based on SEMIKRON press-in tool in use: Press-in force per terminal: 95±10N Press-in speed: 10mm/s In case the press-machine is equipped with the possibility to record the force-stoke values during the press-in process, some relevant values should be considered. Details about the typical vs stroke profile are in the SEMITOP® Press-Fit mounting instructions. B) Press-out process The press-out tool allows to disassemble the module from the PCB. The following parameters are based on SEMIKRON press-in tool in use: Press-out force per terminal: 40N Press-out speed: 2-5mm/s In case the press-machine is equipped with the possibility to record the force-stoke values during the press-out process, some relevant values should be considered. Details about the typical vs stroke profile are in the SEMITOP Press-Fit mounting instructions. Each SEMITOP® Press-Fit type can be used only once. In case a module is disassembled, it can be used again. In this case the module must be soldered to the PCB due to the remaining deformation of the pins after the press-out process. An additional press-in will lead too low holding forces between the terminal and the PCB hole. In case soldering of Press-Fit module is expected, the anular ring has to be designed according to the standards for through hole components. In case the PCB is disassembled, it is possible to use it again depending on the plating material: Sn>0.5µm : PCB can be disassembled and used two additional times Au 0.05-0.2 µm over 2.5-5 µm Ni: PCB can be used only once It is possible to press multiple modules onto one PCB. In this case the modules can be pressed one by one (subsequently) or all at once. Pressing multiple modules at once requires a press-in tool according to the above detailed single tool. The tool has to ensure the correct levelling of the modules and PCB to avoid mechanical stresses. © by SEMIKRON / Technical Explanation / SEMITOP® / 2015-10-14 Page 43/65 5.6.3 PCB starter kit 5.6.3.1 Demo PCB board for GD topology, SEMITOP®4 soldered terminals Figure 42: Demo PCB for GD topology: outer dimension and schematic 5.6.3.2 Demo PCB board for DGDL topology, SEMITOP®4 soldered terminals Figure 43: Demo PCB for DGDL topology: outer dimension and schematic © by SEMIKRON / Technical Explanation / SEMITOP® / 2015-10-14 Page 44/65 These PCBs are intended only for testing purpose and not for mass production. These demo boards are intended for dynamic test and therefore they are a low stray inductance design. The boards allow as well the use of capacitors and resistor for DC link precharge circuit. Recommendation: 4 electrolytic capacitors 330uF 400V 4 resistors 68kW/4W, 1 resistor 330W/4W Suggested hole diameter for the solder pins in the circuit board is 2mm. Suggested hole diameter for the mounting pins in the circuit board is 3,6mm. Both demo PCB boards are available on request. Components such as connectors, SMDs etc., are not included in the shipment. 5.7 ESD protection IGBT and MOS circuits in SEMITOP® modules are sensitive to electrostatic charges. All SEMITOP® modules are ESD protected during transport, storage and mounting process with an ESD cover. During the handling and assembly of the modules, it is recommended to use a conductive grounded wristlet and conductive grounded workplace. 6 Technologies 6.1 Principle of Press-Fit technology Press-fit technology allows a solder free interface of SEMITOP® to the PCB and it is based on the following physical phenomenon: if two contact faces of a connection are fitted together, there are only a few spots which are really connected (metal to metal) and which carry the current – also for polished surfaces. The minimum radius of such a microscopic metal-metal contact is typically 10µm. In force fitting technologies like Press-Fit, there is always a necessary plastic deformation on these really effective contact points within the contact zone, due to the high contact pressure that occurs since the macroscopic contact force concentrates on a small microscopic contact area. That means the two faces will be merged. Thus, the effective contact zone will be increased and, that is the most important thing, a gas tight contact zone is generated, which is very robust against corrosive environments. The connection principle is the well-known cold welding effect: free electrons are generated out of the plastic deformation of both contact faces. The metal-bond electron cloud links the free electrons and connect them again with the same mechanism as in the basic metal. The bonding force increased within the first hours of the connection due to recrystallizations effects [4], [5] Figure 44: Principle of Press-Fit connection © by SEMIKRON / Technical Explanation / SEMITOP® / 2015-10-14 Page 45/65 This terminal insertion process is conducted at room temperature and therefore if brings to additional advantages of no extra heating process for surface mounted devices and no need to use heat resistant plastics for the connector housing. (the press-fit pin design in the picture is only an example and not representative of the press-fit terminal presently in use) 6.2 Pin current capability The maximum SEMITOP® pin current capability is defined by the boundary conditions of different applications (operating conditions, heatsink temperature, cooling conditions) and cannot be given as one common value. The current through the pin depends on the power losses and on the cross section area of the terminals. The contact point between pin and PCB is cooled by pin itself and terminals. By increasing the cross section area of the SEMITOP® connection terminals (i.e using bigger connectors, larger copper strips, wider PCB wires), the maximum allowable DC pin current will be increased. 6.2.1 Soldered terminals current capability A SEMITOP®3, soldered on a standard FR4 PCB with 105µm copper thickness, was assembled on an P16/120 heatsink without cooling. The pin temperature rise, at PCB contact, was measured as function of: the PCB track width; the DC current. The following measurement of the temperature rise on one pin as function of the DC current had been performed: (a) 1 (one) pin soldered on 4mm width single layer PCB track; (b) 1 (one) pin soldered on 4mm width double layer PCB track; (c) 1 (one) pin soldered on 10mm width double layer PCB track Figure 45: Pin temperature rise, at the PCB contact, as function of the PCB track width and of the DC current © by SEMIKRON / Technical Explanation / SEMITOP® / 2015-10-14 Page 46/65 6.2.2 Press-fit pins current capability One of the task of the press-fit pins is to offer an alternative PCB interface to the soldered terminals. It requires that current carrying capability of the new version is similar to the standard pin. A SEMITOP®4 equipped with soldered terminals and one equipped with press-fit pins have been compared for this purpose with the following PCB characteristic: 2 layers PCB 105µm copper thickness FR4 surface finish Assembly on heatsink at an approx. temperature of 20°C The following figure shows the current capability comparison: Figure 46: Soldered vs press-fit pin current capability The measurement was done with the help of an infrared camera and the temperature of the hottest point was defined. The curve shows a very similar temperature rise for both contact technology at a given current. As general consideration, the results show as the boundary conditions could influence the pin current capability. These results come from experimental test and are referred to specific boundary conditions. These result SEMITOP® modules have been designed in order guarantee that the physical limit is due to the silicon and not by the pin out. Customers have to take care about the right PCB track dimensioning in order to avoid any PCB over temperature at the pin contact. 6.3 Tin whisker formation Electroplated tin layers as used as lead-free solderable finish on the terminations of semiconductor devices are known to form whiskers. These whiskers are monocrystals of tin and grow within weeks to years with a diameter of some microns up to a length of several hundreds of microns or even millimeters. Thus they can cause shorts and failure of a whole electronic circuit. The following picture shows the cross section of a tin-layer on copper where large intermetallic can © by SEMIKRON / Technical Explanation / SEMITOP® / 2015-10-14 Page 47/65 be observed which grow into the tin grain boundaries: Figure 47: Electroplated tin on copper with large Cu6Sn5 intermetallics Some studies demonstrate that the whisker formation is due to compressive stresses that can be originated from the co-deposition of organics (e.g. in bright tin layers), from the irregular growth of intermetallic or from temperature variation in combination with large mismatch in CTE (coefficient of thermal expansion) between the base material and the tin layer. Effective countermeasures to avoid or minimize whisker growth is the deposition of thick tin layers (e.g.7,5 µm minimum) or the use of diffusion barriers as suppressors of irregular intermetallic. In SEMITOP® modules the whisker formation is avoided with the use of 8 µm tin layer. 6.4 Thermal interface materials Thermal grease must be applied to avoid air gaps at the interface between the module and the heat sink. The function of the grease is to flow according to the shape of the interface, allowing a metal-to-metal contact where it is possible, and filling the remaining gaps. Thermal interface material is any thermally conductive material available for this specific task. These materials can be roughly grouped in the following categories: Pastes, e.g. thermal paste with Al2O3 and boron nitride (BN) compounds Phase changes materials, based on the principle of phase transition or variation of viscosity Foils, electrically non-insulating or electrically insulating Combined systems such as waxed-coated graphite or aluminium foils SEMIKRON recommends Wacker-Chemie P12 as thermal grease material for SEMTITOP®. The junction to heatsink thermal resistance reported in SEMITOP® data sheets is valid for the modules assembled on the heatsink as described on the SEMITOP® mounting instructions. Other thermal interface materials could be used but has to be put in evidence that the thermal resistance value junction to heatsink could results different from the official datasheet values. Normalized thermal resistance value junction to heatsink for different thermal foils is shown. Thermal foils usually perform the best thermal resistance value after a curing phase. © by SEMIKRON / Technical Explanation / SEMITOP® / 2015-10-14 Page 48/65 Figure 48: Normalized thermal resistance junction to heatsink for different thermal compound Analyzed thermal foils, even after the curing phase, present worst thermal resistance values compared to the thermal resistance value measured using SEMIKRON recommended Wacker-Chemie P12 thermal grease. This has to be kept in consideration in order to avoid any junction overheating. Other comparative measurements can be performed on request. At the time of publication, intensive test has been carried out as regards the use of phase change materials (called PCM); phase change materials are not the right candidate as thermal interface material for modules without baseplate since there is high risk of DBC breaking occurrence. Normally the breaking is not visible as mechanical defect but it can be detected only via dedicated insulation test and via SAM (scanning acoustic microscope) analysis. The following picture shows the resulting areas where mechanical crack was detected (via SAM analysis) on a SEMITOP® after mounting on the heatisnk through the use of PCM. Figure 49: DBC crack with the use of PCM © by SEMIKRON / Technical Explanation / SEMITOP® / 2015-10-14 Page 49/65 7 Restriction of hazardous substances in electrical and electronic equipment (RoHS) SEMITOP® is a lead free design in accordance with the stipulations of the EU Directive proposal 2002/95/EG (RoHS) and following update Directive 2011/65/EU (RoHS2). SEMIKRON analyzed the single parts of homogeneous materials for SEMITOP® searching for 6 RoHS restricted substances: Polybrominated Biphenyls (PBB) Polybrominated Diphenyl Ethers (PBDE) Mercury Cadmium Lead Chromium VI All measures, carried out on each homogeneous materials, show RoHS compliance of the product. The following table resumes all the results: Table 25: Result of chemical analysis for 6 RoHS restricted substances Result by weight… Name of substance Allowed concentration value Plastic case loaded DBC terminals <0.05% <0.05% <0.05% 0.1% Cadmium (Cd) <0.005% <0.005% <0.005% 0.01% Mercury (Hg) <0.05% <0.05% <0.05% 0.1% Hexavalent chromium (CrVI) <0.05% <0.05% <0.05% 0.1% Polybrominated Biphenyls (PBB) <0.05% <0.05% <0.05% 0.1% Polybrominated Diphenyl Ethers (PBDE) <0.05% <0.05% <0.05% 0.1% Lead (Pb) SEMITOP® terminals are tin plated and are soldered to the DBC using lead free solder, SnAg(3,5). There are no problem in using lead free solder with SEMITOP modules (Test had been performed in Reference to IEC 600688-2-20A). © by SEMIKRON / Technical Explanation / SEMITOP® / 2015-10-14 Page 50/65 8 Laser marking All SEMITOP® modules are laser marked before shipment, according to the below picture: Table 26: SEMITOP® laser marking (1) (3) (2) (4) 1. 2. 3. 4. 5. 6. 9 (5) (6) SEMIKRON logo Type designation Housing size Date code: 6 digits --> YYWWL (L=lot) “R”: identification of RoHS compliance “ES” stands for engineering samples. All SEMITOP® are laser marked with this id-tag until the product is not released for mass production Packaging specification 9.1 Packing box SEMITOP® modules are packed into an ESD(not electrically chargeable) blister (fig.49 – left) and packed in a standard carton box (fig.49 – right): Figure 50: SEMITOP® packaging system dimensions: 154 (W) x 203(D) mm The quantities per package (either solder terminals or Press-Fit) are: SEMITOP®1 : 20 modules SEMITOP®2 : 15 modules SEMITOP®3 : 10 modules SEMITOP®4 : 6 modules © by SEMIKRON / Technical Explanation / SEMITOP® / 2015-10-14 Page 51/65 9.2 Marking of packing boxes All SEMITOP® packing boxes are marked with a sticker label that is following figure: placed on the packing box per Figure 51: Place for label on SEMITOP® packing boxes The yellow label means that the packing contains electrostatic sensitive devices. The label contains the following items: Figure 52: Label of SEMITOP® packing boxes 1. 2. 3. 4. 5. 6. 7. SEMIKRON logo Type designation Data code with 6 digits “YYWWL”. L=lot of production. “R” means the module is RoHS compliance Order: normally set to 0 Quantity per package (depending on module size) with relative bar code Part number of the module with relative bar code Datamatrix: example of the above string 241249120301015290PR301024081770160000940 Application identifiers are as follow: 241: SEMIKRON item number 10 : date code 30 : quantity per package 240: customer item number (optional) 94: customer purchase order position (optional) © by SEMIKRON / Technical Explanation / SEMITOP® / 2015-10-14 Page 52/65 9.3 Storage and shelf life conditions SEMITOP® products are qualified according to IEC 60721-4-1 and can be stored in original package as per following storage conditions: Table 27: Storage conditions Duration 2years Climatic class 1K2 (IEC 60721-3-1) Following shelf life conditions, which are not tested and based on SEMIKRON experience, are possible and should not be exceeded: Table 28: Shelf life conditions Relative humidity Storage temperature Max. 85% -25°C … +60°C Condensation Not allowed at any time Storage time Max. 2years © by SEMIKRON / Technical Explanation / SEMITOP® / 2015-10-14 Page 53/65 10 Reliability 10.1 Qualification test and special test The objective of reliability tests are: To ensure general product quality and reliability To establish design limits by performing tests under a variety of test conditions To ensure process stability and reproducibility of production processes To evaluate the impact of product and processes changes on reliability The following tests are the minimum requirements for a product release or for requalification of new and/or redeveloped modules. These are disruptive tests made on a number of production samples. Table 29: Qualification program for SEMITOP® Test Test conditions Standard reference High temperature reverse bias 1000h; Tc=140°C±5°C; 95% max. reverse blocking voltage IEC 60747 High temperature gate stress 1000h; ±VGS,max; TSTG,max IEC 60747 High voltage humidity high temperature reverse bias 504h; 85°C; 85% RH; 80% max. reverse blocking voltage IEC 60068 Part 2-67 High temperature storage 1000h; +125°C IEC 60068 Part 2-2 Low temperature storage 1000h; -40°C IEC 60068 Part 2-1 Temperature cycling 100cycles; -40 … +125°C IEC 60068 Part 2-1-14 Test Na Power cycling 20.000cycles; ∆T=110K IEC 60749-34 Resistance to solder 260°C ± 5°C; 10s ± 1s IEC 60068 Part 2-20 Test Tb Solderability 235°C ± 5°C; ageing 3 IEC 60068 Part 2-20 Test Ta Vibration Semi-sinusoidal sweep; 5g; x-y-z axis; 2h/axis IEC 60068 Part 2-6 Test Fc Shock Semi-sinusoidal pulse; 30g; ±x, ±y, ±z; 3x/direction IEC 60068 Part 2-27 Test Ea Tensile strength IEC 60068 Part 2-21 Test Ua1 SEMITOP® modules were also tested as regards the following special tests, with positive result: Vibration test (up to 10g along 3 axes) according to Q101 Rev. May 15, 1996 “Stress test qualification for automotive grade discrete semiconductors” There was no change in static parameter before and after the test. Salt Spray Test according mil-std-810F method 509.4 +JESD22-a107-a Corrosive Atmosphere test according to DIN EN 60068-2-60Ke method 3including SO2 in addition to H2S, NO2 and Cl2 (see table below) © by SEMIKRON / Technical Explanation / SEMITOP® / 2015-10-14 Page 54/65 Table 30: Special tests Condition Unit SEMIKRON test conditions H2 S [ppm] 0.4 NO2 [ppm] 0.5 Cl2 [ppm] 0.1 SO2 [ppm] 0.4 T [°C] 25 RH % 75 time days 21 Before, during and after test completion, relevant components parameters are measured in order to estimate the test influence on component lifetime. SEMITOP® Press-Fit has been qualified according to standard SEMIKRON qualification program (table 29) by testing one pilot configuration per each housing size: Table 31: SEMITOP® Press-Fit qualification test Device under test Test type SK50GD12T4Tp SEMITOP®4 Press-Fit Static test Thermal resistance Temperature cycling H3TRB HTRB Low temperature storage High temperature storage Power cycling Sinusoidal vibration SK30MLI066p SEMITOP®3 Press-Fit Static test H3TRB Temperature cycling Sinusoidal vibration Low temperature storage High temperature storage HTRB SK95D16p SEMITOP®2 Press-Fit Sinusoidal vibration Thermal resistance Dedicated tests have been performed as regards the thermal performances: SK50GD12T4T and SK200GD066T, (SEMITOP®4, both solder and press-fit version) showed same Rth.j-s performances, proving that the module design works well for the press-fit technology too and it is independent on the terminal technology. Special care was put to the vibration test and temperature cycling test for the press-fit pins. Scope of these tests was to verify that the resistance of the connection remains stable. Tests performed on SK50GD12T4Tp showed steady state performances of the contact between terminals and PCB after the test. © by SEMIKRON / Technical Explanation / SEMITOP® / 2015-10-14 Page 55/65 Figure 53: PCB example for vibration test and test arrangement for contact resistance Table 32: Details of SEMITOP® Press-Fit vibration and temperature cycling test Device under test Test description Test condition IEC standard Sinusoidal vibration Axes:Z Frequency range: 100-500Hz Acceleration: 5g Scanning speed: 1octave/minute Test duration: 2hours Random vibration Axes:Z Frequency range: 20-2000Hz Acceleration level (RMS): 5g Test duration: 2hours CEI EN 60068-2-64 Mechanical shock Axes:Z Impulse shape: semi-sinusoidal Peak acceleration value: 30g Test duration: 11ms Number of pulses: 6 (3positive and 3negative) CEI EN 60068-2-27 SK50GD12T4Tp Temperature cycling Temperature swing: -40… +125°C CEI EN 60068-2-6 CEI EN 60068-2-1-14 Test Na 10.2 Lifetime calculation Lifetime of power modules is limited by mechanical stresses that occur among the different materials of the package during working. These mechanical stresses are due to the different CTEs (coefficient of thermal expansion) of such materials as explained in Table 15. During heating up and cooling of a module the different materials expand according to their different CTEs; these materials are joined and therefore they don’t expand freely and this leads to the above mentioned mechanical stresses. When temperature changes, the mechanical stresses that occur inside the different materials layers, lead to mechanical fatigue. Result is that after a certain number of power © by SEMIKRON / Technical Explanation / SEMITOP® / 2015-10-14 Page 56/65 cycles the module fails. The typical resulting failure picture from field is the wire bond “lift off”, that means contact between chip (or DBC copper) and wire bonds is lost (refer to the picture below) [3]: Figure 54: Typical wire bond lift off observed to the electron microscope Therefore the lifetime of a module is related to the number of temperature cycles which can be withstood by the module. The temperature swing is the difference between the maximum reached temperature and the minimum temperature value. The bigger is the temperature difference, the more stress is induced. Equation 6: Number of cycles to failure ೌ ∙ ∆ ∙ ಳ ∙ೕ with: Nf = number of power cycles kB = Boltzmann-constant Ea = activation energy (9.89∙10-20 J) A = constant (3.025∙105) α = constant (-5,039) Tjm = medium junction temperature [K] ∆Tj = temperature cycling amplitude [K] Different investigations have been carried in this area, including a research project known as “LESIT study”. This study puts in evidence the relationship between the number of cycles and the temperature cycling amplitude ∆Tj = Tj,max-Tj,min and the mean temperature during power cycling Tjm. Curves for lifetime estimation of SEMITOP® modules can be extrapolated from the existing LESIT curve, to obtain the ones in the following picture: © by SEMIKRON / Technical Explanation / SEMITOP® / 2015-10-14 Page 57/65 Cycles to failure Figure 55: Dependency of the power cycling value Nf as a function of the temperature cycling amplitude Tj and the mean temperature Tjm for standard IGBT modules ∆Tj [K] At the time of publication, this curve applies to all SEMITOP® IGBT modules covering the following technologies: 063,065, 066, 125, 126, 12T4 11 Support 11.1 Customer specific power modules Customer specific power module strategy means support and production structure to handle specific demands in a fast and effective way. SEMITOP® is the most representative product platform to accomplish customer specific targets and wishes due to its flexible and low inductance design approach, and capability to integrate the latest chip technologies. Main customer advantages are: Innovation and differentiation Wide range of chip portfolio for the best in class performance offer Short time for delivery of samples Reduction of development time efforts Short time to market The SEMITOP® specific product design flows through the following process cycle: © by SEMIKRON / Technical Explanation / SEMITOP® / 2015-10-14 Page 58/65 Figure 56: Customer specific process overview The process goes through the following steps: New inquiry comes from the customer based on specific electrical requirements: possible housing wishes, electrical boundary conditions (basically same info as in SEMISEL), project time plan and business information like production volume, expected price SEMIKRON evaluates the project specifications and a technical and economic feasibility starts In case of positive feasibility result, SEMIKRON will interface to the customer with a complete offer showing all the technical aspects (SEMITOP® housing choice, pinout, internal layout in case of exclusive product) and the price offer level, sales terms and conditions Customer takes his time to evaluate SEMIKRON proposal In case of release, SEMIKRON will start to produce the first samples and they will be sent to customer for the first tests There is always a daily SEMIKRON support to achieve fast time to market when developing a new project. This means collaboration in all project phases: the customer is involved during the project definition to ensure a quick definition of engineering specifications. This helps to eliminate changes late in the design process when they are very expensive so to get the right request the first time. Software support is used to minimize the engineering workload so to ensure that every product performs according to customer requirements. This allows to produce a custom module quickly and according to customer request. 11.2 Add-on services It is possible to provide further product support to the customer besides the standard production through a so called service request process. Service process is quite simple: Customer requires for a service related to SEMITOP® product The service request is internally evaluated Customer receives a formal offer with all technical detailed and sales conditions In case of customer release, service implantation starts Example of service request are reported in the following table: © by SEMIKRON / Technical Explanation / SEMITOP® / 2015-10-14 Page 59/65 Table 33: Example of service Service type Electrical selection Special test possible besides the standard qualification program Private labelling Different packaging system to fulfill warehouse management or more stringent quality requirements Pre-applied thermal paste 11.3 SEMISEL simulation software All SEMITOP® types can be analysed with the simulation software tool “SEMISEL” using real application parameters like: DC-link voltage Switching frequency Output current Temperatures Overload conditions Others The software will return chip losses and chip junction temperature estimation for the input operating conditions. “SEMISEL” is a free software available on SEMIKRON website: http://www.semikron.com/servicesupport/semisel-simulation.html © by SEMIKRON / Technical Explanation / SEMITOP® / 2015-10-14 Page 60/65 12 Caption of figures Figure 1: SEMITOP® Press-Fit family (left) and one single step PCB assembly concept (right) ....................4 Figure 2: SEMITOP® mechanical construction ......................................................................................5 Figure 3: SEMITOP® dimension example .............................................................................................6 Figure 4: SEMITOP® positioning inside SEMIKRON portfolio ...................................................................8 Figure 5: SEMITOP® flexibility: up to 55kW output power .....................................................................8 Figure 6: SEMITOP® available solutions with fast switching technologies.................................................9 Figure 7: SiC chip combinations and SEMITOP® SiC available configuration .............................................9 Figure 8: Frequency range application for different modules................................................................ 12 Figure 9: 600V/650V IGBT technological positioning .......................................................................... 13 Figure 10: 1200V IGBT Trench technology positioning ........................................................................ 15 Figure 11: IGBT Safe Operating Area (SOA) diagram ......................................................................... 18 Figure 12: IGBT Reverse Bias Safe Operating Area (RBSOA) diagram ................................................... 19 Figure 13: IGBT Short Circuit Safe Operating Area (SCSOA) diagram ................................................... 19 Figure 14: MOSFET Safe Operating Area (SOA) diagram ..................................................................... 20 Figure 15: Diode Surge overload current vs. time .............................................................................. 21 Figure 16: SEMITOP® structure and concept of SKiiP technology.......................................................... 22 Figure 17: Thermal resistance paths for a baseplate and a baseplate-less module.................................. 23 Figure 18: Maximum output power as function of the switching frequency ............................................ 24 Figure 19: SEMITOP® package sketch (cross section view) .................................................................. 25 Figure 20: CTE comparison for different power modules ..................................................................... 26 Figure 21: System setup for Rth measurement................................................................................... 27 Figure 22: Multilayer thermal structure and thermal equivalent Cauer network ...................................... 28 Figure 23: Foster network .............................................................................................................. 29 Figure 24: Example of thermal impedance profile .............................................................................. 29 Figure 25: Typical NTC sensor characteristic ..................................................................................... 30 Figure 26: Typical NTC sensor characteristic ..................................................................................... 30 Figure 27: Position of temperature sensor on DBC substrate ............................................................... 31 Figure 28: Sketch of high energy plasma caused by melted off bond wire ............................................. 31 Figure 29: Heatsink specification ..................................................................................................... 32 Figure 30: Scratch specification for SEMITOP® modules ...................................................................... 32 Figure 31: PCB assembly and heatsink assembly ............................................................................... 35 Figure 32: Assembly steps for SEMITOP® module with soldered terminals............................................. 35 Figure 33: Assembly steps for SEMITOP® module with Press-Fit pins .................................................... 36 Figure 34: Measuring gauge by ELCOMETER...................................................................................... 37 Figure 35: SEMITOP® with pre-applied thermal paste ......................................................................... 38 Figure 36: Example of running application with multiple SEMITOP® modules on the same PCB ................ 39 Figure 37: Good soldered joint profile............................................................................................... 40 Figure 38: Details .......................................................................................................................... 40 Figure 39: Wave soldering profile .................................................................................................... 41 Figure 40: Distance between components and centre of PTH ............................................................... 42 Figure 41: Press-in depth in PCB ..................................................................................................... 43 Figure 42: Demo PCB for GD topology: outer dimension and schematic ................................................ 44 Figure 43: Demo PCB for DGDL topology: outer dimension and schematic ............................................ 44 Figure 44: Principle of Press-Fit connection ....................................................................................... 45 Figure 45: Pin temperature rise, at the PCB contact, as function of the PCB track width and of the DC current ......................................................................................................................................... 46 Figure 46: Soldered vs press-fit pin current capability ........................................................................ 47 Figure 47: Electroplated tin on copper with large Cu6Sn5 intermetallics ................................................. 48 Figure 48: Normalized thermal resistance junction to heatsink for different thermal compound ............... 49 Figure 49: DBC crack with the use of PCM ........................................................................................ 49 Figure 50: SEMITOP® packaging system ........................................................................................... 51 Figure 51: Place for label on SEMITOP® packing boxes ....................................................................... 52 Figure 52: Label of SEMITOP® packing boxes .................................................................................... 52 Figure 53: PCB example for vibration test and test arrangement for contact resistance .......................... 56 Figure 54: Typical wire bond lift off observed to the electron microscope .............................................. 57 Figure 55: Dependency of the power cycling value Nf as a function of the temperature cycling amplitude Tj and the mean temperature Tjm for standard IGBT modules .............................................................. 58 Figure 56: Customer specific process overview .................................................................................. 59 © by SEMIKRON / Technical Explanation / SEMITOP® / 2015-10-14 Page 61/65 13 Caption of tables Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table 1: SEMITOP® tolerances according to the different dimensional ranges ..........................................6 2: SEMITOP® overall housing size dimensions .............................................................................7 3: Device technology matrix ................................................................................................... 10 4: IGBT technology matrix ..................................................................................................... 10 5: SEMITOP® designation system ............................................................................................ 11 6: Comparison between available 600V/650V IGBT technologies ................................................. 13 7: Comparison between available 1200V IGBT technologies........................................................ 14 8: Comparison between available 1200V IGBT technologies........................................................ 14 9: Comparison between available 1200V IGBT technologies........................................................ 15 10: MOSFET portfolio ............................................................................................................. 16 11: SiC MOSFET portfolio ....................................................................................................... 16 12: Main SiC markets and tasks .............................................................................................. 18 13: IGBT performance comparison .......................................................................................... 24 14: IGBT performance comparison for the same reference point ................................................. 24 15: Typical material data for SEMITOP® package....................................................................... 25 16: Cosmetic issue acceptance matrix ..................................................................................... 33 17: Mounting process outline .................................................................................................. 36 18: Recommended average thermal grease thickness for SEMITOP® modules ............................... 37 19: Pre-applied thermal grease thickness with the use of a special pattern ................................... 38 20: Pre-applied thermal paste storage conditions ...................................................................... 38 21: Mounting parameters for SEMITOP® .................................................................................. 38 22: Specification of PTH with I-Sn ........................................................................................... 41 23: Specification of PTH with I-Sn for soldering of Press-Fit pins to the PCB ................................. 42 24: Specification of mounting hole diameter ............................................................................. 42 25: Result of chemical analysis for 6 RoHS restricted substances ................................................ 50 26: SEMITOP® laser marking .................................................................................................. 51 27: Storage conditions ........................................................................................................... 53 28: Shelf life conditions ......................................................................................................... 53 29: Qualification program for SEMITOP® .................................................................................. 54 30: Special tests ................................................................................................................... 55 31: SEMITOP® Press-Fit qualification test ................................................................................. 55 32: Details of SEMITOP® Press-Fit vibration and temperature cycling test .................................... 56 33: Example of service .......................................................................................................... 60 14 Caption of equations Equation Equation Equation Equation Equation Equation 1: 2: 3: 4: 5: 6: Rth,j-s as function of the temperature parameters and impressed power ............................... 26 Equation for thermal resistance and capacitance ............................................................. 28 Zth general equation for the Foster network ................................................................... 28 NTC general equation ................................................................................................... 29 PTC general equation ................................................................................................... 30 Number of cycles to failure ........................................................................................... 57 © by SEMIKRON / Technical Explanation / SEMITOP® / 2015-10-14 Page 62/65 15 Symbols and Terms Letter Symbol Term a.c, AC Alternating current Al2O3 Aluminum oxide AlN Aluminum nitride CTE Coefficient of thermal expansion Cth Thermal capacitance d.c., DC Direct current DBC Direct bonding copper di/dt Change of current per time dic/dt Change of IGBT collector current per time DIN Deutsches Institut für Normung e.V. (DIN; in English , the German Institute for Standardization) EN European standard Eoff Energy dissipation during turn-off Eon Energy dissipation during turn-on fsw Switching frequency I Indium IC Continuous collector current IC,nom Nominal collector current ICRM Repetitive peak collector current ID Continuous drain current (for MOSFET) IF(OV) Overload forward current IFSM Surge forward current ISC Short circuit current NPC Three-level inverter with clamp diode PTH Plated through-holes rds(on) Drain-source on-resistance (MOSFET) RG Gate circuit resistance Rth,c-s Thermal resistance case to sink Rth,j-c Thermal resistance junction to case Rth,j-s Thermal resistance junction to sink SiC Silicon Carbide Sn Tin TC Case temperature © by SEMIKRON / Technical Explanation / SEMITOP® / 2015-10-14 Page 63/65 TNPC Mixed voltage three-level inverter TS Heatsink temperature Tj Silicon junction temperature VCC Collector-emitter supply voltage VCE Collector-emitter voltage VCES Collector-emitter voltage with gate-emitter short circuited VCE,sat Collector-emitter saturation voltage VDD Drain-source supply voltage (MOSFET) VDS Drain-source voltage VR (Direct) reverse voltage VRRM Repetitive peak reverse voltage Zth,j-s Transient thermal impedance junction to heatsink A detailed explanation of the terms and symbols can be found in the "Application Manual Power Semiconductors" [2] 16 References [1] www.SEMIKRON.com [2] A. Wintrich, U. Nicolai, W. Tursky, T. Reimann, “Application Manual Power Semiconductors”, ISLE Verlag 2015, ISBN 978-3-938843-83-3 [3] “Power Cycling with High Temperature Swing of Discrete Components based on Different Technologies” (IEEE Power Electronics Specialists Conference 2004 PESC04, pp2593-2598) [4] www.powerguru.com [5] Self acting PressFIT module; Thilo Stolze; Infineon Technologies AG, Max-Planck-Strasse 5, 59581 Warstein. [6] Reliability of PressFit connections, T.Stolze, M.Thoben, M.Kich, R.Severin, Infineon Technologies AG, Max-Planck-Strasse 5, 59581 Warstein. © by SEMIKRON / Technical Explanation / SEMITOP® / 2015-10-14 Page 64/65 17 History SEMIKRON reserves the right to make changes without further notice herein Revision no. 3 Contents Update of contents and use of the new template 18 Disclaimer SEMIKRON reserves the right to make changes without further notice herein to improve reliability, function or design. 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