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October, 2014
Vol 3 Issue 10
ISSN 2278 – 0211 (Online)
Design of Impedance Matching Circuit
Shiwani Shekhar
B.Tech Final Year Student, Electronics & Communication Engineering Department
J.K. Institute of Applied Physics & Technology, University of Allahabad, Allahabad, India
Ripudaman Singh
B.Tech Final Year Student, Electronics & Communication Engineering Department
J.K. Institute of Applied Physics & Technology, University of Allahabad, Allahabad, India
Abstract:
This report explains the intuitive technique for designing the impedance matching circuit. Impedance is the opposition by a
system to the flow of energy from a source. For constant signals, this impedance can also be constant. For varying signals, it
usually changes with frequency. The energy involved can be electrical, mechanical, magnetic or thermal. The concept
of electrical impedance is perhaps the most commonly known. Electrical impedance, like electrical resistance, is measured
in ohms. In general, impedance has a complex value; this means that loads generally have a resistance component (symbol: R)
which forms the real part of Z and a reactance component (symbol: X) which forms the imaginary part of Z. For maximum
efficiency impedance matching is very essential.
1. Introduction
In electronics, impedance matching is the practice of designing the input impedance of an electrical load or the output impedance of its
corresponding signal source to maximize the power transfer or minimize signal reflection from the load.
1.1. Maximum Power Transfer Theorem
Designing circuits involves the efficient transfer of the signals. In the early days of electric motors, it was found that to get the most
efficient transfer of power from the battery (source) into the motor (load) required that the resistance of the different parts of the
circuit be the same, in other words, matched; this is known as the maximum power transfer theorem. For DC circuits, maximum
power will be transferred from a source to its load if the load resistance equals the source resistance. A simple proof of this theorem is
given by the following example:
Figure 1: The circuit and graph to prove the condition for maximum power transfer.
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;
2. Impedance Matching
Impedance Matching was originally developed for electrical power, but can be applied to any other field where a form of energy (not
necessarily electrical) is transferred between a source and a load. The first Impedance Matching concept in RF domain was related to
antenna matching. Designing an antenna can be seen as matching the free space to a transmitter or receiver. Impedance Matching is
always performed between two specified terminations. The main purpose of Impedance Matching is to match two different
terminations (Rsource and RLoad) through a specific pass-band, without having control over stop-band frequencies. We may assume
that component losses are negligible but parasitic effects need to be considered.
The main role in any Impedance Matching scheme is to force a load impedance to “look like” the complex conjugate of the source
impedance, and maximum power can be transferred to the load. When a source termination is matched to a load with passive lossless
two-port network, the source is conjugated matched to the input of the network, and also the load is conjugate matched to the output of
the network. Any reactance between Rs and RL reduces the current in RL and with it the power dissipated in RL. To restore the
dissipation to the maximum that occurs when Rs = RL, the net reactance of the loop must be zero. This occurs when the load and
source are made to be complex conjugates one of another, so they have the same real parts and opposite type reactive parts. If the
source impedance is Zs = R + jX, then its complex conjugate would be Zs* = R − jX.
Figure 2: Impedance Matching of a resistive source and a complex load for maximum power transfer
Using only one series reactive element between two equal resistive terminations creates a voltage drop that reduces the voltage across
the load. Impedance Matching can eliminate or minimize the unwanted reactance through a range of frequencies. The matching
process becomes more difficult when real parts of the terminations are unequal, or when they have complex impedances. The second
reason is device protection – If RF circuit is not matched we get reflected power. This reflected power builds standing waves on the
transmission line between the source and load. Depending on the phase between the forward and reflected both waves can either
subtract or add. Because of that on the line we can get places where the voltage is the sum of both voltages or eventually places where
the voltage equals zero (maximum current). If the standing wave is positioned in such a way on the transmission line so that the
maximum voltage or current is applied to the power FET’s they can be destroyed.
2.1. Impedance matching using L-C Section
Any two resistive terminations can be simultaneous matched by adding two reactive elements between them.
If we need to match in a narrow frequency a source Rs and a load RL, we can get almost the same performance by using a high-pass
or low-pass network configuration. The pass-band performances near the matching frequency are very similar for both networks,
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when the out-of-band characteristics of the low-pass and high-pass are different. A low-pass rejects signals at the high-end, and allow
passing at low frequencies. The high-pass network does the opposite.
Figure 3: Four possible single matching L-C networks
2.2. Impedance matching with Transmission lines using Smith Chart
Smith Chart is a good choice when Impedance Matching is done using transmission lines.
 Cascading transmission lines always follow a clockwise rotation on the Smith Chart.
 Moving away from a termination on a transmission line, always follow a clockwise circular rotation on the Smith Chart.
 If the chart is normalized to the characteristic impedance of the transmission line, the rotation is a along a concentric circle.
 The radius of the concentric circle is determined by the normalized termination.
Figure 4: A complex source can be matched to the 50Ω load with a cascade series transmission line
And a parallel short-circuited stub, there are 4 adjustable parameters: ZTL, ӨTL, ZSS, ӨSS
A parallel stub is treated as an equivalent parallel inductor or capacitor at specific frequencies, depending on what type of reactance it
represents. If we use several cascade lines with different characteristic impedances, the Smith chart must always be renormalized to
the appropriate impedance.
Figure 5: Smith Chart Alignment of Load And Source Impedance
Following a counter-clockwise rotation on the chart is equivalent to de-embedding, which is incorrect for this application.
Moving away from any termination (source or load) with a transmission line, always leads to a clockwise rotation.
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3. Basic Design Steps
1. Select the Smith Chart from Tools option. Then the following drop down menu will be displayed.
Figure 6: Smith Chart Utility Window






This is the network schematic window.
This is the plot window.
These are the components we may add such as series inductor, series capacitor, etc.
Main toolbar.
The smith chart.
This is where we set source and load impedance.
2. Select Zs* from #1 window and set the source impedance. Similarly, set the load impedance.
3. Now from window#3, add line length. This is a standard transmission line. Notice on the smith chart that your cursor draws the
clockwise (toward the generator).
4. After selecting line length, make it almost half wavelength long. The cursor should draw almost a complete circle, and it should end
up 'almost' back at the load.
5. Now, select an open circuit or short circuit stub, and again, make it long enough to draw out another, almost complete circle. Notice
the path that cursor takes. Also, observe that our design (window#1) consists of load, line, stub, and source. Right now, your
impedance is the pink square, but you want it to be at the center, to match the source.
Figure 7: Smith Chart Utility Window with open stubs
6. In window #1, select the t-line. Now you can manipulate its length, either numerically below window #1, or graphically on the
chart. As you change length, the circle drawn out by the stub moves along with the termination of the line. Reduce the t-line length
until the ‘circle’ passes thru the origin. Like so:
7. Now, select the stub and reduce its length until you end up at the origin.
8.Using the LineCalc tool the length and width of corresponding transmission line is determined.
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9. Now, using these values we draw the schematic of the impedance matching circuit. And then corresponding layout and graph can be
eventually obtained.
4. Design Specifications for Different Impedance Matching Circuits
For Fc = 1.5 GHz :
Source Impedance = 50 Ohms, Load Impedance = 200 Ohms (using MLOC):
MT EE_A DS
Tee2
Subst="MSub1"
W 1=4.809 mm
W 2=4.809 mm
W 3=4.809 mm
Term
Term1
Num=1
Z=50 Ohm
MLOC
T L2
S ubst="MSub1"
W =4.80 mm
L=23.205 mm
MLIN
TL1
Subst="MSub1"
W =4.809 mm
L=32.615 mm
MT EE_A DS
Tee1
Subst="MSub1"
W1=4.809 mm
W2=0.14 mm
W3=4.089 mm
T erm
T erm2
Num=2
Z=200 Ohm
MLOC
TL3
Subs t="MS ub1"
W=4.809 mm
L=8.354 mm
MSub
MS UB
MS ub1
H=1.57 mm
Er=2.2
Mur=1
Cond=5.8e7
Hu=3.9e+034 mil
T=0.017 mm
TanD=0.0009
Rough=0 mil
Bbase=
Dpeaks=
S-PARAMETERS
S_Param
SP1
Start=0 GHz
Stop=5 GHz
Step=25 MHz
Figure 8: Schematic View
Figure 9: Output Graph
Source Impedance = 50 Ohms, Load Impedance = 200 Ohms (using MLSC)
MT EE_ADS
T ee2
Subst="MSub1"
W1=4.809 mm
W2=4.809 mm
W3=4.809 mm
T erm
T erm1
Num=1
Z=50 Ohm
MLSC
T L2
Subst="MSub1"
W=4.809 mm
L=13.5 mm {t}
MT EE_ADS
T ee1
Subst="MSub1"
W1=4.809 mm
W2=0.14 mm
W3=4.089 mm
MLIN
T L1
Subs t="MSub1"
W =4.809 mm
L=25.65 mm {t}
T erm
T erm2
Num=2
Z=200 Ohm
MLSC
T L3
Subst="MSub1"
W=4.809 mm
L=32.5 mm {t}
M Sub
S-PARAMETERS
S_Param
SP1
Start=0 GHz
Stop=5 GHz
Step=25 MHz
MSUB
MSub1
H=1.57 mm
Er=2.2
Mur=1
Cond=5.8e7
Hu=3.9e+034 mil
T =0.017 mm
T anD=0.0009
Rough=0 mil
Bbas e=
Dpeaks=
Figure 10: Schematic View
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Figure 11: Layout View
Figure 12: Output Graph
Source Impedance = 50 Ohms, Load Impedance = 120+j*90 Ohms (using MLOC)
MT E E_A DS
T ee2
S ubs t="MSub1"
W 1=4.809 mm
W 2=4.809 mm
W 3=4.809 mm
T erm
T erm1
Num=1
Z=50 Ohm
MLOC
T L2
Subs t="MSub1"
W=4.809 mm
L=49.5 mm {t}
MT E E_A DS
T ee1
S ubs t="MS ub1"
W 1=4.809 mm
W 2=0.14 mm
W 3=4.089 mm
MLIN
T L1
S ubs t="MSub1"
W =4.809 mm
L=14.355 mm {t}
T erm
T erm2
Num=2
Z=200 Ohm
MLOC
T L3
Subs t="MS ub1"
W=4.809 mm
L=7.155 mm {t}
MSub
S- PARAMETERS
S_P aram
SP 1
Start=0 GHz
Stop=5 GHz
Step=25 MHz
MSUB
MSub1
H=1.57 mm
E r=2.2
Mur=1
Cond=5.8e7
Hu=3.9e+034 mi l
T =0.017 mm
T anD=0.0009
Rough=0 mi l
B base=
Dpeaks =
Figure 13: Schematic View
Figure 14: Layout View
Source Impedance = 50 Ohms, Load Impedance = 120+j*90 Ohms (using MLSC)
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MT EE_ADS
T ee2
Subst="MSub1"
W 1=4.809 mm
W 2=4.809 mm
W 3=4.809 mm
T erm
T erm1
Num=1
Z=50 Ohm
MLSC
T L2
Subst="MSub1"
W =4.809 mm
L=14.85 mm
MT EE_ADS
T ee1
Subs t="MSub1"
W 1=4.809 mm
W 2=0.14 mm
W 3=4.089 mm
MLIN
T L1
Subs t="MSub1"
W =4.809 mm
L=23.85 mm
T erm
T erm2
Num=2
Z=120+j *90
MLSC
T L3
Subs t="MSub1"
W =4.809 mm
L=34.45 mm
MSub
MSUB
MSub1
H=1.57 mm
Er=2.2
Mur=1
Cond=5.8e7
Hu=3.9e+034 mi l
T =0.017 mm
T anD=0.0009
Rough=0 mil
Bbase=
Dpeaks=
S-PARAMETERS
S_Param
SP1
Start=0 GHz
Stop=5 GHz
Step=25 MHz
Figure 15: Schematic View
Figure 16:.Layout View
Figure 17: Output Graph
Source Impedance = 50 Ohms, Load Impedance = 141-j*12 Ohms (using MLOC)
:
MT EE_ADS
Tee2
Subst="MSub1"
W1=4.809 mm
W2=4.809 mm
W3=4.809 mm
T erm
T erm1
Num=1
Z=50 Ohm
MLOC
T L2
Subs t="MSub1"
W =4.80 mm
L=51.15 mm
MLIN
T L1
Subs t="MSub1"
W=4.809 mm
L=9.987 mm
MT EE_ADS
T ee1
Subs t="MSub1"
W 1=4.809 mm
W 2=0.14 mm
W 3=4.089 mm
T erm
T erm2
Num=2
Z=141-j *12
MLOC
TL3
Subst="MSub1"
W=4.809 mm
L=9.672 mm
MSub
S-PARAMETERS
S_Param
SP1
Start=0 GHz
Stop=5 GHz
Step=25 MHz
MSUB
MSub1
H=1.57 mm
Er=2.2
Mur=1
Cond=5.8e7
Hu=3.9e+034 mil
T =0.017 mm
T anD=0.0009
Rough=0 mi l
Bbase=
Dpeaks=
Figure 18: Schematic View
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Figure 19: Layout View
Figure 20: Output Graph
Source Impedance = 50 Ohms, Load Impedance = 141-j*12 Ohms (using MLSC)
MT EE _A DS
T ee2
Subs t="MSub1"
W1=4.809 mm
W2=4.809 mm
W3=4.809 mm
T erm
T erm1
Num=1
Z=50 Ohm
MLSC
T L2
Subst="MS ub1"
W=4.809 mm
L=15.12 mm
MT EE_ADS
T ee1
Subs t="MSub1"
W1=4.809 mm
W2=0.14 mm
W3=4.089 mm
MLIN
T L1
S ubs t="MSub1"
W=4.809 mm
L=32.4 mm
T erm
T erm2
Num=2
Z=141-j *12
MLS C
T L3
Subs t="MSub1"
W=4.809 mm
L=25.388 mm
MSub
S-PARAMETERS
S _P aram
S P1
S tart=0 GHz
S top=5 GHz
S tep=25 MHz
MSUB
MSub1
H=1.57 mm
Er=2.2
Mur=1
Cond=5.8e7
Hu=3.9e+034 mil
T =0.017 mm
T anD=0.0009
Rough=0 mi l
Bbas e=
Dpeaks=
Figure 21: Schematic View
Figure 22: Layout View
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Figure 23: Output Graph
Source Impedance = 59+j*28 Ohms, Load Impedance = 10-j*180 Ohms (using MLOC)
MT E E_ADS
T ee2
Subs t="MSub1"
W1=4.809 m m
W2=4.809 m m
W3=4.809 m m
T erm
T erm1
Num=1
Z=59+j *28
MLOC
T L2
Subs t="MSub1"
W=4.809 mm
L=34.10972 mm {t}
MLIN
T L1
S ubst="MSub1"
W=4.809 mm
L=18.56224 mm {t}
MT EE _A DS
T ee1
S ubst="MSub1"
W1=4.809 mm
W2=0.14 mm
W3=4.089 mm
T erm
T erm 2
Num=2
Z=10-j* 180
MLOC
T L3
Subs t="MS ub1"
W=4.809 m m
L=11.78408 m m {t}
MSub
MSUB
MSub1
H=1.57 m m
E r=2.2
Mur=1
Cond=5.8e7
Hu=3.9e+034 mi l
T =0.017 mm
T anD=0.0009
Rough=0 mi l
B base=
Dpeaks=
S- PAR AMETERS
S _P aram
S P1
S tart=0 GHz
S top=5 GHz
S tep=25 MHz
Figure 24: Schematic View
Figure 25: Layout View
Figure 26: Output Graph
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5. Conclusion
In this report, we have discussed the techniques of impedance matching circuit at different frequencies. We also discussed the design
of impedance matching circuits using smith chart. Design specification for different impedance matching circuit is also discussed in
detail. Impedance matching with Transmission lines using Smith Chart also encompasses various methods for impedance matching.
6. References
1. D.M Pozer, “Microwave Engineering”, John Wiley, 2000.
2. Agilent ADS 2002, Agilent Technologies, Palo Alto, CA,2002.
3. G.L.Matthaei, L. Young, and E.M.T. Jones, Microwave Filters, Impedance-Matching
4. Networks, and Coupling Structures, McGraw-Hill, NewYork, 1964.
5. D. M. Pozar, “Microwave Engineering”, John Wiley & Sons Inc., 1998.
6. www.wikipedia.org
7. shodh.inflibnet.ac.in:8080/jspui/bitstream/123456789/1070/2/
8. vuir.vu.edu.au/600/1/03chapters4-6
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