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Design And Analysis of A Power Efficient
Cascode-Compensated Amplifier
Shafqat Ali, Steve Tanner and Pierre Andre Farine
Swiss Federal Institute of Technology (EPFL), 1015 Lausanne, Switzerland.
[email protected], [email protected]
Abstract— In the paper, we present the design focused analysis of
a power efficient cascode-compensated amplifier. The analysis,
presented here, is much more intuitive than the reported work so
far. Based on this analysis, an amplifier in UMC 0.18 µm
technology is designed. Cascode compensation along with other
power saving techniques results in a power efficient amplifier
that achieves a relatively high figure of merit (1927
MHz.pF/mW). The designed amplifier is compared with the state
of the art in the literature.
Keywords: Cascode Compensated Amplifier,Power Efficiency.
I.
INTRODUCTION
The rapid expansion of ubiquitous electronic communication
has introduced countless battery operated portable devices in
the market. These battery operated devices in turn have put
stringent requirements on the power efficiency of electronic
circuits. Amplifiers are the basic yet the most critical elements
of any electronic circuit design. As a result, improving power
efficiency of amplifiers continues to remain an active area of
research in the field of electronic circuit design.
Most of the electronic circuits use feedback to desensitize
the performance from the variations in gain and other
amplifiers parameters. Feedback relies on high gain so most of
the amplifiers are multi-stage type. As a result frequency
compensation is needed to stabilize the amplifiers. The most
basic and widely used technique so far has been the miller
compensation, among others. However, Miller compensation is
not very power efficient. The transconductor efficiency is
defined by (1) [1].
Te  2  GBW  CL g m
(1)
It implies that for a given load capacitance, the higher the gain
bandwidth product to gm ratio, the higher the transconductor
efficiency. By definition, the trans-conductor efficiency of a
single stage amplifier is always unity. A single stage amplifier
is however not very practical in applications where relatively
higher gain is needed. Consequently multi-stage amplifiers are
of considerable interest. For a Miller-compensated two-stage
amplifier the relationship of gm of second stage with the GBW
of amplifier is given by (2) (assuming a phase margin of ~ 60).
gm2  2  CL  GBW
(2)
As a result the transconductor efficiency is less than ½ [1] (the
gm of the first stage is not included in this calculation).
An important figure of merit for comparing the amplifiers is
given by (3) [1].
FOM PWR  ft  CL P (MHz.pF/mW)
(3)
Here CL is load capacitance and ft is unity gain frequency of
amplifier and P is the power consumption in mW.
The rest of the paper is organized as follows. In section II
we discuss the advantages of cascode-compensated amplifier
and give examples from the literature on this type of amplifier.
In section III we present a design oriented analysis. Section IV
gives the design and simulation results of the cascode
compensated amplifier in UMC 0.18 µm technology and
compares it with the other reported designs. It is followed by a
conclusion in section V.
II.
REVIEW
A number of papers have addressed the cascode
compensation [2-5]. A major benefit of the cascodecompensated amplifiers is its power efficiency. For example in
[2], authors find that it can achieve 1.8 times more GBW than a
miller compensated amplifier for the same phase margin and
power consumption. Another benefit of the cascodecompensated amplifier is its low area. This is because the
compensation capacitor is relatively smaller than the one in the
standard miller-compensated amplifier. A major reason for the
above mentioned benefits is that in cascode compensation the
feed-forward path almost does not exist which improves the
stability. Another benefit of the cascode compensation is that it
results in better power supply rejection ratio (PSRR) [6].
Besides the advantages there are some limitations as well
that will be discussed during the presentation of the design of
the amplifier.
The works like [2-5] have considerable stress on small
signal analysis which results in higher mathematical
complexity. For example, Aminzadeh et al., in [3], present an
open loop analysis of the cascode amplifier and then derive the
parameters of the second order linear system by equating the
transfer function of the amplifier to the transfer function of a
standard second order system. As a result, the approximate
expressions for the damping factor and the natural frequency of
second order system are obtained. This is valuable information
however in real design scenario, a much more direct and
intuitive way of looking at the circuit is often desired.
III.
DESIGN ORIENTED INTUITIVE ANALYSIS
In this section we present the design oriented analysis of the
cascode-compensated amplifier. A diagram of the amplifier
is shown in Fig. 1.
Figure 3: ‘Za’ Vs Frequency
Figure 1: A basic cascode compensated amplifier
The biasing of the circuit is not being shown in Fig. 1 and the
three important nodes have been labeled by ‘a’, ‘b’ and ‘c’. To
analyze this circuit intuitively we zoom on to the most
important part of the whole amplifier which is shown in Fig. 2.
If we increase the frequency beyond s1, Za does not
decrease anymore. Instead it becomes constant in magnitude.
This is because after s1, the load capacitance ‘CL’ starts to
dominate at node ‘c’. As a result the current generated by M1
(because of V) gets divided between CL and Cc. So the
magnitude of the frequency at point s1 must be equal to the
frequency of the load pole (point at which CL starts to dominate
at node ‘c’) which is given by (6). (Here Cc is added to CL
because it is effectively in parallel with CL)
s1  1 RL .(CL  Cc)
Figure 2: Simple Circuit For Analysis
The total impedance (Zt) at node ‘a’ is the parallel
combination of Za and Zp. Za is the impedance of the circuit
(made up of M5, Cc, M1, RL and CL) while Zp is the parasitic
impedance (RA ¦¦ CA). The behavior of Zp, as a function of
frequency is very straightforward, as it is just a resistance in
parallel with a capacitance. The behavior of Za is slightly more
complex than this and is sketched in Fig. 3. To understand the
behavior of impedance Za, we apply a test voltage source (with
amplitude V) at node ‘a’ and determine the current that flows
into node ‘a’. Please note that node ‘a’ is directly connected to
the gate of M1 as well. At very low frequencies the voltage at
the drain of M1 (node ‘c’) will be given by
Vc  gm1  RL V
(6)
The resistance looking into source of M5 is ~1/gm5. This
resistance is in series with the capacitor Cc. If we further
increase the frequency this resistance starts to dominate
because the impedance value of Cc becomes less than 1/gm5.
After point s2, the load capacitance presents relatively low
impedance path for current to flow into than the Cc branch. As
a result the current flowing into node ‘a’ decreases and the
solid line starts to rise. Therefore the frequency at point s2 is
the one at which the impedance of Cc becomes equal to 1/gm5.
Therefore this frequency is given by (7).
s 2  gm5 Cc
(7)
Knowing Za and Zp we can now determine the behavior of
Zt which is the parallel combination of Za and Zp. The
frequency behavior of Zt is shown in Fig. 4 as a solid line
while the behavior of Za and Zp is shown by dotted lines.
(3)
Here gm1 is the transconductance of M1 and RL is load resistor
as shown in Fig. 2. The impedance at node ‘b’ is small (just
~1/gm5). As a result the voltage across the capacitor Cc is also
gm1.RL. Consequntly the current flowing into node ‘a’ and Za at
low frequencies is given by (4) and (5) respectively.
Ia  V  sCc  g m1  RL
(4)
Za  1/( sCc  g m1  RL )
(5)
As shown by (5), Za at low frequencies is capacitive. Fig. 3
(until the point s1) shows this capacitive trend of Za. The
compensation capacitor behaves as if its value is multiplied by
the gain of the second stage (~gm1RL, see equation (5) ).
Figure 4: ‘Zt’, ‘Za’ and ‘Zp’ Vs frequency
From this simple analysis we find that Zt has at least two
poles and a zero. The location of the first pole (p1) can be
easily calculated by equating Za and Zp at low frequency. The
low frequency value of Za is given by (5) while the low
frequency value of Zp is just RA. Consequently p1 is given by
p1  1/(Cc  g m1  RL  RA )
(8)
The value of zero z1 is already shown in Fig. 3. It corresponds
to the frequency where Za stops to decrease, as already
explained. Please note that this zero occurs exactly at the
frequency where the load pole occurs.
Just as we found p1 by equating Za and Zp at low frequency,
we can determine p2 by equating Za and Zp at higher
frequencies (as they cross each other second time as shown in
figure 4). The higher frequency value of Zp is simply 1/sCA.
The value of Za at frequencies above z1 (in Fig. 4) can be
simply calculated from a simplified version of Fig. 2. At this
frequency the resistance RL can be ignored since CL now
dominates. As a result the current that is generated by M1
(because of V) gets divided between Cc and CL in proportion to
the values of these capacitances so we can write the Za value
(at these frequencies to be)
Za  g m1 (Cc) /(Cc  CL )
(9)
Equating Za with the value of Zp (=1/sCA) we get the value of
p2 as
 Cc  g m1

p 2  
 C A  Cc  CL
(10)
be 2 times higher than the gain bandwidth of the amplifier.
This condition is given by (12).
 Cc  gm1
1
 
2
 CA  Cc  CL GBW
C  (Cc  C L )  GBW
 g m1  2 A
Cc
(12)
(13)
Usually the load capacitance and GBW are the given. For a
minimum power design CA (the parasitic capacitance at node
‘a’) has to be minimized. One the one hand, Cc should not be
so big that it becomes a significant load on the second stage
and on the other hand it should also be not so small that
advantage factor (Cc/CA , as given by (10)) is lost. The noise
specifications for the amplifier will affect the choice of Cc
value. Therefore the designer should focus on reducing C A as
much as possible.
The above mentioned guidelines have been used to design
the amplifier shown in Fig. 6. The amplifier has been designed
to be used in a switched capacitor circuit. There are two clock
phases in the circuit, namely ph1 and ph2. The common mode
control and some of the biasing has been omitted for clarity of
the figure. The dimensions of the amplifier are given in the
table I.
Compared to a standard miller-compensated amplifier the p2
of this amplifier is a factor (Cc/CA) higher in frequency.
Having determined the impedance Zt at node ‘a’ we can simply
draw an even simplified version of amplifier (see Fig 5). Since
the load pole is cancelled by the zero of Zt the poles of Zt
become the poles of the whole amplifier.
Figure 6: Cascode Compensated Amplifier
Table I: Transistor Dimensions
Figure 5: Simplified Cascode Compensated Amplifier
Since the dominant pole of amplifier is given by (8). The gain
bandwidth of the amplifier is simply
GBW  g m7 / Cc
IV.
(11)
DESIGN OF A CASCODE COMPENSATED AMPLIFIER
Having determined the basic behavior of the amplifier we
can embark on the design of an actual amplifier. For this
design we fixed the required phase margin to be > 60° (and CL
to be 3pF). This means that the non-dominant pole (p2) has to
Transistor
Width
Length
M13-M14
24 µm
400nm
M5-M6
06 µm
180nm
M2-M3
04 µm
180nm
M1,M4
06 µm
180nm
M8-11
12 µm
180nm
To gain more gm for a given current in the output stage, the
output stage is a push pull kind of stage. Capacitor Cb acts as
the DC level shift from node ‘a’ to the gate of the PMOS
devices (M8,M11). During clock phase ph1 (which is the reset
phase of the amplifier) the capacitor Cb is connected to the
diode connected transistors M7/M12. In the amplifying phase
(ph2), Cb are connected to the PMOS device (M8,M11). The
effective gm of the output stage is thus the sum of gms of
NMOS and PMOS devices of 2nd stage.
To get more gain from the amplifier, cascodes can be added
to the output stage. This will also help in reducing the
GBW Simulations
100
Voltage Gain
Phase
50
Gain/Phase
0
-50
-100
-150
-200
0
10
Figure 8: Amplifier Layout (160µm x 190 µm)
10
1
10
2
10
3
10
4
10
5
10
6
10
7
10
8
Frequency
Figure 7: Gain And Phase Vs Frequency
capacitance CA, by eliminating the Miller multiplication of
Cgd of M1 and M4. This would however result in lower head
room which is not a problem in some circuits for example feed
forward sigma delta modulators etc [7]
The input transistor is sized to lower 1/f noise as much as
possible. The nominal tail current is 5 µA. The total current
consumption, including the biasing, is 16 µA. The amplifier
achieves a gain bandwidth of ~18.5 MHz, with a phase margin
of 71°, as shown in Fig. 7. The load capacitance is 3 pF.
FOMPWR (as given by (3)) therefore comes out to be ~1927. A
set of corner simulations were done as well. The results of the
corner simulations are shown in table II.
Table II: Corner Simulation Results
Corner Name
GBW MHz
Typical
18.5
Slow Slow
18
Slow Fast
18.6
Fast Slow
18.4
Fast Fast
19
A comparison with the state of the art is presented in table III.
Table III: Comparison
Work
This Work
[5]
[8]
[9]
[10]
[11]
[12]
[13]
FOM
(MHz.pF/mW)
1927
263
772
423
32
833
392
596
V.
Technology
0.18µm
0.18µm
0.18µm
0.18µm
-65nm
0.18µm
0.18µm
CONCLUSION
In this paper we have presented an intuitive and design
oriented analysis. We also give a design example of a power
efficient cascode compensated amplifier. The designed
amplifier is compared with the other published work and
shows promising power efficiency.
ACKNOWLEDGEMENTS
This work was funded by the NanoTera program of Swiss
National Science Foundation (SNF) under Grant No. 6309903.
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