Download Utilization of Ballistic Deflection Phenomena for Room Temperature

NSF Nanoscale Science and Engineering Grantees Conference, Dec 3-6, 2007
Grant # : 0609140
NANO OVERVIEW
Utilization of Ballistic Deflection Phenomena for Room Temperature Devices
and Circuitry
NSF NIRT Grant 0609140
Marc Feldman, Martin Margala+, Paul Ampadu, Yonathan Shapir
University of Rochester, +University of Massachusetts Lowell
Scope of Program
This NIRT project focuses on nonlinear ballistic transport at room temperature. Ballistic
transport is usually considered an aspect of the quantum physics regime, and has been studied
intensively at cryogenic temperatures. Nevertheless certain ballistic deflection effects in
mesostructures are quite robust at room temperature. An example is the "ballistic rectifier." The
ballistic deflection nonlinearity can be used to construct other devices and circuitry operating at
room temperature that are very different from conventional circuitry. In this research project,
ballistic deflection devices and circuitry are fabricated, tested, and analyzed. Simultaneously, the
physics of nonlinear room temperature ballistic transport is investigated and the architectural
challenges presented by the unfamiliar requirements and opportunities of circuitry based upon
mesoscopic ballistic transport are being explored. This project utilizes a multidisciplinary
approach, investigations at the physics, the device, the circuit, and the architectural level.
Experiments and Results
Several devices of different geometries were fabricated on separate runs. The substrate was
fabricated using Molecular Beam Epitaxy, and consists of lattice matched layers of InGaAs and
InAlAs on an InP substrate. Device fabrication consists of only two lithography steps. First, a
suitable hard-mask is patterned using electron beam
lithography. This mask is then used in the etching of the
Vdd
substrate via an inductively coupled reactive ion etcher.
Contacts are formed using a standard Ni-Ge-Au stack that
was annealed at 400 degrees Centigrade until ohmic. In
L-drain
R-drain
Fig. 1, a scanning electron microscope image of a typical
BDT structures is shown. The dark areas including the
triangle region indicate the removed material from the
L-gate
R-gate
2DEG structure. Several IV curve measurements were
performed on a six probe station using an Agilent 4156C
Parameter Analyzer at room temperature. From the IV
Vss
curve measurements several interesting effects were
observed. In Fig. 2, we see the current response for a
Fig. 1. BDT with 500nm gates and 80nm series of drain voltages as a function of a gate bias.
gate-channel spacing.
The gates were biased push-pull with the left gate used as
the reference in the charts (as an example of a push-pull bias, when the left gate is at -0.1V the
right gate will be at +0.1V). There are two significant results of this measurement. First, we
observe that the current first increases as a function of a gate voltage then it decreases.
NSF Nanoscale Science and Engineering Grantees Conference, Dec 3-6, 2007
Grant # : 0609140
Second, we notice that the
drain current increases as a
function of applied bias as well
as the transconductance. The
fact that the current rises and
then falls as a function of gate
bias is attributed to the channel
first being pinched off, then as
the gate voltage is further
increased, the electrons are
steered from the right drain
into the left drain, and then
eventually the channel pinches
off again. At the peak between
the steering region and the
pinch-off region, we have
Fig. 2. IV characteristic of the left drain port as a function of push- pull maximum conductivity. The
gate voltage (in reference to the left gate), an increase in drain voltage
right drain (which is not
increases the transconductance, near linearly for voltage beyond 1V.
shown) has the identical
response, but mirrored around the center axis. Subtle differences in amplitude occur due to
process variation, though some devices have been measured with near identical left and right
drain response. This positive and negative transconductance region characteristic enables design
of circuits that are inverting and non-inverting, depending only on gate offset voltage. The shape
of this transfer characteristic makes it ideal for a frequency doubler. A gate bias that enables the
input to swing past either side of the peak output current will result in an output signal that is
twice the input frequency. A
circuit utilizing this effect can
have a significant gain.
We conducted a numerical
curve fit shown in Fig. 3, the
results indicate that there is a
quadratic and linear current
region. The quadratic region
suggests that the channel is
being modulated by a
depletion region in a similar
fashion as a field effect
device whereby as the gate
voltage
becomes
more
positive,
a
conducting
channel opens. The linear
region appears to form as a
Fig. 3. Quadratic and linear curve fitting of the current response
result of the channel being
as a function of gate voltage.
closed off by a depletion
region induced by the other gate, even though locally the channel is being enhanced by the
positive gate.
NSF Nanoscale Science and Engineering Grantees Conference, Dec 3-6, 2007
Grant # : 0609140
As suggested by K. Hieke et al, negative voltages dominate the modulation of the channel [12].
The region with a gate voltage between -0.1 Volts and 0.2 Volt, for the graph in Fig. 3, is the
transition region between the quadratic channel opening and the linear pinch-off of the channel.
The positive and negative slopes of the drain current as a function of gate voltage necessitate the
use of two graphs to plot drain current versus drain-source voltage. In Fig. 4a the negative gate
voltages are shown, and the positive gate voltages are shown in Fig. 4b. We note that for the
negative gate regions, as expected from the previous graphs, the current rises with increasing
voltage. The converse is true for positive gate voltages. The quadratic region would require a
different amplifier design technique than the linear region. As well the transition region requires
more study before amplifiers operating in this region can be well designed, though as mentioned
previously, this region is suitable for frequency doubling.
We made additional observations. In all IV curves we noticed substantial noise on the output.
This is particularly at large bias voltages and high currents. Given the material system we use, it
is possible that the electrons are being transferred to an upper valley, resulting in instabilities. In
traditional HEMT transistors this does not occur due to the influence of the gate barrier potential.
In the BDT with low voltages on the gate, the structure does not have any barrier present.
In all the figures, only the left drain response is shown, but it is important to consider that this
device has a mirrored response on the right drain terminal. Thus, it is possible to design
differential circuits by using only one transistor. This can provide a significant benefit for
communication circuit design, as well as potentially enable higher signaling rates by utilizing
differential signaling throughout the circuit design.
Fig. 4. a(left) IV Current responds as a function of drain voltage for multiple NEGATIVE push pull gate
voltages (shown in reference to the left gate). Note that for negative gate voltages the current increases as
gate voltage increases; b(right) IV Current responds as a function of drain voltage for multiple POSITIVE
push pull gate voltages (shown in reference to the left gate). Note that for positive gate voltages the current
decreases as gate voltage increases.
In Fig. 5 we plotted the transconductance as a function of gate voltage for a 2V bias. Drain bias
affects transconductance performance and this suggests that higher electric fields will produce
devices with higher performance. Device scaling will enable designs that have higher electric
fields as well as it will ensure that a larger percentage of the electrons are being transported
ballistically through the device rather than by drift.
NSF Nanoscale Science and Engineering Grantees Conference, Dec 3-6, 2007
Grant # : 0609140
Fig. 5. Transconductance of the BDT shown in Fig. 1
as a function of push-pull gate voltage with applied 2V
drain bias.
Fig. 6. Change in transconductance as a function of
applied drain bias and a linear fit.
Experimental measurements have indicated that the transconductance of the device increases
with applied drain-source voltage. DC measurements of prototype devices have verified small
signal voltage gains of over 150, with transconductance values from 45 to 130 mS/mm
depending upon geometry and bias. Gate-channel separation is currently 80nm, and allows for
higher transconductance through scaling.
References
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