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Theses and Dissertations
2007
A programmable pulse generator for in-vitro
neurophysiologic experiments
Frank Licari
The University of Toledo
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A Thesis
Entitled
A Programmable Pulse Generator for In-Vitro
Neurophysiologic Experiments
By
Frank Licari
Submitted as partial fulfillment of the requirements for
The Master of Science in Bioengineering
______________________________
Advisor: Dr. Scott Molitor
________________________
College of Graduate Studies
The University of Toledo
May 2007
The University of Toledo
College of Engineering
I HEREBY RECOMMEND THAT THE THESIS PREPARED UNDER MY
SUPERVISION BY
ENTITLED
Frank Licari
A Programmable pulse generator for in vitro neurophysiologic experiments
BE ACCEPTED IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR
THE DEGREE OF
Master of Science in Bioengineering
Thesis Advisor: Dr. Scott Molitor
Recommendation concurred by
Committee
Dr. Brent Cameron
On
Dr. Patricia Relue
Final Examination
Dean, College of Engineering
ii
An Abstract of
A Programmable Pulse Generator
Generator for In Vitro Neurophysiologic
Experiments
Frank Licari
Submitted in partial fulfillment of the requirements for
The Master of Science in Bioengineering
The University of Toledo
May 2007
The field of neuroscience has grown tremendously in the last twenty years
due to advancements in instrumentation. It is now possible to electrically stimulate
individual or groups of neurons, and record the results with electrodes and optical
imaging techniques. Current methods to control instrumentation using waveform
generation encounter many difficulties including cost, complexity, lack of
customization, and multiple components to generate complex waveforms. Therefore,
it would be advantageous to design a multichannel waveform generation device that
can provide analog or digital signals with customizable on times, off times, delays,
amplitudes, and number of cycles.
A functional Direct Digital Synthesis (DDS) system was developed using a C
programmed microcontroller. To begin, parameters were entered in Matlab, and
microcontroller timers generated a TTL pulse using an internal oscillator to control
iii
the parameters of the waveform. An analog switch selected whether the signal
entered a circuit to output a sine or square wave. If a sinusoid was selected the
waveform was developed using a frequency divider and eighth order Bessel filter.
The original digital or newly formed sine waves were amplitude adjusted using
operational and programmable gain amplifiers. The signal was directed to the proper
output channel by a set of eight analog switches addressed by a demultiplexer.
This accuracy of the digital waveforms was compared with a function
generator using an equal duty cycle with a range of times between 0.1ms and 1s,
and the waveforms were found to be identical in timing characteristics and
amplitude. The ability to generate irregular digital pulses was also tested, and the
resolution was excellent over the same timing range. A sinusoid was generated
using the Bessel filter and the signal was found to be clean and accurate in
amplitude and frequency. The additional requirements of variable initial delay, finite
number of pulses, and the ability to output from one of eight channels were also met.
Future design improvements may include using a DDS IC for higher timing
resolution and a programmable digital to analog converter for more accurate sine
wave generation.
iv
Acknowledgements
I would like to thank Dr. Scott Molitor for his guidance and understanding throughout
my graduate career and the unique course that it took. I would also like to thank him
for the opportunity to work on this project. The lessons I learned in electronics,
programming, troubleshooting and common sense will be used throughout the rest
of my career. Thank you to Dr. Brent Cameron and Dr. Patricia Relue for serving on
my committee and for providing help and advice over the past three years of my
graduate and four years of my undergraduate studies. I would also like to thank the
other professors in the department past and present that I have had the opportunity
to learn from and who have provided me with the desire to undertake this path. I also
give a large amount of thanks to Dr. James Kaltenbach from Wayne State
University, who I have had the privilege of working with over the last eight months. I
appreciate the understanding that you have shown in allowing me to complete this
project and for furthering my excitement in neuroscience. I would like to thank my
friends and family for their continued support throughout the years. Finally, I would
like to give the warmest thanks to my wife Amy for allowing me to pursue my dream
unconditionally and for being my biggest supporter.
v
Table of Contents
1
Background……....................................................................................1
1.1 Motivation………………………………………………………………………..4
1.2 Overview of Direct Digital Synthesis………………………..………………5
1.3) Overview of Neurophysiologic Pulse Generator……………………………8
2
Development of the Neurophysiological Pulse Generator…………………...11
2.1) Data Acquisition System with AD5930 DDS Integrated Circuit………………….11
2.1.1) Motivation…………………………………………………………12
2.1.2) System Overview…………………………………………………13
2.1.2.1) NIDAQ Programming Overview………………………..15
2.1.2.2) AD5930 DDS/Frequency Burst Integrated Circuit……18
2.1.3) Design and Testing………………………………………………...32
2.1.3.1) Circuit Board Design…………………………………….33
2.1.3.2) Interface with Data Acquisition Unit……………………35
2.1.3.3) NIDAQmx Program………………………………………36
2.1.3.4) Testing Methods………………………………………….42
2.1.3.5) Future Applicability………………………………………45
2.1.3.6) Design Replacement…………………………………….46
2.2) AD5930 with Microcontroller Control……………………………………….46
2.2.1) Microcontroller Overview………………………………………….46
2.2.1.1) SPI Interface…………………………………………..…47
2.2.1.2) I/O Ports Used for SPI Transfer and Delays…………50
2.2.1.3) Programming the Microcontroller……………………51
2.2.2) Design and Testing………………………………………………..53
2.2.2.1) Circuit Board Overview…………………………………54
2.2.2.2) Interface with Microcontroller and Other Circuits........55
2.2.2.3) Programming Overview…………………………………56
2.2.2.4) Testing Methods………………………………………….59
2.2.2.5) Future Applicability………………………………………62
2.2.2.6) Design Replacement……………………………………63
vi
2.3) Microcontroller DDS System………………………………………………..63
2.3.1) Motivation…………………………………………………………..63
2.3.2) Design Overview…………………………………………………64
2.3.2.1) Waveform Generation…………………………………65
2.3.2.2) Wavetype Selection……………………………………68
2.3.2.3) Amplitude Selection……………………………………70
2.3.2.4) Channel Selection………………………………………72
2.3.2.5) Power Supply……………………………………………74
2.3.2.6) USART Interface………………………………………..76
3) Materials and Methods………………………………………………………………..
Methods………………………………………………………………..77
………………………………………………………………..77
3.1) Microcontroller Overview…………………………………………………...77
3.1.1) PORTB and PORTD………………………………………………78
3.1.2) PORT Registers……………………………………………………79
3.2) Waveform Generation Circuit……………………………………………….80
3.2.1) Timer/Counter Overview…………………………………………..80
3.2.2) Timer/Counter Registers…………………………………………..81
3.2.3) Initial Waveform Generation………………………………………85
3.2.4) Waveform Generation Program…………………………………..87
3.3) Wavetype Selection Circuit………………………………………………….92
3.3.1) DG425 Analog Switch.............................................................93
3.3.2) SN74HC390 Frequency Divider…………………………………94
3.3.3) MAX292 Bessel Filter………………………………………….97
3.4) Amplitude Control Circuit………………………………………………….99
3.4.1) MAX532 Programmable Gain Amplifier……………………….100
3.4.2) Output Correction………………………………………………..105
3.5) Channel Selection Circuit…………………………………………………106
3.5.1) SN74HC138N Demultiplexer…………………………………..107
3.5.2) Analog Switch Outputs…………………………………………..109
3.6) Power Supply Circuit……………………………………………………..111
3.6.1) -5V Supply………………………………………………………112
vii
3.6.2) +5V Supply……………………………………………………….112
3.6.3) +/-15V Supplies…………………………………………………..114
3.7) Circuit Board Design and Layout…………………………………………116
3.7.1) Power Supply Board……………………………………………..116
3.7.2) Main Signal Board……………………………………………….118
3.7.3) Wiring Considerations…………………………………………..121
3.7.4) Connector Considerations…………………………………....122
3.8) Matlab Interface Design…………………………………………………..122
3.8.1) Program Description………………………………………….123
3.9) PC Control of the Microcontroller…………………………………………126
3.9.1) USART Registers……………………………………………..126
3.9.2) Communication with Matlab…………………………………….132
3.9.3) Communication with Microcontroller………………………….135
4) Results and Discussion………………………………………………………………
Discussion………………………………………………………………136
………………………………………………………………136
4.1) Register and GUI Values…………………………………………………..136
4.2) Square Wave Generation………………………………………………….138
4.3) Sine Wave Generation……………………………………………………142
4.4) Square Wave with Variable Interpulse Intervals………………………..143
5) Future Work……………………………………………………………………………
Work……………………………………………………………………………148
……………………………………………………………………………148
6) References…………………………………………………………………………….
References…………………………………………………………………………….152
…………………………………………………………………………….152
7) Appendix……………………………………………………………………………….
Appendix……………………………………………………………………………….155
……………………………………………………………………………….155
1) Hardware Timing Values……………………………………………………..155
viii
List of Figures
Figure 1: Overview of DDS System………………………………………………………5
Figure 2: A Graphical Representation of the Delta Phase Register and Phase
Accumulator…………………………………………………………………………………6
Figure 3: Overview of the Neurophysiologic Pulse Generator………………………10
Figure 4: BNC-2090A Rack Mount Connector Block…………………………………13
Figure 5: An Overview of AD5930 Programming………………………………………20
Figure 6: AD5930 Functional Block Diagram…………………………………………28
Figure 7: Data Acquisition Unit Design Interconnection ………………………………32
Figure 8: AD5930 External Circuitry……………………………………………………33
Figure 9: Overview of NIDAQmx Program……………………………………………38
Figure 10: Integer to Binary Converter…………………………………………………39
Figure 11: Overview of the Atmega169 SPI Interface…………………………………48
Figure 12: Overview of Microcontroller/AD5930 Design………………………………54
Figure 13: SPI Data Transfer GCC Code……………………………………………….57
Figure 14: Example of CTRL Pin Activation…………………………………………….58
Figure 15: Example Scope Data from VMLAB…………………………………………60
Figure 16: Overview of Atmega169 Timer/Counter Circuits…………………………..66
Figure 17: DG425 Internal Circuit………………………………………………………69
Figure 18: Internal MDAC of the MAX532 Programmable Gain Amplifier…………71
Figure 19: 3-8 Decoder/Demultiplexer Circuit of SN74HC138N……………………73
Figure 20: MAX860-864 Charge Pump Circuit……………………………………….75
Figure 21: An Overview of the AVR Butterfly…………………………………………78
Figure 22: Overview of Matlab Section of Timing Generation………………………88
Figure 23: Overview of C Section of Timing Generation…………………………….90
Figure 24: Overview of Wavetype Selection Circuit…………………………………92
Figure 25: Pin Out of DG425 Analog Switch……………………………………………93
Figure 26: Pin Out of SN74HC390 Frequency Divider………………………………...95
Figure 27: The Divide by 100 Counter………………………………………………….97
Figure 28: Op-Amp Circuit to Generate Maximum Input………………………………99
ix
Figure 29: Overview of MAX532 Programmable Gain Amplifier……………………101
Figure 30: Overview of PGA Register Creation ………………………………………103
Figure 31: Output Correction Circuit……………………………………………………106
Figure 32: SN74HC138 Demultiplexer…………………………………………………107
Figure 33: SN74LS04 Hex Inverter…………………………………………………….108
Figure 34: Demultiplexer/Inverter Connections………………………………………109
Figure 35: Analog Switch and Output Connections…………………………………110
Figure 36: Conditional Setup for Channel Selection…………………………………111
Figure 37: +5V Power Supply Circuit…………………………………………………..112
Figure 38: MAX864 as a Voltage Tripler………………………………………………114
Figure 39: Layout of Power Supply Board……………………………………………117
Figure 40: Schematic of Power Supply Board………………………………………..117
Figure 41: Photograph of Power Supply Board………………………………………118
Figure 42: Breadboard Overview………………………………………………………119
Figure 43: Schematic of Main Signal Board…………………………………………..120
Figure 44: Photograph of Assembled Breadboard……………………………………121
Figure 45: Overview of GUI Interface…………………………………………………124
Figure 46: Serial Transfer Code………………………………………………………..125
Figure 47: Steps for GCC Serial Transfer…………………………………………….134
Figure 48: Square Wave with 10 ms On and Off Times and Amplitude +9V………138
Figure 49: Square Wave with On and Off Times of 10ms, 15 pulses, and Initial Delay
of 50 ms…………………………………………………………………………………...139
Figure 50: Square Wave with 10 ms On and Off Times and Amplitude -2V………140
Figure 51: Square Wave with 10 ms On and Off Times and Amplitude
+0.5V………………………………………………………………………………………140
Figure 52: Square Wave with 0.1 ms On and Off Times……………………………141
Figure 53: Square Wave with 1 Second On and Off Times…………………………141
Figure 54: Sine Wave with Frequency 0.1 kHz and Amplitude 5V…………………143
Figure 55: Square Wave with On Time of 2 ms and Off Time of 1 ms…………….144
Figure 56: Square Wave with On Time of 20 ms and Off Time of 1 ms…………...145
x
Figure 57: Square Wave with On Time of 200 ms and Off Time of 1 ms………….145
Figure 58: Square Wave with On Time of 1ms and Off Time of 20ms…………….146
xi
List of Tables
Table 1: Summary of Built In Functions for Typical NIDAQmx………………………16
Table 2: Summary of NIDAQmx Digital Output Functions……………………………16
Table 3: Summary of NIDAQmx Counter and Timer Functions………………………17
Table 4: AD5930 Register Identifiers……………………………………………………21
Table 5: Summary of Control Register Bits……………………………………………22
Table 6: MCLK Dividers for Incremental Interval Register……………………………26
Table 7: AD5930 Register Values for Experiment……………………………………43
Table 8: SPI Pins and Functions……………………………………………………….47
Table 9: SPCR Register Bits……………………………………………………………49
Table 10: Functions in GCC Program…………………………………………………56
Table 11: SPCR Register Settings for AD5930 Programming………………………57
Table 12: Demultiplexer Outputs for all Addresses…………………………………….74
Table 13: Overview of TCCR0A Bits…………………………………………………….83
Table 14: Bit Values Setting Modes of Operation……………………………………...83
Table 15: Control of Compare Output PB4……………………………………………..84
Table 16: Clock Prescale Settings……………………………………………………….84
Table 17: Comparison of Register and Register Bits for Sine and Square Wave
Circuits………………………………………………………………………………………86
Table 18: Output Values for Each Count Value………………………………………..96
Table 19: Overview of USART Control Bits…………………………………………...127
Table 20: Character Length as Set by UCSZ Bits……………………………………130
Table 21: Register Values for HyperTerminal Transmission………………133
xii
1) Background
The field of neuroscience has grown tremendously in the last twenty years
due to advancements in instrumentation. It is now possible to electrically stimulate
individual neurons or groups of neurons and record the results using stimulus and
recording electrodes, respectively. (3, 5-6) Another research technique uses
pressure pipettes or iontophoresis to inject neurons with drugs in order to test the
effect of a chemical change on the neuron. (4) Optical imaging can be used in-vitro
with fluorescence imaging or in-vivo with a voltage sensitive dye to monitor the
changes that take place by electrical or chemical stimulation. (1-2, 5) These several
examples show that the need for instrumentation control is paramount in this field of
research, and all have one aspect in common, the need for waveform generation
control. Three applications will now be discussed in more detail to show how current
technology is used, an extracellular stimulator, sound application to a speaker in
auditory research, and camera synchronization in optical imaging.
When a neuron is optically imaged it is critical that the time that the image is
acquired be synchronized with the stimulus being applied. This is important to be
able to see the response to the stimulus during the imaging time and, because most
imaging experiments requiring averaging, to be repetitively the same between each
1
run. (5) Some of the important parameters to be considered include: the time after
the shutter opens before the acquisition begins, the initial delay between this time
and stimulus application, the amount of time the stimulus is on and off, and the delay
between sequential acquisitions. (1-2, 5-7) One instrumentation system that can be
used to control these parameters is the Warner Instruments Neurolog System.
The Neurolog System from Warner Instruments is a modular system that
uses different components with a common chassis that supplies the power supply
and grounding. This system allows the user to incorporate digital and analog pulse
generators along with amplifiers and signal conditioning units, to stimulate and
record from neurons. (10) The applicable components for this application are the
NL405 Pulse/Width Delay Unit and the NL304 period generator. The NL405
produces pulses of adjustable duration and delays between 1 µs and 1 s that can
either be applied once, or applied repetitively. The NL304 also produces pulses and
delays, but at time lengths up to 60 seconds. (8) A typical manner of usage would be
to use one NL405 to generate the shutter delay and trigger another to generate the
initial delay. (9) The acquisition onset time and interstimulus delay could be
controlled using either the NL405 or NL304 depending on the length of time of the
acquisition. If time is in milliseconds the NL405 is appropriate, but when this
timeframe is in seconds the NL304 is appropriate. It can be seen immediately that
many timers are needed for one channel of stimulus. If multiple imaging sessions
were occurring then multiple systems would be needed.
An application using an analog signal is to apply sound to a speaker for
stimulating the cochlea and central auditory pathways. (2) A typical speaker requires
a 0 to 100mV sinusoid with varying frequencies of Hz to tens of kHz. (2) One system
that is used for this application is the modular system from Coulbourn Instruments.
(2) This system uses four timers (S52-53) to present the initial delay, length, the rise
time, and the fall time of the stimulus. The input voltage and burst frequency is
applied to the timers with a programmable function generator. A standard for this
voltage is 0-1 V, and the amplitude is decreased by a programmable attenuator
(S85-06) which lowers the voltage to 10 mV before a constant gain amplifier adjusts
the amplitude to the required level. This system can be triggered on a single pulse,
or can be constantly retriggered to provide a constant stimulus. Again, because this
is a modular system, multiple channels require a large number of units, presenting a
very high cost.
The final application to be discussed is the use of an extracellular stimulator.
This device can use an analog source for current or a digital source for voltage
stimulation. There are unique circumstances for this source such as low voltages
(mV), a discrete or continuous number of pulses, and the need to provide initial and
interpulse delays of varying lengths. One system that is used for this type of
3
stimulation is the RX7 microstimulation base station from Tucker Davis, and its
corresponding hardware. (11) The RX7 is software controlled and can program the
various pulse lengths and number of pulses. However, several other pieces of
hardware are needed, including the MS16 current isolator, the RA16PA preamplifier
to digitize signals, and the SH16 headstage and electrodes. (11) This system is able
to utilize up to 16 channels, but only with the same stimulus information on each.
1.1
1.1) Motivation
As previously shown, generation of waveforms for neurophysiologic
experiments is possible, but has many drawbacks. Some of these problems include
cost, difficulty in using, lack of customization, and the requirement to buy several
parts for one application. Therefore, it is of great interest to develop a pulse
generation device that can provide analog or digital waveforms with customizable on
and off times, amplitudes, and number of cycles. In addition, it would be highly
advantageous to be able to have a multi-channel device that would allow the user
not to have to use multiple pieces of stimulation equipment. Because of the sensitive
nature of this research, accuracy is of the utmost importance. One of the most
popular and accurate methods of waveform generation utilizes a method known as
Direct Digital Synthesis, which is now described in detail.
4
1.2)
.2) Overview of Direct Digital Synthesis
A direct digital synthesis system is able to generate a user selectable
frequency with only a single master clock source. There are several parts to a DDS
system including the clock source, serial load register, parallel data phase register,
phase accumulator, phase register, sine look up table, digital to analog converter,
and low pass filter. (12-13) A block diagram of the parts of a DDS and how they
interact is shown in the Figure 1 below:
Figure 1: An Overview of A DDS System (12
(12)
12)
The input to the DDS system is a stable clock source, usually a crystal
oscillator or clock from a microcontroller. The user specifies the value of the
5
frequency, and this value is loaded into the serial load register. This value is then
transferred to the delta phase register, and remains constant until the frequency
information is updated. The phase accumulator is updated once each clock cycle
and is added to the number in the delta phase register. This process repeats until
the final value of the phase accumulator is reached. For example, if the DDS has 32
bit resolution, this high value is two to the thirty-second power or 1111…….1111.
The larger the value in the delta phase register, the faster it will step through the
accumulator, providing a faster frequency. This is graphically shown as steeping
through a wheel as shown in Figure 2 below:
Figure 2: A Graphical
Graphical Representation of the Delta Phase Register and Phase
Accumulator (12
(12)
12)
The output of the phase accumulator becomes the address to the sine lookup
table. Each address in the lookup table is a phase point on the sine wave, which
6
corresponds to the amplitude information of one cycle of a sine wave. This digital
amplitude word becomes the input to the DAC which is converted to a sinusoid. The
output wave is then passed through a low pass filter to eliminate any noise from the
clock source. The frequency of the output sine wave becomes (12):
There are many advantages to using a digital direct synthesis system to
generate pulses. The first, and most important, is the excellent accuracy of this type
of device. The step value of a 24 bit DDS system is one divided by four times ten to
the ninth power, which is more than most applications require. (12) The second
advantage of DDS is the ability to update the registers nearly instantaneously with
no phase discontinuities. Most DDS systems are found in a single integrated circuit
eliminating the need for multiple parts normally needed in other pulse generation
circuits. The DDS usually requires a small amount of external hardware, often only
decoupling capacitors and a low pass filter at the output.
Several disadvantages to a DDS system exist based on the fact that it uses
sampling to generate an output. This leads to issues with quantization noise, aliasing
and filtering which becomes more problematic when slow frequencies are used. One
of the most common problems with DDS is that higher order harmonics are often
visible at the output, requiring multiple filters to recover the wanted signal. Another
problem that exists is that the output frequency is a function of the input frequency.
7
This limits the range of the device to high speed applications. For example, if the
user requires a range of 1 Hz to 10 kHz and a 10 MHz clock source is used, the 1Hz
signal would be impossible to generate. The design of the pulse generator in this
project attempts to utilize the advantages of the DDS system and to overcome the
shortcomings.
1.3)
1.3) Overview of the Neurophysiologic Pulse Generator
In order to achieve the goals of this project a multichannel pulse generation
device was designed capable of producing both analog and digital waveforms. The
user is able to control the amplitude, pulse on and off time, number of pulses, and
initial onset before pulses begin. This device is modified DDS simulator that uses the
basic principles of a master clock, phase register, lookup table and digital to analog
converter.
There were three different types of design that were explored. The first
design attempt used a data acquisition system to communicate with an AD5930
DDS integrated circuit for waveform generation, a MAX532 programmable gain
amplifier (PGA) for amplitude control, and a demultiplexer for channel control. The
data acquisition system proved unsuccessful at communicating with the IC, and was
replaced with a microcontroller, the AVR Butterfly. This methodology failed due to
8
difficulties with noise control in the AD5930, leading to the final design using the
microcontroller itself to produce the pulses.
In the final design, the parameters for the waveform generator are entered by
the user in a graphical user interface in Matlab. The important parameters included
the wavetype (sine or square), the output channel (1-8), the amplitude (-10 to 10 V),
the pulse on time (0.1 ms to 1s), the pulse off time (0.1ms to 1s), and the number of
pulses. This information was then translated into values that can be utilized by a
specialized C program that programs the microcontroller. The output pulse was sent
from the microcontroller to an analog switch, controlled whether the pulse entered
the digital or sinusoid generator circuit. If the pulse entered the digital circuit its
amplitude was adjusted using op-amps and a programmable gain amplifier. The
output channel was selected by using another set of analog switches addressed by
a demultiplexer.
If a sinusoid was selected, the pulse value was increased 100 times the
original value in the Matlab program. The waveform was then sent to the wavetype
analog switch and the sinusoidal circuit is selected. A 1/100 frequency divider was
used to retrieve the original requested frequency. The two waveforms were then
sent to an eighth order Bessel filter to produce the sine wave, which required two
waveforms at a 100:1 ratio in order to produce a true sinusoid. The amplitude and
9
channel selection circuits modified the waveform and sent it to the proper output as
in the digital circuit. An overview of the final design is shown in the figure 3 below:
Micro
controller
Sinusoid
Wavetype
Selection
Frequency
Divider
Square
Filter for
Sine Wave
Amplitude
Selection
Figure 3: Overview of the Neurophysiologic Pulse Generator
10
Channel
Selection
2) Development of the Neurophysiological Pulse Generator
2.1) Data Acquisition
Acquisition System with AD5930 DDS Integrated Circuit
There were three designs used in the development of the neurophysiologic
pulse generator. The first design attempted to use the PCI-6259 data acquisition
board from National Instruments to generate the pulses needed to control an
AD5930 DDS frequency sweep generator integrated circuit. This IC required a 3 wire
SPI interface to obtain information for its control and frequency registers, as well as
a control pulse to output the final pulse. In addition to the IC, multiple digital lines
were needed to control additional circuits for amplitude and channel selection.
The PCI-6259 data acquisition board uses a DAQ-STC timing controller to
generate appropriate control signals that can be made available to the hardware
because a common PCI bus is utilized. (15) The available hardware on this device
includes an analog input and output, digital input and output, counters and timers,
and programmable function inputs. In order to control the actions of this device there
are three different levels of programming available using National Instruments
software. There are two top level programming options, Labview and Measurement
Studio. These two programs can be used together or separately, allowing the user to
easily control the actions of individual hardware lines and ports or to design
11
simultaneous or sequential events. (15) The next lower level, NIDAQmx, uses Visual
Basic or Visual C functions and libraries to control the hardware in a manner similar
to Labview. In addition, NIDAQmx allows further control of timing and internal and
external interrupts. (15) The lowest level of programming utilizes C to directly control
the registers of the data acquisition board, allowing fundamental processes to be
controlled. (14) However, it is difficult to use this type of programming to control high
level processes and this method is not used in general application programming.
For the purposes of this design, NIDAQmx programming was chosen, so that it
could be easily combined with other programming currently being used with this data
acquisition board.
2.1.1) Motivation
The data acquisition system from National Instruments had many possible
advantages for the design of a multichannel stimulator. First, the large number of
digital output port lines gave the possibility of controlling many channels
simultaneously or sequentially. Second, event triggering of the device is easily done
so that control of the starting and stopping of multiple ports could be done either
internally or externally. The high speed timers (10 MHz) were compatible with the
DDS integrated circuit, which required up to a 50MHz crystal for its master clock
circuit. (15) Because NI-DAQ uses C, many libraries and files already existed,
12
making programming of the device relatively easy. Finally, because the data
acquisition system was already installed the cost of the design was less than for an
entirely new prototype.
2.1.2) System Overview
The PCI-6259 data acquisition board can be configured for analog input or
output, digital input or output, or counter and timer functions. In addition, there are
ten programmable inputs and seven RTSI trigger lines that can be used to receive
external sources for timing signals and for timing control. The user also has access
to a 5V digital supply and the internal analog and digital ground planes. The external
connections from the data acquisition board were made available to a rack mount
connector block, the BNC-2090A. This unit allowed access to the analog, digital, and
timer circuits using BNC or springfit connections. The rack is shown in Figure 4
below:
Figure 4: BNC-2090A Rack Mount Connector Block (16)
13
For the purposes of this project, the digital output, timer and counter lines, and the
programmable inputs were used and will now be discussed in detail.
There are eight digital lines accessible using the PCI-6259 (DIO0-7) that
can be utilized either individually or together as a port. Each of these lines are
capable of receiving a TTL input or output. For this device any value over 2.5V is
considered high and anything below this value is considered low. When the digital
input or output is used as a single line, the data is sent or received in a serial
method. The timing is provided by the 10 MHz or 100 kHz internal clock sources or
an externally applied clock less than 10 MHz. When the lines are utilized as a port,
the information is sent simultaneously to all selected lines in the port. This allows for
parallel data transfer and can be used when rapid transmission is needed.
There are two general purpose timer/counters accessible from the data
acquisition system. There are several different timer/counter applications including:
simple counting and timing, event counting, period and pulse width measurement,
and square wave generation. In addition to the two timer/counters the PCI-6259 also
provides a constant 10 MHz frequency output that can be used as a clock source.
Each of the counters has three general parts, the source, the gate, and the
output. (manual) The source is used to provide the timebase for the timer/counter.
There are many possible options for the source of the counter including the 10 MHz,
14
or 100 kHz internal clocks, or an external timebase 10 MHz or less. The gate of the
counter initiates the starting and stopping and can be generated from either an
internal or external location. Internal triggers can be sent from an event that occurs
during a digital or analog input, a digital or analog output, the other counter or
frequency output, RTSI line, or from an internal clock source. A trigger can occur
when a rising edge, falling edge, high level, or low level is sampled by the trigger line
of the counter. The final part of the counter is the output, which when not sending a
pulse, can idle at either a high or low state as specified by the user.
2.1.2.1)) NIDAQ Programming Overview
2.1.2.1
Each data acquisition or transmission event in NIDAQmx is identified by a
TaskHandle which is assigned a numerical value, typically beginning at 0. (17) Every
event performed in NIDAQmx follows the same general procedure. First the event is
created and assigned a TaskHandle value. Next, the acquisition system is prepared
for the event, and the event is transmitted. During this time the transmission is
constantly verified for proper execution. The last step ends the task and clears any
used values. A listing of the internal functions used at various points of the
transmission can be found in Table 1 below:
15
Function Name
DAQmxCreateTask
DAQmxStartTask
DAQmxWaitUntilDone
DAQmxStopTask
DAQmxClearTask
Function
Sets a TaskHandle to an event
Begins a data acquistion or
transmission
Puts delay in data transmission to verify
that all data has been passed
Stops a data acquistion or transmission
Clears the TaskHandle
Table 1: Summary of Built In Functions for Typical NIDAQmx Event
Every NIDAQmx internal function is preceded by the command DAQmxErrChk,
which checks the function for errors while it is being run. (17) If an error is found it
stops the transmission and enters a subroutine at the end of the program. This
subroutine stops the program, and displays the error that was found.
A Digital Input or Output event utilizes two or three built in functions to create
the channel, read or write the data, and if necessary, attach the timing of the data
transfer to a timing source. The three major functions for transmission of data from
a digital output line are shown in Table 2 below:
Function Name
DAQmxCreateDOChan
DAQmxWriteDigitalLines
DAQmxCfgSampClkTiming
Function
Creates a channel and specifies input or output
Writes the data when channel is output
Configures timebase and number of points for
data transfer
Table 2: Summary of NIDAQmx Digital Output Functions
16
The program for the neurophysiologic pulse generator utilizes eight digital output
lines, four use the timed configuration for controlling the AD5930 and PGA, and four
are static throughout the data transfer for addressing the demultiplexer and the
channel selection.
There are three counter/timer functions to output the pulse requested by the
user. Each of the functions specify the channel (ctr0, or ctr1), the timebase (10 MHz,
100kHz, or external), the initial value of the counter (high or low), the on time, the off
time, and the initial delay. The timer can either output a number of pulse ticks, a
frequency, or a specific time. The on time, off time, and delay have units in relation
to the type of output specified by the user. The three functions are summarized in
Table 3 below:
Function Name
DAQmxCreateCOPulseChanTicks
DAQmxCreateCOPulseFrequency
DAQmxCreateCOPulseTime
Function
Outputs a pulse with high time and low time in
pulse ticks of counter source
Outputs a pulse with a high time and low time
given as a frequency
Outputs a pulse with a high time and low time
in seconds
Table 3: Summary of NIDAQmx Counter and Timer Functions
17
The pulse generator uses the number of pulse ticks function for the initial delay
before turning on the AD5930, and the pulse time function for delays in between
pulse generations.
2.1.2.2)) AD5930 DDS
DDS// Frequency Burst Integrated Circuit
2.1.2.2
The AD5930 integrated circuit is a DDS frequency sweep generation chip that
allows the user to output a sine, a triangle, or a square wave. (18) The output
generates multiple frequency bursts, with a start frequency, incremental interval and
number of increments specified by the user. In addition, the type of sweep, the
amount of cycles per burst, and the between burst intervals can be controlled. The
AD5930 has eight registers to control the parameters of the frequency sweeps
programmed using an SPI interface. The pulse output is initiated by the pulsing of
the CTRL pin, and the actions of this pin can also control the length of time that the
frequency burst is active, or the amount of time between bursts. The sine and
triangle wave outputs have a constant amplitude of 1.2 volts and the square wave
output is a standard TTL 0-5V output. (18)
The AD5930 works using the fundamentals of a DDS system. A master
reference clock is used to generate the entire range of two to the twenty fourth
power possible frequencies. The chip is able to do this by using a delta phase
register to index a PROM stored sine lookup table. This information is sent to a SIN
18
ROM, which converts the frequency information into amplitude information for the
digital to analog converter, and the DAC converts the signal to its final sinusoidal
form. (18) The SIN ROM can also be bypassed, truncating the digital signal and
giving a triangular output. When a digital output is needed, it is taken directly from
the DDS core, before being buffered and made available at the digital output pin.
(18) After the first pulse has been generated, the delta phase register is reloaded
with information for the next frequency burst, and continues until the last frequency
burst is output.
There are two output frequency profiles available from the AD5930, triangular
and saw sweep. In the triangular sweep, the output pulse begins at the lowest
frequency and increments to the highest frequency. The pulse then decrements
back to the lowest frequency. (18) In the saw sweep, the bursting begins at the
lowest frequency and continues to the highest, before starting over again at the
lowest frequency. (18) The frequency burst can be output in two different modes as
well, continuous or burst. In the continuous mode the output waveform is present
during the entire burst time. (18) In burst mode the waveform is on for a percentage
of time of the frequency burst, for the remainder of time, the output returns to the
midscale voltage. (18)
The programming of the AD5930 consists of writing values to each of the
eight registers controlling the various parameters of the frequency sweep. Each
19
register is 16 bits long, with the first four bits containing the register address and the
last 12 bits containing the data. (18) The information for each register is transferred
from the microcontroller using a 3 wire serial SPI interface. In this form of data
transfer the binary values are only considered when the FSYNC pin is taken low.
The process of data transfer is shown in Figure 5 as follows:
FSYNC
taken low
The information of one Register is transferred
from the data acquisition unit to
the AD5930
FSYNC
taken high
Single
data pulse
All registers
written?
NO
YES
Data Transmission
Complete
Figure 5: An Overview of AD5930 Programming
The data transfer proceeds for each of the eight registers, and then a start can be
initiated at the CTRL pin.
20
The first four programmed bits tell the integrated circuit which register to write
the next twelve bits of data into. The four bit codes for each of the registers are
shown in Table 4 below:
REGISTER
ADDRESS
D15
0
0
0
0
0
1
1
1
D14
0
0
0
0
1
0
1
1
D13
0
0
1
1
D12
0
1
0
1
0
0
0
1
Register Name
Control
Number of Increments
Frequency Increment- LSB
Frequency Increment- MSB
Increment Interval
Burst Interval
Start Frequency LSB
Start Frequency- MSB
Table 4: AD5930 Register Identifiers (18)
(18)
The eight registers include the control register, two start frequency registers,
two frequency increment registers, the incremental interval register, the number of
increments register, and the burst time register. (18) The twelve bit control register is
used to set up to control the various operating modes of the AD5930. A summary of
the function of each of the bits is shown in Table 5 below:
21
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
B24
DAC Enable
SINE/TRI
MSBOUTEN
CW/BURST
INT/EXT
BURST
INT/EXT INCR
MODE
SYNCSEL
SYNCOUTEN
Reserved
Reserved
Method of Loading Fstart and Fincr Registers
Enables DAC
Selects Sine or Triangle Output
Selects Digital Output
Type of Bursting
How Bursting is Controlled
How Frequency Increments are Triggered
Type of Frequency Sweep
Type of Output on SYNCOUT pin
Enables SYNCOUT pin
Reserved
Reserved
Table 5: Summary of Control Register Bits (18)
(18)
Bit 11 is used to control how the 24 bit start frequency and frequency
increment interval registers are programmed. If this bit is set to 1, a complete word is
loaded into the frequency register on two consecutive writes. The first write contains
the 12 LSB’s of the frequency word and the second write contains the 12 MSB’s. If
the bit is set to 0 these two 24 bit registers operate as two separate registers that
can be written too independently. This is used when only part of the register needs
to be changed.
Bit 10, the DAC enable pin, is used to conserve power in the AD5930 by
shutting down the digital to analog converter when the current output is not needed.
When this bit is set to 1 the DAC is enabled and a current output is possible. When
Bit 10 is written to 0 the DAC is disabled, and only a digital output is possible.
Bit 9 and bit 8 are used to determine the type of output that is seen at the
digital and current output pins. When the DAC is enabled, bit 9, the SINE/TRI bit,
22
selects the output that can be seen at the IOUT pin, either sinusoidal or triangular.
When this bit is set to 1, a sinusoidal output is available, and when it is set to 0 a
triangular output is seen. Bit 8 is used to enable the digital output pin, MSBOUT.
This is set to 1 to enable the output, or 0 to disable the output.
Bits 7 through 5 are set to control the burst profile and control of the output.
When bit 7, the CW/BURST pin is set to 1, the IC outputs each frequency
continuously for the length of time specified in the burst register. When set to 0 the
AD5930 outputs each frequency for the length of time in the burst register and
returns to midscale for a length of the time interval under internal or external control.
Bit 6 controls whether this pattern is controlled internally when set to 0, or externally
when set to 1. When the control is external the frequency increments when a pulse
is received at the control pin. When the control is internal the amount of time
between the end of one pulse and the beginning of the next is set in the incremental
interval register. Bit 5, INT/EXT INCR determines how the frequency increments are
controlled. If this value is set to 1 the increments are controlled externally through
the control pin. If this value has been set to 0 then control is internal and the
frequency is incremented at the end of each burst frequency.
Bit 4 is used to set the type of frequency sweep that the burst pattern will be.
When this value is set to 1 the output is patterned by the saw sweep, and if the value
is set to 0 this pattern becomes a triangle sweep. Bit 3 and Bit 2 work together to
23
determine if a signal is present at the SYNCOP pin 9, and if so what this value
represents. When Bit 2 is set to 1, the SYNC output can be seen, and the value of
Bit 3 determines what this value represents. When Bit 3 is set to 1 the SYNCOP pin
is high at the end of each frequency sweep and returns to zero at the start of each
subsequent sweep. With this setting the pin can be used to monitor the number of
bursts transmitted. If the bit is set to 0 then the SYNCOP pin outputs a pulse of 4
times the clock value at each frequency output, which is typically used to control
other circuits. The final two bits 1, and 0, are reserved for the AD5930 and must
always be set to a value of 1. If they are set to 0 the IC will not be functional.
There are two start frequency registers in order to provide for the 24 bit
resolution of the device. One register holds the values for the 12 MSB’s and the
other holds the values of the 12 LSB’s. The user can either change the values of one
of these registers at a time or both at the same time depending on the setting of Bit
11 in the control register. The frequency value is found by dividing the 10 MHz
reference clock by a value between zero and two to the twenty-fourth power. This
gives an excellent signal resolution of approximately 0.59 Hz per position with a 10
MHz clock.
The frequency increment registers include one 11 bit register for the 11
MSB’s and one 12 bit register for the 12 LSB’s. The final value of the MSB register
programs the frequency sweep to increase or decrease by the value in the other 23
24
bits. The first frequency burst of the sequence is given by the start frequency
register. The next frequency burst has a value of the start frequency added to the
frequency increment. The third frequency output becomes the start frequency added
to twice the increment. This continues until the final sweep frequency is reached.
This is summarized in the equation below (18):
FOUT =FSTART + NINCR × Δf
The increment frequency is translated into a binary word using the same
method as with the start frequency. The 10 MHz clock is used as a baseline and
there are two to the twenty-third power different positions. The highest increment
value is in the two to the twenty-third power position, 5 MHz, and the lowest value is
in position 0, 0.6 Hz.
The number of increments register is 12 bits in length and contains the
information regarding the number of frequency bursts that should occur. The number
of increments is programmed in a binary fashion. The minimum number of
increments allowed is 2 while the maximum number is 4095.
The incremental interval register contents allow the user to program the
output length for each frequency burst. The time between bursts is either a fixed
number of output cycles or a number of the master clock periods. Bits 12 and 11 of
25
the register are used as dividers for the time base when master clock periods are
used. The settings are summarized in Table 6 below:
D12 D11 Multiplier Value
0
0
Multiply (1/MCLK) by 1
0
1
Multiply (1/MCLK) by 5
1
0
Multiply (1/MCLK) by 100
1
1
Multiply (1/MCLK) by 500
Table 6: MCLK Dividers for Incremental Interval Register (18
(18)
18)
When the number of cycles is used, each time interval is 100ns (for a 10 MHz clock)
multiplied by the binary register word. The minimum amount of pulses is 1 and the
maximum number is 2047. When the number of MCLK periods is used the original
clock value is divided by the amount requested in the register. The binary word in
the register is then multiplied by this value to give the overall incremental interval. In
the case of this project this register is always set to give a fixed number of clock
cycles.
The final programmable register, the burst register, controls the period of time
that a signal is on during the entire frequency burst interval, set in the incremental
interval register. As with the incremental interval, the burst time can be programmed
in number of cycles or number of clock periods. Bits 12 and 11 have the same
functionality as in the interval register, and the timebase and clock cycle amounts
26
are identical. In the case of this project this register is always set to give a fixed
number of clock cycles.
After the registers have been programmed, a low to high transition at the
CTRL pin begins the frequency sweep. During the most basic operation of this
device, the first value is loaded from the start frequency register and each
successive burst increases or decreases in frequency as specified in the frequency
interval register. This continues for the amount of pulse bursts specified in the
number of increments section. The length of time the pulse is on is controlled by the
burst time register, and the overall length of the burst controlled by the incremental
interval register. (18) However, there are two other methods to activate and control
the frequency sweeps that can be set by the user with bits 5, 6, and 7 in the control
register.
The first type, known as external increment-auto burst uses the CTRL pin to
step through each of the frequency increments. (18) With the first low to high
transition, the first frequency is output. The time of the frequency burst is controlled
by the burst register which returns to midscale until the next low to high transition on
the CTRL pin. This method is often used when there are different delays required
between each frequency burst.
The final type of control is known as external increment-external burst. In this
method both the incremental interval and the burst interval are controlled using the
27
control pin. (18) When the CTRL pin is taken from low to high the frequency sweep
begins. The CTRL pin remains high, and the output remains on for the entire
duration of the sweep. When the CTRL pin returns to a low value the output returns
to midscale for the length of time needed between bursts. When the next transition
occurs the next frequency increment is loaded and the burst continues until the next
high to low transition, and repeats until the last frequency sweep have ended.
The AD5930 IC can be grouped into six important sections: reference, SPI
programming, on-off and burst control, timing, output, and power and ground. A
functional overview of the device is shown in Figure 6 below:
Figure 6:
6: AD5930 Functional Block Diagram (18
(18)
18)
The reference section consists of the full scale adjust controller, or
FSADUST, which determines the magnitude of the full scale current at the output.
This pin has an external resistor applied to analog ground to provide a constant
28
reference voltage (Vrefout) of 1.2 volts. The current magnitude can then found by the
equation (18):
Iout=18*(Vrefout/Rset)
Rset is the external resistor, and its value is typically 6.8k in most applications. This
makes the typical full scale current at pins Iout and Ioutb 3 mA. Pin 2 is used as an
external voltage reference source of 1.18V from the internal supply of the AD5930.
This pin be used as a low voltage power supply or can be overdriven and used as
an input of a voltage between 1.15 and 1.26V to allow for a slight adjustment of the
output current.
The CTRL pin, 13 is a digital input used for the functions of initializing,
starting, and incrementing the frequency sweeps. This pin is made active by a low to
high transition synchronized with a low to high transition of master clock pulse. The
function of this pin is determined by the values stored in the control register, and the
various functions that were described above. Pin 17 is the STANDBY pin, used to
externally turn the internal DAC on and off regardless of the control register settings.
When this pin is pulled to a high value the DAC is shut down at the next rising pulse
of the MCLK. When the STANDBY pin is retuned to a low state, then at the next
MCLK transition the full functionality of the AD5930 is restored. This pin is utilized in
29
the channel selection circuit of this design, to turn off the AD5930 IC’s that are not
selected for output.
The AD5930 contains a three wire SPI interface requiring a clock pulse, a
sync pulse and a data line. SDATA, pin 14, receives the 16 bit words of data from
the data acquisition system. Pin 15, the SCLK pin provides the timing clock source
needed during information transfer. The data is transferred on a high to low
transition of from this clock source. Pin 16, the frame synchronization pin, is normally
high and must be taken low with a falling clock edge in order for the IC to accept the
data presented on the SDATA pin. In order for the AD5930 to have the complete set
of information for the frequency sweep, eight data transfers are performed, with one
register being sent during each FSYNC pulse.
MSBOUT, pin 10, is used to provide the digital output pulse when called upon
in the control register. The output is a TTL pulse of 0-5V with a frequency and
bursting profile developed in the programmed registers. Pin 19 provides a sinusoidal
or triangular current source output. Pin 20 provides the same signal, 180 degrees
out of phase. As previously mentioned, the current magnitude is determined from the
resistor chosen at pin 1.
The AD5930 requires a stable clock source at pin 8 in order to provide a
timebase for the DDS core. This source is provided by a 10MHz crystal oscillator
located on the circuit board. Because of the high frequency, multiple capacitors are
30
required to prevent clock feedthrough to the other pins. This clock must also be kept
separate from SCLK, the clock source described previously for the SPI circuit. If this
condition is not met there will be a greater chance of jitter in the SCLK which can
result in incorrect data transfer and incomplete or incorrect register filling.
There are two separate +5V power supplies, one each for the analog and
digital circuits of the AD5930. The power supplies were isolated and decoupled to
prevent clock feedthrough and noise from entering the digital circuit. Pin 4, AVDD,
was connected to the analog power supply and controls the reference and output
circuits. Pin 5 receives input from the digital power supply, DVDD, and controls the
timing, SPI programming and control circuits.
As with the power supplies there are also two types of grounding required
with the AD5930, analog and digital. The analog ground path was connected to the
GND pin of the PCI-6259, which supplied the path to earth ground. The digital
ground was taken from the DGND1 spring connector. The two grounds were tied
together at the largest common point on the circuit board to eliminate as much noise
as possible. The analog ground was connected to pin 18, AVDD, pin and served as
the ground for all analog circuitry. The digital ground, DVDD and is connected to pin
7, and pin 11, in order to properly ground the digital circuitry and the internal output
buffer. All non used pins are brought to ground as well, including pin 6, the
31
CAP/2.5V pin, pin 9, the SYNCOUT pin, the INTERRPUT pin 12, and the IOUTB pin
20.
2.1.3) Design and Testing
There were three major building blocks for this design, the NIDAQmx
program, the interface between the data acquisition unit and the circuit board, and
the final circuit board. The completed circuit board contained four AD5930 ICs, the
channel selection circuit, and the amplitude selection circuit. The integration of the
design blocks are shown in Figure 7 below:
Amplitude
Selection
NIDAQmx
Program
Data
Acquisition
Board
Output
AD5930
Demultiplexer
Figure 7:
7: Design Interconnection
The circuit board, interface, and program will be described in the order listed in this
section. The final two circuits will be described in detail in the final design section.
32
2.1.3.1) Circuit Board Design
The circuit board was built using a Radio Shack perf board rather than a
standard breadboard. This was done to protect the sensitive AD5930 integrated
circuit by isolating the power supplies and ground paths. It can be very difficult to
eliminate parasitic capacitances that can be present in a breadboard due to poor
isolation. The AD5930 was supplied as a 20 pin TSSOP surface mount package,
and in order to plug it into a standard circuit board a TSSOP to DIP adapter was
used. There was a great deal of external circuitry that was connected to the AD5930
as shown in Figure 8 below:
33
Figure
Figure 8:
8: AD5930 External Circuitry
The 6.8k resistor connected between pin 1 and analog ground is used to
determine the full scale current at the outputs IOUT and IOUTB. Pin 2 can be used
as an external reference, but is not in this design, so a 10nF decoupling capacitor is
applied between the pin and AGND. A 0.1uF capacitor is attached between pin 6
and digital ground to decouple the onboard 2.5V digital supply to DGND. This is an
external supply that can be used to power a microcontroller or similar low voltage
device, but is unused in this application. A 200 ohm resistor is used as a load
resistor for the current output at Pin 19, and a 100pF capacitor is also included to act
as a low pass filter. The unused pins and the inverting current output, IOUTB, are
shorted to ground as is common practice in digital circuit design to prevent stray
capacitance from entering the programming or output lines.
Because the master clock runs at a high frequency of 10MHz a large amount
of noise and jitter can enter into the digital circuitry. If this noise is present on the
AVDD and DVDD (pin 4 and 5) lines there can be problems with information transfer
to the device and possibly even with the stability of the device. Therefore, it is critical
that decoupling capacitors be applied between AVDD and AGND and DVDD and
DGND. The 10 µf capacitor is used to filter any noise that may be present on the line
from the PCI-6259, including 60 HZ line noise, while the 0.1 µF capacitor blocks the
high frequency noise.
34
In addition to the AD5930 integrated circuit, the board also contained a
10MHz crystal oscillator, used as the MCLK for the IC. Eight AD5930 chips were
used to provide a total of eight channels of output, with four being present on each of
two boards. To control the channel selection the output lines of a demultiplexer IC
were tied to the STANDBY pin of each of the AD5930 chips. When a low signal was
applied from the demultiplexer, the appropriate channel was active and the other
seven channels were disabled. The output from pin 19 was then sent to a
programmable gain amplifier to adjust the voltage to between a -10 to 10 volt range.
The adjusted output from the PGA was connected along with the digital output at the
final connector.
2.1.3.2) Interface with Data Acquisition Unit
In order to program the circuit board eight digital and two timer lines were
connected from the data acquisition unit. The isolated 5V power supply and
grounding lines were connected from the PCI-6259 as well. The PGA needed a
+15V and –15V supply for operation, and these were provided separately from a
bench power supply. The ground planes from the power supply and data acquisition
unit were tied together. DIO0 was used as the FSYNC line and was connected to
pin 16 of the AD5930, while DIO1 and DIO2 were used as the SCLK and SDATA
(pins 15 and 14) respectively. Digital lines 3-5 (DIO 3-5) were used as the three
35
channel selection lines of the demultiplexer. DIO6 was used for the synchronization
line for the PGA while the SDATA and SCLK lines were the same as for the
AD5930.
The timer line needed for this application was CTR0, which functioned to
provide the initial delay before the control pin initiated the first frequency burst. The
output was initially held low for the length of the delay before pulsing high for one
millisecond. This time was selected to allow for a long enough low to high transition
to occur, but short enough to not interfere with the length of the frequency burst.
In addition to the timer and digital output lines, a programmable function input
PFI0 was used to provide an external 10 MHz timebase from the crystal oscillator.
This was used to synchronize the digital lines and timers with the MCLK of the
AD5930. This attempt was made after failing to synchronize the MCLK and the
internal 10 MHz timebase. It was also discovered that the internal timebase could
not be used as the MCLK for the AD5930 because it is impossible to output the
internal clock while using it for timed data transfer.
2.1.3.3) NIDAQmx Program
The NIDAQmx program consisted of several acquisition events to properly
program the registers for the AD5930, send the proper information to the
36
demultiplexer for the proper channel, the PGA for the proper amplitude, and initiate
the frequency burst. An overview of the program is shown in Figure 9 below:
37
START
Load Libraries
Get info from User
Loop for Number of Channels
Loop for Number of Bursts from AD5930
Integer to Binary Conversion for Registers
Millisecond to Clock Tick Conversion for
Initial Delay
NO
Interpulse
Delay
the Same ?
YES
Burst Register Used
and Timer 1 Disconnected
Millisecond to Clock Tick conversion for
Interpulse Interval-Timer 1 Enabled
AD5930 and PGA Buffers Created
Hardware Tasks Created
AD5930 and PGA Data Sent
YES
Static DIO Lines Data
Sent
YES
Start Pulse
Sent
Stop and Clear Tasks
Another Simulation
from this channel?
NO
Another Channel
In Experiment?
NO
END
Figure 9:
9: Overview of NIDAQmx Program
38
To begin, the library and header files for the NIDAQmx functions were
included and all global variables were declared. The next step was the setup for the
user interface that allowed the user to enter the values for all of the parameters
including: the total number of data transfers to take place, the number of the channel
to be simulated, the initial delay, the initial frequency, the wavetype, the number of
cycles per burst, the delay time between pulse bursts, and the amplitude.
After the user entered values into the interface it was translated in the
program from integer to binary values that could be recognized by the registers. This
was done using a routine that performs an integer to binary conversion, and stores
each of the binary numbers as separate elements in an array. The final four values
for each register were filled with the four digit code unique to that register. The code
for this conversion is shown in Figure 10 below:
while (n<10)
{
value[n]=intvalue[n]/2;
brst[n]=intvalue[n]%2;
intvalue[n+1]=value[n];
n=n+1;
}
Figure 10:
10: Integer to Binary Converter
39
The while loop in the subroutine continued until the entire array was filled.
The binary values were found by dividing the value by two and storing the remainder
in the register array. When the divided value reached zero then the rest of the array
became filled with zeros. The array was stored and added to the digital line transfer.
In the main part of the program, two loops controlled the output to the digital
and timer lines. The first loop was iterated to the value given by the user when asked
how many channels of stimulation would be required for the experiment. This
allowed the user to run multiple simulations from either one or many different
channels without having to restart the program repeatedly. Within this loop there was
a second loop that updated the values for each channel of stimulation. This loop
updated the registers and delays for each pulse generation and continued until the
number of stimulations for that channel was reached. The first seven registers of
each stimulation were filled as described above using the decimal to binary
conversion. The final register, the control register, contained mostly standardized
values and was mostly unchanged. The only two bits that were typically updated
were the two wavetype bits, which depended on whether a sinusoid or square wave
was selected. After the AD5930 registers were filled, the PGA registers were filled
using the integer to binary converter to give the value for the amplitude.
After filling the registers, the number of counter ticks for the initial and
interpulse delays was found. The initial delay was converted from the millisecond
40
value entered by the user to the number of clock cycles by multiplying the value by
10000. This converted 1 millisecond to 0.1 microseconds, which is the value of one
clock pulse. This value was passed to the CTR0 timer setup function. The interpulse
delay could be entered as either a constant or variable value. If the pulse value was
constant then the incremental interval register value of the AD5930 was used and
CTR1 was idle. However, if this value was variable, the CTR1 timer was loaded with
a value found in the method shown below:
InterpulseInterval=InitialDelay+n*BurstTime+n*Interpulsedelay
Where n is the waveform number being output
The register contents were loaded into two buffers, one for the AD5930 and
one for the programmable gain amplifier. The AD5930 buffer was 136 bits long,
containing information from all eight registers plus one 0 data bit in between register,
to keep time while the clock was low. The PGA buffer was 24 bits long and could be
output continuously. After the buffers were loaded, the data transfer began. The first
set of data output was for the AD5930 registers, which required three data lines. The
external 10MHz source was applied through the PF0 line and assigned to an analog
output channel, because digital lines do not accept external clock sources. The
analog output was connected to the digital lines DIO1 and DIO2 so that the SCLK
41
and SDATA were in sync. DIO0 for the FSYNC line was set to a value of zero, and
the data for the registers was written to the digital lines. To complete the data
transfer DIO0 was pulled back to a high value. This process was then repeated for
the PGA registers, except that DIO6 was used as the FSYNC line instead of DIO0.
The static channel data was written to the demultiplexer from lines DIO3-5.
The values written were found by comparing the channel requested by the user to
eight conditionals. When the proper channel was found, low or high output values for
DIO3-5 were given. After all of the appropriate data was written, the AD5930 was
turned on after the initial delay, provided by CTR0. If the interpulse interval differed
between frequency bursts the CTRL pin was pulsed from CTR1 when necessary. In
order to ensure that the data was updated each time through the loop all of the
TaskHandles were stopped and cleared. A complete copy of the program can be
found in the appendix.
2.1.3.4) Testing Methods
In order to properly test the board a complete assembly was built on two
separate perf boards and were carefully wired. 32 AWG hookup wire was used for
the signal lines and 22 AWG wire for the connectors, grounds and power lines.
Before applying power, each of the circuits was completely static tested and
compared to each of the other circuits. This helped to prevent accidental shorting of
42
power and signal lines, and to make sure that none of the digital lines were crossed.
When this was completed the first step was to test the AD5930 alone, without the
channel or amplitude circuits connected. The values loaded into the registers are
shown in Table 7 below:
Register
Values Loaded
Binary Word
Control
Start Frequency MSB
Start Frequency LSB
Freq Increment MSB
Freq Increment LSB
Number of Increments
Incremental Interval
Burst Time
Sine Wave, DAC On, MSB Off, Saw
Sweep, Internal Burst and Increment
10kHz
10kHz
+10kHz
+10kHz
50
100 clock cycles
100 clock cycles
0000 1110 1001 0011
1100 0001 0001 1011
1101 0000 0000 0100
0011 0001 0001 1011
0010 0000 0000 0100
0001 0000 0011 0000
0100 0000 0110 0100
1010 0000 0110 0100
Table 7: AD5930 Register Values for Experiment
In addition, for simplicity, a constant interpulse interval was selected so only one
timer output was required. A value of 20ms was chosen so that it could be easily
seen on an oscilloscope.
When the power was applied, the output had a value of zero volts at the
current output. The registers were changed to allow for digital output, but this failed
as well. In addition, it was noted that the current output should have a value of 1.2
volts, even without an output, which it did not. After trial and error, it was found that
this occurred because the two 5V supplies were not properly isolated. This was
corrected by using two separate lines from a bench power supply. After this was
43
corrected, however there were still no frequency bursts present at either the digital
or current outputs.
At this point, it became relevant to test the other two parts of the circuit to see
if they were working properly. It was immediately clear that the demultiplexer circuit
worked as expected and turned off all of the AD5930 IC’s except one. The
programmable gain amplifier, however, had the same problems as the DDS chip. In
this case no change was seen in the output voltage from the input voltage, which
occurred when register values of 0 were applied. This was not surprising because it
used the same SPI programming interface.
At this point one AD5930 and one PGA were removed and isolated from the
rest of the board by installing them into a breadboard. The test was retried for each
device and the same failure pattern was seen. It was determined after careful
inspection of the oscilloscope traces that the reason for this failure was the lack of
synchronous data transfer between the FSYNC, SCLK, and SDATA lines. Although
the FSYNC line was held low during each data transfer it was impossible to properly
turn the line on at the same clock cycle at the end of the data transfer. This made an
eight bit transmission, a nine or ten bit data transfer, causing the registers to be
loaded incorrectly. This was a problem for the PGA as well even though all three
registers could be written to at once without pulsing the FSYNC. Instead of 24 bits of
data the PGA was receiving 27 or 28. The final values were either all ones or zeroes
44
depending on the last bit transferred, which gave the IC’s the impression that
another register was being written to.
This problem occurred because the PCI-6259 board can only synchronize two
lines to one clock source. It is also impossible to synchronize two separate clock
sources to trigger on the same clock pulse using the NIDAQmx system. The digital
lines could not trigger at the same time as a counter, which was tested by using one
of the timer lines as the FSYNC line. This was not possible because of the linear
programming of NIDAQmx. The digital lines were always written first, and the timer
line could also not be synchronized. Without being able to synchronize three lines, it
was concluded that it was not possible to program an SPI line using the data
acquisition system and NIDAQmx.
2.1.3.5
3.5)) Future Applicability
2.1.
3.5
At the present time it is unknown whether or not using the PCI-6259 data
acquisition system with NIDAQmx will ever be an option for this design. The major
issue to overcome is the capacity to synchronize multiple digital lines to one source.
If this becomes available, then this is an upgrade that would be worth purchasing,
because of the ease of programming and set up of the system. Another possibility
would be to use two data acquisition board with a common clock source. NIDAQmx
can easily program two boards at the same time in this manner, unlike with multiple
45
lines in the same system. This method however, would involve the expense of the
purchase of another data acquisition unit and the work of internally jumpering the
boards together.
2.1.3.6
3.6)) Design Replacement
2.1.
3.6
In order to overcome the shortcomings of the data acquisition system, an
AVR Butterfly microcontroller with an SPI interface was chosen to replace the DIO
lines under NIDAQmx control. In addition, the Butterfly contains 8 DIO ports that can
be used for the channel selection, and three timers which can be used for delays.
2.2) AD5930 with Microcontroller Control
2.2.1)
2.2.1) Microcontroller Overview
The
AVR
Butterfly
application
board
consists
of
an
Atmega169
microcontroller and a RS232 level converter allowing it to be programmed over a
serial connection. In addition the Butterfly has several peripherals including an LCD
display, joystick, piezoelectric buzzer, and three programming interfaces, JTAG, SPI,
and USI. The Atmega169 microcontroller uses Reduced Instruction Set Computer
(RISC) architecture. RISC uses a small, highly-optimized set of instructions, rather
than a more specialized set of instructions often found in other types of
architectures. (19) This is ideal for this application where a small number of different
46
instructions must be performed in a very quick time period. For this design the three
functional areas utilized from the microcontroller were the SPI interface to program
the AD5930 and PGA registers, two timers for the initial and interpulse delay, and
three I/O ports to control the channel selection.
2.2.1
.1)) SPI Interface
2.2.
1.1
The SPI interface is a synchronous serial data linkage between two electronic
devices, most commonly between a microcontroller and a peripheral device. (19)
The device that initiates and generates the data is known as the master, while the
receiving device is known as the slave. An SPI device is a four line device, but only
three lines are active, depending on whether it is being used as a master or slave.
The fourth line allows several peripherals or multiple controllers to communicate
together. The important SPI pins are shown in Table 8 below:
Port
MISO
MOSI
SCLK
SS
Full Name of Port
Master Input-Slave Output
Master Output-Slave Input
Slave Clock
Slave Select
Function of Port
Receives data from device
Sends data to peripheral device
Clock for sending data to peripheral device
Frame Synchronization between master and slave
Table 8: SPI Pins and Functions
To transmit information the master pulls the slave select line low and an 8 bit
word of data is sent from the MOSI line at each clock pulse. The slave select line
can be pulled high in between words or can be kept low for a multiple of 8 bit words,
along for multiple bytes of data to be sent. When the data transfer is complete the
47
SS line is pulled high and the master is shut down. The Atmega169 microcontroller
has a complete SPI interface, with the device control as a master or a slave done by
programming the SPI registers. An overview of the Atmega169 SPI interface is
shown in the Figure 11 below:
Clock Divider
Data Bus
Data Buffer/
Shift Register
MISO
MOSI
Clock Select
Clock Logic
Pin Control
Logic
SCLK
SS
SPI Control
Status Register
Control Register
19)
Figure 11: Overview of the Atmega169 SPI Interface ((19
19)
The most important blocks of the interface are the pin control logic, the data
buffer/shift register, clock system, and control system. The pin control logic
determines the direction of the data, and controls the enabling of the SCLK and SS
lines. The shift register moves the data out of or into the data buffer using a serial
method. The clock system is further subdivided into the clock divider, selection and
logic circuits. The clock division and clock selection circuits work together to scale
the original clock speed to values of up to 128 times less than the original value. The
48
clock logic circuit controls transfer parameters including the clock polarity, when the
data is sampled, and if the data is sent or received LSB or MSB first. The control
section is used to activate the SPI section, control whether the action is a master or
slave, and the control of interrupts. The SPI circuitry is controlled through three
registers, the SPI control register (SPCR), SPI status register (SPSR), and the SPI
data register (SPDR).
The SPCR register is used to define the various parameters of the SPI
transfer. The functions of the eight SPI bits are shown in Table 9 below:
BIT
NUMBER
7
6
5
4
BIT
NAME
SPIE
SPE
DORD
MSTR
3
2
CPOL
CPHA
FUNCTION
Enable SPI interrupts
Enables SPI
Order data is transferred
SPI function, Master or Slave
Clock polarity between data
transfers
When data is sampled
1
SPR1
With SPR0 and SPR2, clock division
0
SPR0
With SPR1 and SPR2, clock division
When Bit is
1
Enabled
Enabled
LSB
Master
High
Trailing
see
appendix
see
appendix
When Bit is 0
Disabled
Disabled
MSB
Slave
Low
Leading
see appendix
see appendix
Table 9: SPCR Register Bits (19)
The three bits of the SPSR register monitor the data transfer and interrupts as
necessary. The SPIF bit is set when a serial transfer is completed, generating an
interrupt if the SPIE bit in the control register is set and global interrupts are enabled.
The SPIF flag can then be cleared when the interrupt completes or by reading the
49
status register and then writing to the data register. The WCOL bit is set when the
SPDR register is written to during a data transfer. This automatically stops the data
transfer and is cleared by reading the status register and then accessing the data
register. Bit SPI2X is used along with SPR1 and SPR0 in the SPCR register to set
the clock scale value. The relationship between the clock frequency and these three
bits can be found in the appendix.
The SPDR register is the read or write buffer for the data transfer. The
behavior of this register is handled by the actions of the bits in the SPCR and SPSR
register. When the correct parameters are set the data transfer is automatically
initiated when data is present.
2.2.1.2)
2.2.1
.2) I/O Ports Used for SPI Transfer and Delays
The Atmega169 contains 48 I/O lines or pins, separated into six ports (A-F)
that can be used for general I/O. When a port is used in general form it can be used
to transfer data continuously or can vary for a time period based on the internal
oscillator. In addition, each line has an alternate function used in the control of the
peripheral devices. A line is, by default, used in the general configuration and in
order to access the alternate function the line must be overwritten by the program.
To prevent a loss of information it is a common practice not to use the same pin for
both a standard and alternate function in the same program.
50
2.2.1.3
.3)) Programming the Microcontroller
2.2.1
.3
A microcontroller is controlled by programming the internal memory and I/O
registers using either assembly language or C programming. In order for the
microcontroller to understand the commands, the program is converted with a
specialized compiler to a .hex or .eep file. The compiler used by the AVR Butterfly is
the GNU Compiler Collection or GCC. This C compiler uses a makefile to create
several different files, including the .hex and .eep. GCC and the makefile program
are part of a larger suite of programs known as WinAVR, which gives the C program
the functionality to control the entire AVR series of microcontrollers.
When completed, the program is loaded temporarily into a flash memory or
semi-permanently into EEPROM using a specialized programmer. For the Butterfly
either an in system (ISP), UART, JTAG, SPI or parallel programmer is available for
use. For the initial stage of development a proprietary software package, AVR
Studio, was used to load the data to the microcontroller through a UART interface.
This software allowed either a .hex or .eep file to be transferred, but the .hex file was
always used in this design.
GCC is very similar to C in its structure and functionality, especially in
important programming areas such as conditionals, loops, arrays, structures and
51
functions. In addition, specialized statements are used to set register bits, interrupts,
and data values. An example of setting and clearing a register bit is shown below:
PORTB |= (1<<PB1);
PORTB &~ (1<<PB1);
In addition to setting bits individually, the values of an entire register can be
programmed simultaneously as shown below:
DDRB=0x07;
This command turns on the first, second and third bits of the DDRB register, while
leaving bits four through eight with a value of zero. Besides general commands such
as setting or clearing bits each function of the microcontroller has a library with a
specialized set of registers and instructions.
The program flow in GCC is directed using functions and interrupts. A GCC
function operates in the same manner as a C function with the additional operations
of turning on and off register bits, or initiating hardware actions. An interrupt is a
hardware event occurring when a preset value has been reached or a data register
is full or empty. The interrupt in effect stops the main part of the program and
executes separate instructions until the end of the interrupt is reached. A function
52
can be called once or multiple times, but will only occur once unless recalled. An
interrupt repeats every time the hardware reaches a particular point and must be
stopped from occurring. This is typically done by checking the interrupt with a
conditional, and when a certain point is reached, disabling the ability to generate
interrupts.
The structure of a GCC program is organized in the same manner as a C
program. To begin, global variables are initialized and all functions and interrupts are
declared. Any programmed interrupts are placed before the “main” function of the
program and all other functions are placed after the “main” function. The “main”
function includes general instructions and organizes the function calls in the order
that they need to be performed. In a GCC program, at the end of the “main” function
an infinite while loop is placed. This loop allows the program to continue executing
interrupts and hardware commands after all of the functions have been called from
“main”.
A program ends when all of the functions, hardware commands, and
interrupts have been executed.
2.2.2) Design and Testing
The second design consisted of circuit boards containing the AD5930 and
Butterfly, the interconnection between the two devices, and the control of the
53
microcontroller through the GCC program. An overview of the design in shown in
Figure 12 below:
GCC Program
AVR Studio
Micro
controller
AD5930
Amplitude
Selection
Output
Channel
Selection
Figure 12: Overview of Microcontroller/AD5930 Design
2.2.2.1)
2.2.2
.1) Circuit Board Overview
For this design six circuit boards were required, one for the Butterfly
microcontroller and demultiplexer, four separate boards for the AD5930 and PGA
IC’s, and one for the crystal oscillator. Separate boards were developed to better
isolate the circuits and to prevent the oscillator from damaging the microcontroller.
Each AD5930 board contained two chips and a PGA, so that two channels would be
located on each board. The microcontroller board contained the Butterfly and the
demultiplexer, along with the connectors to interact with the AD5930 board. The
crystal oscillator was placed on a separate board with connectivity only to the MCLK
pins of the AD5930 chip, and a power supply.
All of the circuits developed for the first design were identical except that the
connection was to the microcontroller instead of the data acquisition unit. Both the
54
AD5930 and the microcontroller were very sensitive to noise in their digital circuitry,
requiring that the analog and digital power lines to be isolated as much as possible.
The microcontroller and demultiplexer power bus were connected to the DVDD of
the AD5930 and the ground was attached to DGND. The crystal oscillator also used
the digital bus, but was placed as far as possible from the microcontroller, and the
MCLK line was completely isolated from the supply. The PGA required +/- 15V and
these lines were wired separately from the 5V bus. For proper grounding AGND and
DGND were separated and connected at one point, the bench power supply. As in
the previous design all power and ground lines were 22AWG wire and all signal
wires were 32AWG.
2.2.2.2)
Microcontroller
2.2.2.
2) Interface Between Microc
ontroller and Other Circuits
The microcontroller used the alternate function of three port lines with their
alternate function, PORTB0 (FSYNC), PORTB1 (SCLK) and PORTB2 (SDATA) to
control the SPI interface of the AD5930. The PGA utilized the same SCLK and
SDATA lines but used a separate FSYNC line, PORTD0. An additional pin was used
to pulse the control pin (PORTB6), after the initial delay and between frequency
bursts when necessary. In order to address the demultiplexer three pins from port D
were used (PORTD1, PORTD2, and PORTD3).
55
2.2.2.3)) Programming Overview
2.2.2.3
To test the microcontroller, the AD5930 and other circuitry a simple GCC
program was developed. The values for the registers, delays and channel were
given as constants, chosen to provide output that would be easily recognizable. The
GCC program was then broken into five functions summarized in Table 10 below:
Function Name
SpiInit
SpiSendByte
SpiSendByte2
ChannelSelect
PulseDelay
Purpose
Sets SPI Transfer Parameters
Sends SPI Data to AD5930
Sends SPI Data to PGA
Addresses Multiplexer
Sets CTRL pin after initial delay
Table 10: Functions in GCC Program
For further simplification it was decided the CTRL pin would only be used for the
initial delay and the interpulse interval would be controlled by the incremental
interval register of the AD5930.
The SPI initialization function (SpiInit) sets the data register (SPDR) to 0 and
the bits of the SPCR as shown in Table 11 below:
56
Bit Name
MSTR
SPRO
SPR1
CPOL
CPHA
DORD
SPE
SPIE
Setting
1
1
1
1
1
0
1
1
Function
Sets SPI to master mode
With SPR1 lowers CLK by 16
With SPR0 lowers CLK by 16
Idles high between writes
Data sampled on falling edge
Data sent MSB First
Enables SPI
Enables SPI Interrupt
Table 11: SPCR Register Settings for AD5930
AD5930 Programming (19)
The spiSendByte function contained the commands to control the transfer of
data to the AD5930, in sixteen 8-bit transfers. Each data transfer is summarized in
the code shown in Figure 13 below:
PORTB &= ~ (1<<PB0);
spiTransferComplete = FALSE;
SPSR &= ~ (1<<SPIF);
SPDR=data1;
while(!(inb(SPSR) & (1<<SPIF)));
SPSR |= (1<<SPIF);
spiTransferComplete = FALSE;
SPSR &= ~ (1<<SPIF);
Figure 13: SPI Data Transfer GCC Code
The data transfer began by forcing the FSYNC data line low and then setting
the
flags,
spiTransferComplete
to
false,
and
SPIF
to
0.
When
the
spiTransferComplete flag is set to true and the SPIF bit is set to 1 the data transfer is
complete, otherwise it continues. The eight MSB of the first register are loaded into
57
the data register and sent. The transfer continues during the period of time set in the
while loop, when the SPIF flag has not been set. When the transfer is complete, the
flag is set by the hardware, and in order to clear the bit, it must be set by the user
and then cleared. Because there is more register data remaining both flags are not
set and the process repeats. When all of the data has been transferred the flag is set
for a final time, spiTransferComplete is set to true and PB0 is reset to high.
To address the demultiplexer to set the proper channel the ChannelSelect
function is called. This simple function takes the channel value and compares it with
eight conditional if-then statements. When the channel is found the proper lines are
turned on or off setting the address bits of the demultiplexer.
After the data has been successfully sent to the AD5930 and demultiplexer,
the last step is to apply the pulse to the CTRL pin starting the waveform generation.
This is done by the following code in Figure 14:
void PortWrite(int firstdelay)
{
/* enable PD5 as output */
DDRD=0X0F;
PORTD |= (1<<PD6);
_delay_loop_2 (firstdelay);
PORTD &~ (PORTD,PD6);
_delay_loop_2 (firstdelay);
PORTD |= (1<<PD6);
}
Figure 14: Example of CTRL Pin Activation
58
For the pulse to be generated, PD6 was enabled for output, and immediately
cleared so that it did not prematurely activate the CTRL pin. The initial delay was
given in milliseconds and was stored as the variable firstdelay. This value was
placed in an internal function that creates a delay based on a number of clock
cycles, microseconds, or milliseconds. The delay loop was executed until reaching
the value of firstdelay when the pin was turned on.
Another delay loop was
executed so that the pulse width could be seen and to verify that its rise and fall
times were long enough for the AD5930.
At this point the program was compiled using a makefile and the .hex file
created. The microcontroller was programmed using AVR studio and executed by
cycling power to the Butterfly and pushing up on the joystick.
2.2.2.4)) Testing Methods
2.2.2.4
Another advantage to choosing this microcontroller was the ability to use a
simulator, VMLAB to see verify that the SPI interface and the I/O lines were
functioning appropriately. This was very used to see the three SPI lines
synchronized and that the delay to turn on the device would occur after the data had
been transferred. The simulator showed that the output was the three SPI lines were
properly synchronized. The scope data was transferred to Excel and can be seen in
the Figure 15 below:
59
5
4
FSYNC
SCLK
3
SDATA
2
1
0
1
5
9 13 17 21 25 29 33 37 41 45 49 53 57 61 65 69 73 77 81 85 89 93 97
Figure 15: Example Scope Data from VMLAB
Knowing that all of the signals were appropriate, the same values for the
AD5930 registers were used as in the previous design, and the microcontroller was
programmed. The signals were verified using a dual channel oscilloscope, so that
two lines could be compared simultaneously. Before applying the microcontroller
the AD5930 was checked for proper output voltages, and the expected values were
present. The microcontroller was then turned on and the output at both the digital
and current outputs became active. Instead of multiple frequency bursts from one
line, a sinusoid of multiple harmonic frequencies appeared at the current output. At
the digital output a square wave appeared with a frequency the same as the
oscillator.
Assuming that the DDS chip may not have been properly filtered, capacitors
to block lower frequencies were installed, but this had no effect. In addition, both
60
lines were giving an output regardless of the settings in the control register. As
before, the AD5930 was removed and placed in a breadboard to try and eliminate
any noise present in the circuit, but the results were identical to when it was in the
circuit board. To try and reduce the noise from the crystal oscillator, a function
generator was used as a clock source. The sinusoid and digital pulses became
sharper, but the harmonics remained. At this point the manufacturer, Analog
Devices, was contacted, and the failure analysis given was that too much noise was
in the digital lines corrupting the data. While the signal appeared clean when it
arrived at the IC, it was being corrupted when it reached the DDS core of the
AD5930 giving random outputs instead of the requested. At this point an additional
filter was installed at the MCLK line, but this only reduced the largest harmonic on
the output and did not stop the problem from occurring.
After the test for the AD5930 failed, the PGA was tested separately using the
breadboard. This device worked as expected, with the voltage being reduced to the
degree set in its three registers. One reason why the MAX532 may have worked
properly is that it is a DIP integrated circuit while the AD5930 is a TSSOP. A DIP IC
is much less sensitive to noise because its die is further away from its surface.
Another explanation is that the MAX532 does not receive an input from an oscillator,
and that this clock is corrupting the data. The functional PGA device further proved
61
that the AD5930 was receiving too much noise, and that it could not be used in this
application at this time.
2.2.2.5) Future Applicability
There are two possible ways that the AD5930 integrated circuit could be used
in the future. The first possibility would be to purchase an AD5930 development
board specially designed to allow the user to create applications using this IC. In
addition, software is provided to program the registers and initiate the control pin.
This method at this time is not cost effective, which is why it was not pursued. In
addition, for the final design up to eight units would need to be purchased, or the
channel control circuit would have to be redesigned.
The other method of using the AD5930 would be to have a four layer circuit
board built so that the ground and power planes can be properly isolated. A four
layer board is nearly impossible to build without being professionally machined. This
method is cost restrictive because there is still some doubt as to whether this IC
would be best for this application. Several programming issues could prohibit this
design from working such as when only one frequency or longer times than 0.5
seconds were needed.
62
2.2.2.6)) Design Replacement
2.2.2.6
A replacement design was developed using the timer/counter lines of the
Butterfly microcontroller. The timers can be programmed with adjustable
frequencies, initial delay times, and interpulse intervals. The one drawback of the
Butterfly was that it could only provide a 0-5 V TTL output. An eighth order Bessel
filter IC was used to filter the TTL pulse to a sine wave. Wavetype selection was
accomplished using an analog switch to direct the signal to the appropriate circuit.
For amplitude control the programmable gain amplifier was kept, and continued to
use the SPI lines. The channel selection continued to be controlled by the
demultiplexer, but its output was directed to turn on only one of eight analog
switches.
2.3) Microcontroller DDS System
2.3.1
2.3.1)
3.1) Motivation
Because the AVR Butterfly microcontroller has built in timer/counter lines, the
consideration of using it for waveform generation was thought about when still using
the AD5930. The method was not pursued until it was proven that this IC would not
work, because the timers have a lower resolution then the AD5930. The AVR
Butterfly has two 8 bit timers and one 16 bit timer, but it was found that with proper
programming it was possible to generate the entire range of needed pulses from 0.1
63
millisecond to 1 second with a time step of 0.1 millisecond. In addition, it is possible
to control the initial delay, interpulse delay, and interstimulus delay. While the
microcontroller does not output sinusoids, they are easily generated by the use of a
filter. The original program was modified to include the waveform generation code,
and the original code was used to control the I/O lines and the SPI for the PGA.
2.3.2) Design Overview
The final design of the neurophysiologic stimulator allowed the user to enter
the waveform type, on and off times, the amplitude, the channel, and the initial delay
into a Matlab GUI. The microcontroller outputs a 0-5 volt pulse with the requested
timing characteristics that is applied to an analog switch to select the waveform type.
The switch separates the signal into separate circuits for the sinusoid and digital
waves. In the sinusoid circuit, the filter requires that the waveform be split into two
values, one with the frequency 100 times the other. This is done by passing the
initial waveform through a 1:100 frequency divider. The sinusoid is then created
using an eighth order Bessel filter.
At this point the sinusoid and square wave circuits have the same circuitry,
but are kept in separate paths. The signal is amplified to 10V using a standard
operational amplifier. The amplitude is then adjusted to the requested value between
-10 and 10V using a programmable gain amplifier. As in the previous designs the
64
PGA is programmed using the SPI interface of the microcontroller. The amplitude
adjusted output is applied to a series of analog switches used to choose the required
channel. The channel is selected from the output of the demultiplexer, which is
addressed from the microcontroller. The output is then made available at one of the
eight two pin connectors.
The final design was able to implement most of the functionality of a DDS
system using the microcontroller and outlying circuitry. The device uses a master
reference clock of 2 MHz, the internal oscillator of the microcontroller. The
timer/counter circuit functions on the number of MCLK pulses to generate an output
frequency. This value is set into a register and the timer counts to it before turning
the pulse on or off. This method is nearly the same as using a delta phase register
and look up table. The digital to analog conversion is where the design differs, with
the sinusoid being formed from a Bessel filter instead of a digital to analog converter.
This design overcomes some of the shortcomings of a DDS system as well,
including the ability to output longer pulse times and the presence of very little noise.
2.3.2.1)) Waveform Generation
2.3.2.1
The Atmega169 microcontroller has three programmable timer/counters that
are accessible as alternate functions at four of the PORTB lines. Two of the timers
65
are 8 bit, and one has 16 bit resolution or can be split into two 8 bit timers. An
overview of the timer/counter circuit is shown in Figure 16 below:
Overflow
Interrupt
Request
TCCRn
Control
Logic
Clock
Select
Tn
Clock Input
(Internal
or External)
Bottom
Data
Bus
Timer/Count
er
TCNTn
=
=0x00
Top
=0xFF
Compare
Output
Waveform
Generation
OCn
Signal
Interrupt
Request
OCRn
Figure 16: Overview of Atmega169
Atmega169 Timer/Counter Circuits (19)
(19)
The internal clock of the microcontroller is 2MHz, and this timebase can be
used or divided by 8, 64, 256, or 1028. With this large range of clock dividers the
hardware timers can output a pulse between 0.1 µs to 0.25s. Longer pulse widths
can be implemented by using software timing or manipulating delay loops.
The counter can have one of three functions, MAX, BOTTOM, or TOP. (19) A
MAX counter begins at the lowest value 0x00(0) and counts to the maximum value
0XFF (255). The BOTTOM counter works in reverse from the maximum to the
lowest value. A TOP counter begins at either 0x00 or 0xFF and counts up or down to
66
a value specified by the user. Each type of timer can be controlled by hardware or
software. A hardware timer will only turn a pulse on or off at the pin that functions as
its output. This is much faster than a software timer, where the default output pin is
turned off and any DIO line can be used to generate the pulse output. In this design,
both of these methods are used together to allow for the entire range of frequencies
to be available.
There are four different operating modes for the counter/timer: normal, phase
correct PWM, clear timer on compare match (CTC), and fast PWM. (19) In the
normal mode the counter always counts upward to the highest value and then
restarts from 0x00. The CTC mode counts from 0x00 to a value requested by the
user, and when this value is reached the counter starts over again from 0x00 and
repeats. In phase correct PWM mode the counter counts from BOTTOM to a MAX
value requested by the user between 0 and 255 (2^8 choices for 8 bit counter), and
then counts back to the BOTTOM value. The MAX value is given by. In fast PWM
mode the counter counts from 0x00 to 0xFF and then counts back to 0x00. This
method is considered fast, because the output is set or cleared when the value in
the OCRnA register is reached and the reverse is done when it reaches 0xFF. When
the counter reverses the direction the value is set or cleared as it reaches OCRnA
again and the reverse occurs when 0x00 is reached. (19)
67
When a TOP or MAX value is reached the hardware timer can be set or
cleared, and an interrupt can be executed. When the timer mode is set to reach a
TOP value this triggers an overflow interrupt. By contrast, when the mode is set to
reach a MAX value in the OCRnA register, a signal interrupt occurs. During an
interrupt any number of commands can be executed to change pin outputs, allow
pins to receive inputs, or change the values of registers to alter the flow of the
program. It is important to note, however, that during an interrupt, the timer does not
stop and, if a large number of commands are present, the interrupt may be missed
leading to improper operation.
2.3.2.2)) Wavetype Selection
2.3.2.2
There are two types of waveforms that can be generated by the
neurophysiologic stimulator, square and sinusoidal. A TTL, 5 volt pulse is generated
automatically by the microcontroller, and must be filtered to become a sine wave. In
order to separate the square and sine wave circuits an analog switch, DG425 is
used. An overview of the IC is shown in Figure 17 below:
68
Figure 17: DG425 Internal Circuit (22)
(22)
This IC contains two DPST switches that can be programmed separately from
the microcontroller by manipulating the two input lines, IN1 and IN2. (22) When the
line is pulled high the input becomes active, and when the line is pulled low the input
is inactivated. For the wavetype selection circuit the sine wave is selected by IN1
and the square wave by IN2. For a square wave output the pulse is applied directly
to the amplitude selection circuit, while for the sinusoid circuit the pulse is applied to
a frequency divider.
The frequency divider circuit uses a SN74HC390 IC that has two divide by
two, and two divide by five counters. Each of the divide by two and divide by five
counters has a separate clock input. This allows for the possibility of creating a
divide by 100 counter by using all four inputs. The original waveform from the
hardware timer is 100 times the requested frequency, and the frequency divider is
used to return the original value.
The MAX292 works as a switched capacitor-filter with internal summing and
scaling circuitry. (23) The MAX292 has a linear phase response in the passband,
69
which preserves the waveform, and the capacitor-filter attenuates the higher
frequencies to give the rounded edges. This is optimized to the creation of a perfect
sinusoid by using a clock source exactly 100 times the requested value, which is the
maximum clock to corner frequency. (23) The original and frequency divided waves
are applied to the IC and the sinusoidal output is then applied to the amplitude
circuit.
2.3.2.3
2.3.2.
3) Amplitude Selection
The output from either the sinusoid or square wave circuits is 5 volts. A
standard non-inverting op-amp raises the voltage to 10V, the maximum voltage
required by the pulse generator. Next, the output is applied to the programmable
gain amplifier to adjust the voltage to between -10 and 10 volts. A programmable
gain amplifier is a device that acts as an op-amp with an externally adjustable gain,
using a serial data word to control a multiplying analog to digital converter (MDAC)
which in turn controls the feedback resistor of the internal op-amp. (27)
The final two MSB’s of the data word decode a series of three switches
determining the total reference current that is available to the MDAC. (27) Each
switch when closed removes ¼ of the overall current, and the closing of more
switches continues to lower the current, lowering the output voltage. The reference
70
current is reduced to the final level using ten different switches in an R-2R pattern as
shown in Figure 18 below:
Figure 18: Internal MDAC of the MAX532 Programmable Gain Amplifier (27)
(27)
The inputs to the resistor network correspond to the register values in order
from MSB to LSB. If an entire register of zeroes is loaded, an open loop condition
occurs and the amplifier is saturated to the input voltage. Closing more of the
switches further increases the resistance, lowers the current and effectively reduces
the amplifier gain. The last step of the MDAC is to convert the current back to a
voltage using the output amplifier and a feedback resistor. The conversion is done
using the following formula (27):
Vout= -D* Vref
In this equation Vout is the output voltage, Vref is the input voltage and –D is the
fractional representation of the digital word and has values between 1/4096 to
71
4096/4096. The converted output voltage is available at the voltage output pin.
Because the output voltage is inverted another op-amp circuit is used to correct the
polarity.
2.3.2.4)) Channel Selection
2.3.2.4
The neurophysiologic pulse generator uses eight channels that are
individually controllable by setting one of the eight DPST switches. The analog
switch utilized in this circuit is identical to that in the wavetype selection circuit, but
the input lines are controlled by the demultiplexer. Because each switch is only
active when the input line is positive, it is possible to turn on only one of the eight
switches at a time. The demultiplexer IC chosen was a 3-8 decoder/demultiplexer,
the SN74HC138N. The circuit is summarized in Figure 19 below:
72
Figure 19: 33-8 Decoder/Demultiplexer Circuit of SN74HC138N (21
(21)
21)
This IC uses a series of logic gates acting in the matter of a three input, eight
output decoder. The selected output has a low value, while the other outputs remain
high. The values that select the channel are entered as address, which is received
from the digital output lines of the microcontroller. The output selection from each
input line combination is shown in Table 12 below:
73
Table 12: Demultiplexer Outputs for all Addresses (21)
(21)
Because all of the lines are high except for the selected channel, each of the outputs
is inverted using an eight channel buffer/inverter circuit. This makes the input line of
the selected channel high while leaving all of the others at the low value, allowing for
only one channel to be active.
2.3.2.5)) Power Supply
2.3.2.5
Four separate voltages are required to power the device, +5V, -5V, +15V, and
-15V. All of these voltages are created by utilizing the -6V available at the request to
send line (RTS) of the RS232 port. The -5V is created by a -4.7 volt zener diode
regulator. This output is converted to +5V by a MAX860 charge pump DC to DC
voltage converter and inverter, and a combination of diodes and capacitors. The
+15V and -15V supply are created in the same manner, but with a MAX864 dual
output converter.
74
A charge pump is a device that uses capacitors rather than inductors to store
or transfer energy. (24-25) An integrated circuit charge pump uses internal analog
switches and diodes to charge and discharge the capacitors at the proper times as
shown in Figure 20 below:
Figure 20: MAX860MAX860-864 Charge Pump Circuit (25)
(25)
The oscillator portion of this circuit can be applied from an external clock
source or from an internal oscillator. The charge pump is able to double and then
invert the voltage to give a +10 volt output from one pin and -10 V from another. In
order to raise the voltage to +/-15V an additional, discrete, capacitor and diode
network similar to the internal components of the MAX864 is added.
75
By using this theory all four voltages can be obtained from just the RS232
port. The current drawn by the +/-5V circuits is less than 30mA and for +/-15V is less
than 20mA when fully loaded in order to stay within the limitations of the integrated
circuits and the RS232 itself.
2.3.2.6)) USART Interface
2.3.2.6
The
USART
interface
allows
for
asynchronous
or
synchronous
communication from the microcontroller to a computer. This type of data
transmission operates on the RS232 standard with positive voltages of +3 to +25
volts and negative voltages of between -3 to -25 volts. Data is sent in 5-8 bit frames
with a start bit to initiate data transfer, a stop bit to end data transfer, and a parity bit
to provide for error checking. (35) In this design, commands are sent from Matlab
through the serial port to a GCC program that is opened in Windows HyperTerminal.
The GCC program is then able to constantly update commands and registers in the
Butterfly by sending information across the USART interface. (31, 36) This can only
be done after an initial program is loaded by AVRStudio to allow this communication.
The communication between the computer and the Butterfly is performed with a DB9
serial cable. Three pins are used, RxD to receive commands from the computer,
TxD to send information to be displayed on the computer, and a circuit ground
between the two devices.
76
3) Materials and Methods
3.1) Microcontroller Overview
The Atmega169 microcontroller was used to perform most of the control of
the neurophysiologic pulse generator using commands from a GCC program. The
pulses were created with the eight bit timer, Timer0, and the output became
available at the timer output compare pin. The amplitude was controlled using the
SPI interface as described in the previous design. The microcontroller programmed
the analog switches and demultiplexer using five digital I/O ports from PORTB and
PORTD.
Finally, the computer communicated with the microcontroller using an
USART interface, available as a peripheral device on the Butterfly. This allows
commands to be sent and information to be received from AVR Studio or Windows
HyperTerminal. An overview of the AVR Butterfly is shown in Figure 21 below:
77
Figure 21:
21: An Overview of the AVR Butterfly (36)
(36)
3.1.1) PORTB and PORTD
To simplify the design of the Butterfly only two of the ports were easily accessible,
PORTB and PORTD. This reduces the amount of pins that can be utilized for digital
I/O to 16. The first three pins of PORTB, PB0, PB1, and PB2, function as the SPI
interface. Pins PB3, PB5 and PB6 are used to control the address lines of the
demultiplexer. PB4, the output compare pin of Timer0, generates the square wave
pulse, or for the sine wave the x100 timer source for the MAX292 filter IC. Pin PD4
is used to provide the input to the WR line of the analog switches and has a constant
value of 0. Pin PD7 is used for the RS line of the analog switches and has a
constant value of 1. Pins PD5 and PD6 are used for IN0 and IN1 of the analog
switches for the wavetype selection circuit.
78
3.1.2)
3.1.2) PORT
PORT Registers
There are three registers that control the actions of the PORT pins, DDRn,
PORTn, and PINn, where the n stands for the port A-F. Each of the three registers is
identical between ports when used as a standard digital input/output. When an
alternate function of a port pin is used, DDRn registers values are still utilized, but
the registers of that function control the pin. The DDRn, or data direction register,
determines whether the pin functions as an input or output. When the register bit is
set to one the pin is used as an output, and when the value is set to zero the pin is
used as an input. When the data direction is set to input, the PORT and PIN
registers can be read but cannot be written to. However when set as outputs, either
reading or writing of the pins is possible.
The PORT register is used to write a value to a particular pin or group of pins
when the DDR register allows output. The PIN register can also be used to write or
read data directly, but it is most often controlled by the actions of the PORT register.
When a PORT value is set to one, a high of 5V can be seen on that pin, and the
same bit number in the pin register is set. When a value of zero is written, the output
is cleared along with the pin register. If the data direction is set as an input, and a
write is attempted, a pull up resistor on the corresponding pin is activated and
79
remains so until a low value is written. This action prevents damage to the port
caused by multiple values appearing at the pin.
3.2) Waveform Generation Circuit
The waveform generation circuit utilizes Timer0 of the microcontroller for the
square and sine wave circuits. The square wave circuit uses software timing so that
the full range of timing is available and so that the on and off times do not have to be
identical. The fastest frequency available using software timing is 10 kHz, while the
slowest frequency available is 0.1 Hz. The sine wave circuit requires hardware
timing because the MAX292 Bessel filter requires two waveforms. One waveform is
the original frequency and one waveform must be exactly 100 times greater than the
original. In order for the maximum frequency of 10 kHz to be possible the frequency
divider requires a value of 1 MHz, which can only be generated with hardware
timing. This method also allows the lowest frequencies down to 1Hz to be
generated, because the slowest time from needed from the timer is 10 ms, well
within the range of the timer.
3.2.1)
3.2.1) Timer/Counter Overview
Timer0 is considered to be the most general of the timer/counters because it
functions only as an eight bit frequency generator, single compare unit counter, or
80
external event counter. Timer1 and Timer2 each have the ability to perform these
functions but have additional abilities as well. Timer1 can function as one sixteen bit
or two separate eight bit counters. In addition it can be programmed as a nine or ten
bit counter in both PWM and fast PWM modes, and in PWM mode it can be
programmed to achieve both frequency and phase correction. (19) Timer2 can be
programmed asynchronously, allowing the user to supply a 32 kHz crystal oscillator
independent of the internal clock. This is most often used as a real time clock
generator because it is easily scaled to produce accurate 1 second pulses. With
interrupt control this can then be programmed to minute or hour counters. (19, 36)
3.2.2) Timer/Counter
Timer/Counter Registers
For this application Timer0 was used exclusively, because only a standard 8
bit timer/counter was needed. The five registers needed to program this timer are
output compare (OCR0A), timer/counter value (TCNT0A), timer control (TCCR0A),
timer interrupt mask register (TIMSK0) and timer interrupt flag register (TIFR0). The
OCR0A register, stores the value that the timer counts to when programmed to
count to a MAX value. This is an eight bit register, allowing 256 different choices,
numbered 0 to 255. The maximum frequency that can be achieved without a
prescaler is 1 MhZ, or Fclk/2, while the minimum frequency when the clock is
prescaled by 1024 is 3.80 Hz. This resolution gives approximately a 0.1 ms time
81
increase per register value, enough resolution for this application. When a frequency
is known, to find the OCR0A value that should be loaded along with its prescaler the
formula below is used.
OCR0Avalue= fclk/(2*prescaler*fout)
It is important to note that many values end in decimal values and are rounded, but
because of the high accuracy of this device the resolution is kept. The complete
table for all values is found in the appendix.
The TCNT0A register keeps a record of the amount of clock cycles counted,
scaled by the clock prescaler. This value can be read or written to, forcing the
counter to start at that value. In this application, TCNT0A is always set to 0 and
continues to count to the value stored in OCR0A.
The TCCR0A register is used to control the parameters and applications of
Timer0. A summary of the eight bits in this register is shown in Table 13 below:
82
BIT
NUMBER
7
6
BIT NAME
FOC0A
WGM00
5
COM0A1
Works with COM0A0 to control output compare pin
4
3
2
1
0
COM0A0
WGM01
CS02
CS01
CS00
Works with COM0A1 to control output compare pin
Works with WGM00 to set timer mode
Selects Prescale value with CS01 and CS00
Selects Prescale value with CS00 and CS02
Selects Prescale value with CS01 and CS02
FUNCTION
Forces an immediate compare match
Works with WGM01 to set timer mode
Table 13: Overview of TCCR0A Bits (19)
The WGM00 and WGM01 control the sequence of the counter, the type of
counter being used and the maximum counter value. All four modes are made
available by setting or clearing these two bits in the manner detailed in Table 14
below:
Mode
0
1
2
3
WGM00
0
0
1
1
WGM01
0
1
0
1
Mode of Operation
Normal
PWM-Phase Correct
Clear Timer on Compare
Fast PWM
Table 14: Bit Values Setting Modes of Operation (19)
The CTC timing mode is used for all timing functions in this application. COM0A0
and COM0A1 control the behavior of the output compare pin when hardware timing
83
is used. When CTC mode is used the pin operates in the manner shown in Table 15
below:
COM0A0
0
0
1
1
COM0A0
0
1
0
1
Description
Output Compare Disconnected
Toggles On Compare Match
Clear on Compare Match
Set on Compare Match
Table 15:
15: Control of Compare Output PB4 (19)
The final three bits, CS00, CS01, and CS02, and are used to control the
prescaling of the input clock. In CTC mode the fastest timing is available with a
maximum value of the oscillator frequency divided by 2. A summary of the bit
settings, prescale settings, and frequency settings is shown in Table 16 below:
CS00
0
0
0
0
1
1
1
1
CS01
0
0
1
1
0
0
1
1
CS02
0
1
0
1
0
1
0
1
Description
No clock Source
No prescaling
Divide by 8
Divide by 64
Divide by 256
Divide by 1024
External Clock Source/Rising Edge
External Clock Source/Falling Edge
Table 16: Clock Prescale Settings (19)
The TIMSK0 interrupt mask register enables the compare and overflow
interrupts. In order for any interrupts to be executed, the global interrupt register
84
must also be set using the sei() command in GCC. (35) Bit 1, the OCIE0A bit,
enables the compare interrupt, which is then set each time the count in the TCNT0
register matches the value in the OCR0A register. When Bit 0, the TOIE0 bit is set,
the timer overflow interrupt is enabled, and is set each time the counter overflows, or
reaches value 0xFF.
The final timer/counter register is the TIFR0, or timer interrupt flag register.
The two bits in this register are used as flags to control program flow. When a flag is
set by an interrupt, it can execute another section of the program without holding up
the actions of the interrupt. This method is used when multiple actions need to be
carried out during one interrupt, to prevent the interrupt from overrunning itself. Bit 1,
OCF0A is used to set a flag when a compare interrupt occurs and Bit 0, TOV0 is set
when the overflow compare occurs.
3.2.3)
3.2.3) Initial Waveform Generation
The initial waveform differs depending on whether a sine or square wave is
required. When a square wave is selected the program outputs the pulse without
any modifications to the on or off time. The user inputs the amount of time that the
pulse is high and low into the GUI, allowing the interpulse interval to be greater than,
the same as, or less than the high pulse time. When a sine wave is needed, the
initial waveform is generated at a value 100 times the required frequency at the
85
output. The on and off time are the same because the output is generated using the
hardware timer. Both applications allow for an initial delay before the pulse is
generated and for a finite number of pulses to be specified.
The two different types of waveform require some difference in the way that
the registers are programmed. A summary of the register contents in both cases is
shown in Table 17 below:
Register or Register Bit
WGM00
WGM01
COM0A0
COM0A1
CS00
CS01
CS02
OCR0A
OCIE0A
TOIE0
Sine Wave
1
0
1
0
0
variable
variable
variable
1
0
Square Wave
1
0
0
0
0
0
1
0
1
0
Table 17: Comparison of
of Register and Register Bits for Sine and Square Wave
Circuits
In the square wave application the timing is controlled by the software and the
COM0A1 and COM0A0 bits are set to 0 so that the hardware timer is disabled. This
action allows for long on and off times and for the interpulse interval to be variable.
The output pulse is clear timer on compare so that the highest frequencies possible
can be obtained. The OCR0A is set to 0 and the prescale value is always one so
86
that the length of the waveform is based on the amount of 0.1 ms iterations that
occur in the software loop.
For the sine wave, the output pulse toggles on each compare, allowing for up
to a 1MHz frequency to be generated to create the 10 kHz signal. The timer
prescaler varies depending on the pulse lengths needed and is either divided by 1,
8, or 64 times. For both circuits an interrupt is generated when the values in the
TCNT and OCR0A registers match, meaning that the signal interrupt, OCIE0A bit is
set. Neither of the timer interrupt flags were needed in this application, and were
kept at values of 0.
3.2.4)
3.2.4) Program for Waveform Generation
The program for developing the output waveform is different for the sine and
square wave circuits. The square wave circuit takes into account parameters for the
initial delay, on and off time, and the number of cycles required, while the on and off
times are the same in the sine wave circuit. The values are the same in the sine
wave circuit because the frequency divider forces any duty cycle between 20 and 80
percent to 50 percent, meaning the on and off time is the same regardless. The
square wave circuit does not use the frequency divider, so on and off time can be
the same or can vary.
87
The pulse generation is done using both Matlab and C programming. Matlab
accepts the user input and develops variables for the parameters that the C program
can use to program its registers and generate the waveform. The Matlab program
works as shown in Figure 22 below:
Start
Get timing and
wavetype info
from user
Sine
Square
Sine or
Square?
Wave?
Adjust time to
microseconds
Adjust on and off
times to multiple
of 0.1ms
Compare
Time value
No
Set prescale to1
OCR0A to 0
Yes
> 0.256
ms
> 2.05ms
Prescale 1
Find OCR0A
value
No
Yes
Prescale 8
Find OCR0A
value
Prescale 64
Find OCR0A
value
Send timing register values
Initial delay and
Number of cycles to C
Figure 22:
22: Overview
Overview of Matlab Section of Timing Generation
For the sine wave circuit the on and off time values were adjusted from
milliseconds to microseconds by dividing the input by 100,000. The program found
88
the appropriate prescale and count values for the TCCR0A and OCR0A registers.
The prescale value was decided upon by applying three conditionals with the cut off
times for each prescale being the point were the OCR0A count reached. The time
values and their corresponding count and prescale values are included in the
appendix. The prescale and count values are sent to the C program along with the
initial delay and number of cycles, which are kept at their original integer values.
If the square wave circuit was needed, the count and prescale values were
constant because software timing was used. The count value of 0 and prescale of 1
allowed the maximum time of 0.1ms to be generated. The on and off times are
multiplied by 10 so that they are in terms of 0.1 ms instead of 1. The on and off times
are then sent to the C program, along with the number of cycles and the initial delay.
The C portion of the waveform generation is complicated and requires several
functions and an interrupt. An overview of the programming for this process is shown
in Figure 23 below:
89
Get info
from Matlab
Square
Sine
Sine or
Square
Wave?
Goto
SquarePulseInit
Goto
SinePulseIni
t
Set OCR0A
and Prescale
to Matlab
found values
Set OCR0A to
0 and
Prescale to 1
Set
other
registers
Set
other
registers
Start
timer
Start
timer
Set
Interrupt
Set
Interrupt
Yes
No
Turn
pulse
off
Pulse
On
Yes
Numbe
r of
Cycles
Reach
ed?
No
Yes
Pulse
Off
No
PulseStop
Function
Disables Timer
Yes
Turn
pulse
on
Numbe
r of
Cycles
Reache
Figure 23:
23: Overview of C Section of Timing Generation
90
In the main function of the program the initial delay before the waveform
begins was always executed first to prevent conflicts with the timer. A delay loop
was used that generated delays up to 50 milliseconds, and if a longer time was
needed then multiple 50ms loops were ran. The amount of times the loop processed
was determined by the division of the overall time by 50ms with the remaining time
occurring in the final loop. At this point the pulse generation control was separated
into sine and square wave sections.
When the sine wave circuit was chosen the function SquarePulseInit was
called to set the initial register contents in TCCR0A, TIMSK0, and OCR0A. The timer
began and the interrupt was triggered when the count in OCR0A is reached. The
interrupt was also different for the square and sine wave generations. In this case a
running counter incremented and the pulse was turned on or off by the hardware.
This process continued until the number of pulses requested was reached. The
function PulseStop was called to disable the timing circuit and interrupts.
When the software timing was generated for the square wave the initial
function called was SquarePulseInit. This loaded the OCR0A register with a value of
0 and the prescaler bits of TCCR0A with a value of 1. The timer began and the
counter nearly instantaneously triggered the interrupt. The interrupt selected the
square wave section and the pulse was turned on for the amount of time requested
by a loop that increased an iteration value every 0.1 ms until reaching the time
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requested. (32) The pulse was shut off by another loop that worked identically but
controlled the off time. This process repeated until all of the pulses were output, and
then the function PulseStop was called to clear the timer and disable the interrupts.
The complete code for all of the functions presented is found in the appendix.
3.3) Wavetype Selection Circuit
The wavetype selection circuit consisted of three separate components. First
a DG425 analog switch created two separate circuits for the sine and square waves.
After being selected, the square wave was applied immediately to the amplitude
circuit. The sine wave when chosen was sent to the SN74LS390 frequency divider,
to recover the initial frequency. The original and the divided waveform were applied
to the MAX292 filter to create the sine wave. The output from the MAX292 was
applied to the amplitude circuit. An overview of the wavetype selection circuit is
shown in Figure 24 below:
Square Wave
Micro
controller
Output
DG425
Switch
SN74HC390
Frequency
Divider
MAX292
Filter
Sine Wave
Figure 24:
24: Overview of Wavetype Selection Circuit
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Amplitude
Control
Circuit
3.3.1) DG425 Analog Switch
The timer output from the microcontroller was output from PB4 whether
hardware or software timing is used, even though the programming was different.
The signal was applied to an analog switch, DG425 which directed the waveform to
the hardware of the square or sine wave circuit. An overview of the pin out of the
DG425 is shown in Figure 25 below:
Figure
Figure 25:
25: Pin Out of DG425 Analog Switch (22)
(22)
The DG425 DPST switch contains four switches, with two sets being controlled by
each input. The switch inputs are labeled S1-S4 and the outputs are D1-D4. The
DG425 can be used as a latching circuit so it contains WR and RS pins normally
found on flip flop circuits. These values are kept constant and the channel is
selected by changing the values of the two input pins. Selecting IN1 activates
switches 1 and 3 and selecting IN2 activates switches 2 and 4. The DG425 is
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powered by a positive and negative 15 volt supply, and a 5V power supply, VL that is
used to power the logic circuit when the device is used as a latch. (22)
The DG425 received four signals from the PORTB of the microcontroller to
set the WR, RS, IN0 and IN1 pins. PB3 and PB5 control the WR and RS constant
signals and PB6 and PB7 are used to control IN0 and IN1 respectively. The user
selects whether a sine or square wave is needed, with IN0 turning on the sine wave
circuit and IN1 turning on the square wave circuit.
To program the DG425 both Matlab and C were required. In Matlab the
wavetype was set to an integer value of 1 for a sine wave or 2 for a square wave.
This value was sent to the C program where it was loaded into the WavetypeSelect
function. The wavetype value was compared to two conditionals to test if the sine or
square wave circuit should be activated. In the sine wave circuit, PB5 (RS) and PB6
were set high, while PB3 (WR) and PB7 were set low. In the square wave circuit
PB5 and PB3 were held constant, but PB6 was set to a low and PB7 was set to a
high.
3.3.2)
3.3.2) SN74HC390 Frequency Divider
The SN74HC390 received an input when the sine wave circuit was selected.
An overview of the pin out of the IC is shown in Figure 26 below:
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Figure 26:
26: Pin Out of SN74HC390
SN74HC390 Frequency Divider (26)
26)
The four inputs are known as clock input pins, and there are two each for the
counters. Clock 1A and 2A are utilized by the divide by two circuits and Clock 1B
and 2B by the divide by five circuits. The divide by two circuits are internally
connected to one flip flop, while the divide by five circuits use three flip flops and
gating circuitry. There are four outputs for each of the two counters corresponding to
each of the outputs of the flip flops. Pins 3 and 13, 1QA and 2QA, are the outputs of
the divide by two counter, and are either low or high for one half of the count
frequency. 1QB-1QD and 2QB-2QD are the various outputs for the divide by 5
counters. The value for each count output is summarized in Table 18 below:
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Table 18: Output Values for Each Count Value (26)
(26)
The table shows that output QB is a divide by two counter, QC is a divide by four
counter and QD functions as the divide by 5 counter.
Pins 2 and 14 are used to clear the counters by setting the clear pin of the flip
flops in each circuit. A low to high pulse causes this condition, which can be cleared
by returning this pin to a low value. These pins can be used to further control the
frequency of the output or to guarantee that no frequency leakage occurs. These two
pins are tied to ground for the duration of this application.
The filter circuit required two waveforms in a 100:1 ratio, which can be formed
from the divide-by-two and divide-by-five counters. (29-30) To form the second
waveform, the actual output frequency, the original pulse was applied first to the
input of a divide-by-five, and then a divide-by-two counter. This output was applied
to the other divide-by-five counter and divide-by-two counter achieving a divide-by100 counter. This procedure is summarized in the Figure 27 below:
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ORIGINAL
INPUT
DIVIDED BY
100 OUTPUT
Figure 27:
27: The Divide by 100 Counter (26)
(26)
The maximum input frequency that can be generated by the microcontroller
timer was 1 MHz, meaning that the maximum frequency from the divide by 100
circuit was 10 kHz. This was the maximum frequency required by this application,
and frequencies down to 1 Hz can be created with an input of 100Hz, which was well
within range of the timer and frequency divider.
3.3.3
3.3.3) MAX292 Bessel Filter
The original and frequency divided pulse are sent to the MAX292 eighth order
Bessel filter to be converted into a sine wave. An overview of the integrated circuit is
shown in Figure 28 below:
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Figure 28:
28: MAX292 Bessel Filter (23)
The MAX292 is powered by a positive and negative 5 volt supply for the filter
and the optional, internal op-amp circuit. This was unused in this application and the
op-amp pins, OP- and OP+ pins were shorted together. Pin 1 of the MAX292
received the CLK input, the undivided input from the analog switch. The IN input,
located at pin 8, received the frequency divided waveform, which became the output
sinusoid frequency. The inputs were kept at a 100:1 ratio allowing the sinusoid
output to be clean and available at pin 5. (33) If the ratio of the two frequencies
increased above 100 the output voltage remained the same but the output returned
to a square wave. As the ratio decreased, the output voltage decreased and lost its
sinusoidal characteristics.
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3.4) Amplitude Control Circuit
The amplitude control circuit consisted of the three different parts, an op-amp
to raise the amplitude to the maximum level of 10 volts, a PGA to scale the voltage
to the user selected value, and finally another op-amp to reverse the polarity when
necessary. For the amplitude increase the gain of a LM741N operational amplifier
was set to 2 using the non-inverting input. The circuit used is summarized in Figure
28 below:
Figure 28:
28: OpOp-Amp Circuit to Generate Maximum Input
The resistance values of 10 k Ω were selected because the programmable
gain amplifier required very low current to function properly (1-5mA). The op-amp is
powered by a positive and negative 15 volt supply and uses a floating ground in this
circuit. There were two op-amps in the first part of the amplitude control circuit, one
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each for the sine and square waves. The sine wave op-amp used the signal from the
output pin of the MAX292, while the square wave op-amp used the signal from the
D2 pin of the analog switching circuit. Only one of the two op-amps was used with
each pulse generation, but to isolate the circuits, this practice was used. The 10 volt
output from the op-amp was sent to one channel of the programmable gain amplifier.
3.4.1)
3.4.1) MAX532 Programmable Gain Ampl
Amplifier
The MAX532 programmable gain amplifier allows the user to control the
voltage between -10 and +10 volts with 12 bit resolution. There are two separate,
isolated MDAC circuits that can be programmed simultaneously or separately. In this
case they are programmed separately with one amplifier used for each of the sine
and square wave circuits. The MAX532 is a 16 pin integrated circuit that contains
four circuit types: two amplifier circuits, a serial data input circuit, a serial data output
circuit, and a power supply circuit. An overview of the MAX532 is shown in Figure 29
below:
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Figure 29:
29: Overview of MAX532 Programmable Gain Amplifier (27)
(27)
MDAC1 was used to adjust the amplitude of the square wave circuit while
MDAC2 was used to adjust the amplitude of the sine wave circuit. Pin 2 and pin 7
provided the input signal to the corresponding amplifier, and the gain control
feedback resistor was set internally by the digital to analog converter. Pins 1 and 8
acted as the feedback resistor for the amplifiers and were shorted to their respective
outputs giving a standard inverting op-amp. Because this is an inverting amplifier,
the signal must be readjusted to the proper value using the bi-polar configuration of
the PGA, and another op-amp to correct the voltage.
The MAX532 was controlled using the SPI interface of to the microcontroller.
This IC can use either a 3 or 4 wire interface, but to work properly with the Butterfly 3
wire SPI was used. The four pins in the serial data input circuit are the clock input
pin (SCLK), the data input pin (DIN), the chip select (CS) pin and the asynchronous
load DAC input (LDAC) pin. The LDAC pin is the extra input used for the 4 wire SPI
101
and must be tied to ground during the 3 wire operation. In order to transfer data, the
CS pin was taken low in the same manner as the FSYNC pin of the AD5930. This
allowed data to be clocked in on the DIN pin during the rising edge of a clock cycle
on the SCLK pin.
The PGA uses a separate 12 bit register for each of the DAC channels, and
both channels, even if inactive must be written to with each data write. The SPI data
is transmitted in eight bit words, so three writes were performed to program the
device. The first DAC was written to MSB first, using the 8 bits of the first write and
the first four of the second write. The second DAC was written to with the 4 MSB’s in
the second write and the eight bits presented in the third write. After the third write
was completed the CS pin is taken high and the DAC registers are updated.
Because this is a mixed signal device the MAX532 uses a positive and
negative analog 15 V supply to power the IC and DAC’s. This supply is internally
lowered to 5 volts to supply power for the SPI which is a digital circuit. There are two
analog grounds on the IC for each of the amplifiers and one digital ground for the
SPI circuit. This device did not have the noise issues of the AD5930 because the
digital circuit is internally isolated from the analog and the clock feedthrough is
minimal because an oscillator is not applied.
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To begin the program for the PGA, the amplitude for the waveform was
entered into the program through the Matlab GUI. Matlab then created the values for
the three 12 bit registers as outlined in Figure 30 below:
Amplitude
Given
By User
PGA Register
Position found
Integer to
Binary
Conversion
Sine
Sine or
Square
Wave?
Register 1 and half
of register 2
Loaded with data
Square
Half of register 2
and register 3
Loaded with data
Other half of register 2
and register 3 loaded with
0’s
Register 1 and half of
register 2 loaded with 0’s
Integer Value for Each
Register Found and Sent to
C
Figure 30:
30: Overview
Overview of PGA Register Creation
After the user requested an amplitude the value was converted to a PGA
position value of between 0 and 4095. Because the output had positive and negative
values the bipolar configuration was used, meaning that the negative voltages used
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positions 0 to 2047, and the positive voltages occupied positions 2048 to 4095. The
register position is found using the formula below (27):
position = round(2048 + ((2047 * amplitude) / initialvoltage));
The binary register value was found using an integer to binary converter.
There were three 8 bit registers written to, even though only one output was active
each time. The sine output occupied the entire first register and the first four bits of
the second register, and the square wave output occupied the last four bits of the
second register, and the entire third register. When the sine wave was requested,
the last four bits of register 2 and all of register 3 are filled with zeroes and when a
square wave was requested all of register 1 and the four most significant bits of
register 2 are set to 0. At this point, the value of each of register bit multiplied by 2 to
the register position was summed together in the following manner for the sine
wave, generating an integer value corresponding to the binary word that C can
recognize.
freqval1 = sum((2 .^ (0 : 7)) .* fv(5 : 12));
freqval2 = sum((2 .^ (0 : 7)) .* [fvn(9: 12) fv(1 : 4)]);
freqval3 = sum((2 .^ (0 : 7)) .* fvn(1 : 8));
104
There were two functions in C that allow the data to be transferred from the
SPI interface, SpiInit and SpiSendByte. These two functions were identical to those
written for the AD5930 except that some of the SPCR register values were changed
and three writes were required in the SpiSendByte function. The SPCR register was
adjusted to allow the data to transfer on the rising edge with the clock idling low. The
three data writes occurred at the same pin as used for the AD5930, unlike the
previous design where the PGA was frame selected from PD1.
The SPI data transfer was always the first set of functions executed by the
GCC program, performed before the timers were initialized. This was done so that
the PGA knew the amplitude to set the pulse to before it reached the MDAC input,
and to prevent clock noise from leaking between the SPI and timer ports.
3.4.2)
3.4.2) Output Correction
The output from the PGA was adjusted in amplitude but inverted from the
original signal. In order to restore the voltage to the proper sign the signal was sent
through a bipolar op-amp circuit. This was done by using the internal amplifier as the
first op-amp to adjust the amplitude, and attaching a second op-amp to correct the
polarity. This method is shown in Figure 31 below (27):
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Figure 31:
31: Output Correction Circuit
The gain of the second op-amp was one but the sign of the signal was
adjusted when necessary. The signal was now at the correct amplitude and applied
to the channel selection circuit.
3.5)
.5) Channel Selection Circuit
After the waveform was adjusted to the correct parameters it needed to be
directed to the proper output channel. This device was designed to select between
one of eight channels. The appropriate analog switch was enabled by receiving a
signal on the input pin from the 3 to 8 demultiplexer. The demultiplexer was
addressed from the microcontroller, and selected the appropriate channel by
outputting a low signal. The signal was then inverted by a SN74LS04 inverter to
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provide a high signal to the selected output while sending low signals to the
remaining channels.
3.5.1) SN74HC138N Demultiplexer
The first element of the channel selection circuit was the SN74HC138N
demultiplexer. An overview of the IC is shown in the Figure 32 below:
Figure 32:
32: SN74HC138 Demultiplexer (21)
(21)
The demultiplexer received address signals from the digital output pins of the
microcontroller. The three address lines of the SN74HC138 are pins 1, 2 and 3 and
are given designations of A, B, and C. The three lines act as a binary word between
0 and 7 to tell the IC which output to select. The eight decoded outputs are labeled
Y0-Y7 corresponding with the binary number in the address lines. The voltage of an
inactive pin is always five volts, while an active pin is zero volts. Only one output can
be active at a time, and attempting to tie outputs together can damage the device by
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applying an overvoltage to the internal decoder circuit. The G1A, G2A, and G2B pins
act to enable the demultiplexer. In order for the device to function G1A must have a
high value and G2A and G2B must be low. If any of the three pins has an incorrect,
value the IC is disabled and all of the outputs default to a high value.
The SN74LS04 hex inverter was chosen to switch the polarity of each of the
demultiplexer outputs. An overview of this IC is shown in Figure 33 below:
Figure
Figure 33:
33: SN74LS04 Hex Inverter (20)
(20)
Each inverter simply consists of an input and an output, labeled Yn and An
respectively. Eight channels were required, but there are only six inverters on one
IC, so two devices were used. This interface between the demultiplexer and inverter
is shown in Figure 34 below:
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Figure 34:
34: Demultiplexer/Inverter Connections
3.5.2) Analog Switch Outputs
The final stage of the channel selection circuit was the four dual output analog
switches, giving a total of eight possible outputs. At each of the eight sets of
switches, one of the inputs was from the sine wave circuit and the other was from
the square wave circuit. The two inputs were tied together, but because only one
circuit was active at a time, there was not a signal conflict. Only one of the eight
possible input pins received a high, becoming active, while the other seven
remained low. The output of the switches was sent to the final set of connectors. An
overview of this portion of the circuit is shown in Figure 35 below:
109
Figure 35:
35: Analog Switch and Output Connections
The eight output channels were available to the user in the Matlab GUI. The
channel selected became a corresponding integer value which was sent to the C
program. GCC used the function ChannelSelect to properly address the
demultiplexer, and to provide the constant values for the WR and RS lines of the
analog switches. In this function eight conditionals were used to test the channel
110
value, and when a match was made, the lines PB3, PB5 and PB7 are sent the
proper values. An example of one of the conditionals is shown in Figure 36 below:
if (channel==2)
{
PORTB &= ~(1<<PB3);
PORTB &= ~(1<<PB5);
PORTB |= (1<<PB6);
}
Figure 36:
36: Conditional Setup for Channel Selection
3.6)
.6) Power Supply Circuit
In order for the circuit board to work properly a total of four different power
supplies were needed, +5V, -5V, +15V, and -15V. To prevent the need of a bulky
120V power supply the voltage from the RS232 port of a computer was used. This
was possible because the system did not require a large amount of current, and the
RS232 voltage was approximately -6V, which was easy to manipulate. This power
supply was placed on a separate circuit board and connected along with the ground
plane through a connector. The input to the board was taken from the DB9
connector used to communicate between the microcontroller and computer.
111
3.6.1) -5V Supply
The -5V supply was the easiest to build, requiring only one component, a
1N4732, -4.7 volt zener diode. (28) The zener diode had a -6V value applied from
the RS232 Tx line to its cathode and the anode was tied to the system ground,
allowing for a semi-regulated supply. The -5V supply was required in only one place,
the MAX292 filter integrated circuit.
3.6.2) +5V supply
The +5V supply was derived from the zener diode output and a charge pump
inverter, MAX860 from Maxim. The circuit to perform this is shown in Figure 37
below:
Figure 37:
37: +5V Power Supply Circuit (28)
(28)
112
The MAX860 can either invert the input voltage or double it. This design uses
a doubler configuration in which the normal input-voltage polarity is reversed. The 6V supply was reduced to -4.7V by the 1N4732 zener diode from the -5V circuit. The
IC then doubled the negative VIN into the positive direction, producing a positive
output equal to |VIN|. (28) This was possible because the LV pin was used to enable
low or negative voltages. When the negative voltage was applied to the output pin,
the IC created the +5 volts. VDD, normally the input pin, became the output of the
device. An additional capacitor was applied on the output to further remove any
ripple that may occur.
The auxiliary components of the MAX860 worked as follows: the 1N5817
diode was used to prevent overcurrent conditions from damaging the RS232 port.
The capacitor before the device was used to stabilize the voltage, which can vary
during data transmission. The SHDN pin was used to disable or enable the charge
pump, and the FC pin was used to select the internal frequency that the charge
pump or oscillator should operate at. (24) Because SHDN was grounded the charge
pump was disabled, and the MAX860 used the internal oscillator. The FC pin was
tied to ground setting the internal oscillator to a value of 50 kHz. By running at this
high frequency it was not necessary to use large value flying capacitors (C+ and C-)
to lower the output ripple, and a higher current of 20mA could be utilized.
113
3.6.3) +/+/-15V Supplies
The +15V and -15V were both derived from the +5V supply that was
generated from the MAX860. In this case another voltage doubler and inverter were
used with a series of diodes and capacitors to create a voltage tripler. An overview
of the circuit is shown in Figure 38 below:
Figure 38
38: MAX864 as a Voltage Tripler (34)
(34)
The MAX864 works identically to the MAX860, but it contains two separate
circuits, allowing one to be used as a doubler, and one to be used as a doublerinverter. The MAX864 accepts inputs up to 5.5 volts, so the additional diodes and
capacitors function similarly to half of a charge pump, allowing the voltage to be
increased to the final value. The +5V from the MAX860 was applied to Vin, the input
114
to the charge pump circuit. There are two outputs in this device, V+ and V-, where V+
is the positive charge pump output, and V- is the negative charge pump output.
These two pins have 10 µF output capacitors in order to eliminate ripple before
being applied to the final diode/capacitor network.
The FC0 (pin 8) and FC1 (pin 7) were used to select the frequency of the
charge pump and internal oscillator. (25) When FC0 was set to 1 and FC1 was set to
0 the optimum frequency is 33 kHz, similar to the 50 kHz used for the MAX860. This
allowed for as much synchronization to occur as possible, however, it should be
noted that it did that several seconds upon power application for stabilization to
occur. The SHDN pin acted to enable charge pump, and was connected to the +5V.
Because there were two separate outputs to this device, there were two sets
of flying capacitors. C1+ and C1- function for the non-inverting half of the device,
and C2+ and C2- function for the inverting half. For the MAX864, the frequency set
in FC0 and FC1 also determined the size of capacitor to use. (25) For the frequency
settings used a capacitor value over 2.2 µF was acceptable, so 10 µF capacitors
were used. It was hoped that the higher capacitance would eliminate any further
ripple from the charge pump that may be present because of the different oscillator
frequencies. The final diode/capacitor network increased the non-inverting voltage to
+15 and decreased the inverting voltage to -15 volts. The circuit was the same as is
found internally in the MAX864, but allowed for a higher input voltage.
115
3.7)
.7) Circuit Board Design and Layout
Two circuit boards were developed for this project, one for the power supply
and one for the main signal generation board. The two boards were connected
together by an eight pin connector that sent the +15V, -15V, +5V and -5V to the
main signal board. For the output, eight connectors were used to connect to the
output instrumentation. The signal board was built on a standard breadboard, while
the power supply was built on a perf board.
3.7.1
3.7.1)
7.1) Power Supply Board
The power supply board received its input voltage from the DB9 data
transmission connector through the four pin connector at one end of the board. The
three circuits that generated the four power supplies were separated from each
other, and all required discrete components to be placed around the integrated
circuits. The circuit blocks are shown in Figure 39 and the schematic is shown in
Figure 40 below:
116
Input from
DB9
-5V with
zener diode
+5V with
MAX860
+/-10V with
MAX864
-15V with
diode/capacitor
network
+15V with
diode/capacitor
network
Output to
Signal Board
Figure 39:
39: Layout of Power Supply Board
Figure 40: Schematic of Power Supply Board
117
The two integrated circuits were both surface mount, the MAX860 and
MAX864, and needed to be mounted to the circuit board with DIP adapters. The
MAX860 is an 8 pin SOIC, so it used an 8 pin SOIC-DIP. The MAX864 is a 16 pin
TSSOP and was mounted on a 20 pin TSSOP adapter left over from the AD5930
portion of the design. The board can be seen assembled in Figure 41 below:
Figure 41
41: Photograph of Power Supply Board
3.7.2)
3.7.2) Main Signal Board
The main signal board received the power supplies from an eight pin
connector at one end of the board. The power supplies were connected to different
bus lines on the breadboard. The +15 and -15 V supplies were placed in the middle
118
bus path, the +5 and -5V were placed at one end, and the ground plane was set at
the top. The microcontroller was placed in the left center of the breadboard to create
shorter signal paths, preventing as little noise as possible from reaching the
microcontroller. The IC’s were then laid out in the left and center portions of the
breadboard with the wavetype, amplitude and channel selection circuits kept
together. The layout of the breadboard is shown in Figure 42 and the final schematic
is shown in Figure 43 below:
GND
+5V
-5V
+15V
-15V
Wavetype
Selection
Amplitude
Control
Micro
controller
Channel
Selection
Analog
Switches
Channel
Selection
Demux and
Inverter
Figure 42
42: Breadboard Overview
119
Outputs
Figure 43: Schematic of Main Signal Board
All discrete components were placed as closely as possible to their integrated
circuits to allow for easy troubleshooting and to keep signal paths short. The
assembled board is shown in the Figure 44 below:
120
Figure 44:
44: Photograph of Assembled Breadboard
3.7.3)
3.7.3) Wiring Considerations
Because a perf board was used in the building of the power supply board,
wiring required great care. The circuits were wired from solder point to solder point
using 32AWG, single conductor wire. This wire was hard to work with, and was
fragile to touch at times, but overall gave the best results for this application. The
final ground and power supply paths were wired using 24 AWG wire to prevent noise
from entering any of these planes. The connectors were wired between boards with
the same 24 AWG wire. The breadboard used standard 28 AWG jumper wires, and
121
the primary consideration was to keep the wires as short as possible to allow for
easy troubleshooting and to keep wires from breaking.
3.7.4
3.7.4)
7.4) Connector Considerations
The connectors for the circuit board were Molex 24AWG fully insulated
headers and sockets. They were chosen because of the complete isolation and ease
of soldering and wiring, and because no crimping was needed. The connectors had
plastic insulation between the contacts and around the exterior so that shorting lines
together was impossible. The headers had a back plane half the size of the
connector itself, allowing for the connection to be tight and for it to not break very
easily.
3.8)
.8) Matlab Interface Design
In order to program the microcontroller the software, GCC must be used, but
this type of software is not user friendly when developing GUI interfaces or for doing
high level mathematical calculations. Because of this, the C program loaded into the
microcontroller ran concurrently with a Matlab interface, allowing the user to enter
parameters and perform the conversions to simple variables in GCC. This allowed
for the quickest and most efficient programming of the microcontroller. The Matlab
Interface consisted of a GUI that the user sees when they load the program, a
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section that calculates the variables after the user presses the start button, and a
stop button which quits the program and shuts down the microcontroller.
3.8.1
3.8.1)
.1) Program Description
Before Matlab is opened a .hex file of the entire program is programmed into
the microcontroller using AVR Studio. This installation is required in order for the
user to be able to manipulate the parameters in through Matlab and HyperTerminal.
The Matlab portion of the program began by opening the serial connection and
clearing any values that may have been stored there. The user was then able to
enter values into the GUI, and the values were sent to Matlab as a series of
variables when the start button was pressed. The values were converted from
strings to numbers and the calculations needed for each section were done. The
final values were sent to the C program via the RS232 port. To complete the
program, the serial interface was closed, so that it does not interfere with the control
of the microcontroller. The interface remained open and new data could be entered
after the pulse generation was complete.
The GUI interface was a simple design that first had the user select a channel
for output, and then control the parameters of the pulse train. An overview of the
interface is shown in Figure 45 below:
123
Figure
Figure 45:
45: Overview of GUI Interface
The channel selection consisted of 8 choices, and when selected another
menu opened, allowing the output pulse parameters to be controlled. The wavetype
was selected from two choices of a pull down menu, and the values for the on time,
off time, initial delay, number of cycles, and amplitude were entered into appropriate
edit fields. These values were stored in memory as strings until the start button was
pushed. When this occurred, a callback was initiated were the values for the
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channel, wavetype, PGA registers, and timer registers were found. The details for
the conversions were described in each of the proper sections.
After the calculations were made in Matlab, the values were sent to C using
HyperTerminal with the RS232 port of the PC. The values were converted back into
strings, so that they could be sent as ASCII characters, the preferred method of data
transfer. The data was sent across the port using the sprintf command. The first
character in the sequence was used to identify which button had been pressed, start
or stop, and the next set of characters were the variables needed by the C program.
The part of the program that performs this process is shown in Figure 46 below:
serial_string = sprintf('a %d %d %d %d %d %d %d %d %d %d %d', count, prescaler, ...
npulses, npulses2, delayint, wavetype, channel, delay, freqval1, freqval2, freqval3);
fprintf(user_data.h_serial, serial_string);
Figure 46:
46: Serial Transfer Code
When the stop button was pushed a different character was sent to the C
program, telling the program to stop the actions of the microcontroller. After either
character had been sent the Matlab program closed the serial port, allowing the C
program to be able to communicate with the microcontroller without interference
from Matlab. This interface however stayed open, and could be used to enter the
next set of data when the pulse train ended.
125
3.9
3.9) PC Control of the Microcontroller
As previously mentioned, the microcontroller can be programmed through
AVR Studio. While this method accurately programs the microcontroller, it is not user
friendly to make changes between pulse generations. In order to do this a session of
HyperTerminal communicated between Matlab and GCC and then GCC and the
microcontroller. The original program was loaded into the microcontroller with AVR
Studio containing commands to allow for communication with HyperTerminal. For
both sets of transfers the USART interface was enabled, the transfer rates and port
connections coordinated between the two programs, and the microcontroller was
turned on and made ready to communicate. (31)
3.9
3.9.1) USART Registers
There were a total of six programmable registers that are used for controlling
the USART. These include three control registers (UCSRA, UCSRB, and UCSRC),
two baud rate setting registers (UBBRH, UBBRL) and one data register (UDR). The
three control registers are each eight bits in length and control the operation of the
USART interface, monitor the sending and receiving of information, and verify that
the data is transferred properly. A summary of the bits of the three control registers
is shown in Table 19 below:
126
Register
Bit
RXC
TXC
UDRE
FE
DOR
UPE
U2X
MPCM
RXCIE
TXCIE
UDRIE
RXEN
TXEN
UCSZ2
RXB8
TXB8
Control
Register
UCSRA
UCSRA
UCSRA
UCSRA
UCSRA
UCSRA
UCSRA
UCSRA
UCSRB
UCSRB
UCSRB
UCSRB
UCSRB
UCSRB
UCSRB
UCSRB
Bit
Number
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
UMSEL
UPM1
UPM0
USBS
UCSZ1
UCSZ0
UCPOL
UCSRC
UCSRC
UCSRC
UCSRC
UCSRC
UCSRC
UCSRC
6
5
4
3
2
1
0
Function
Sets Receive Complete Interrupt
Sets Transmit Complete Interrupt
Sets Empty Register Interrupt
Frame Error
Data Overrun Error
Parity Error
Doubles Transmission Speed
Enables Multiple Communications
Enables Receive Complete Interrupt
Enables Transmit Complete Interrupt
Enables Empty Register Interrupt
Enables UART Receiver
Enables UART Transmitter
Sets Character Size with UCSZ1 and UCSZ0
Holds 9th Bit in Nine Bit Reception
Holds 9th Bit in Nine Bit Transmission
Sets Synchronous or Asynchronous
Transmission
Enables and Sets Parity Type with UPM0
Enables and Sets Parity Type with UPM1
Stop Bit Enable
Sets Character Size with UCSZ2 and UCSZ0
Sets Character Size with UCSZ1 and UCSZ2
Sets Clock Polarity of Transmission
Table 19: Overview of USART Control Bits
Bits (19)
The first two bits of the UCSRA register, RXC and TXC are used as flags to
show when data has been received or sent. The RXC flag is set when there is
unread data in the receive buffer and is cleared when the buffer is empty. This can
be used to set a receive complete interrupt when enabled. The TXC flag is set when
the entire frame of the transfer shift register has been sent and there is no data
remaining. This flag is automatically cleared when a transfer complete interrupt is
127
executed. This is done when the transfer complete interrupt is enabled. The UDRE
bit sets a flag to indicate that transfer buffer is ready to receive new data from the
microcontroller. This is a read only bit, and is cleared when data is seen in the buffer
or is set before the transfer begins. This flag can be used to generate a data register
empty interrupt (UDRIE) when it is enabled along with global interrupts. (19)
The next three bits are all read only, and are used to allow the user to know
when an error has been encountered in the data transfer. The frame error (FE) bit is
set when the first stop bit of the next character in the receive bit is zero. The DOR bit
is set when a data overrun condition occurs, which occurs when the receive buffer is
full and a new character is waiting to be shifted into the register and a start bit is
detected. The final bit, UPE, is set when a parity error is received when parity
checking is enabled. (19) All three of these bits can be cleared after the UDR
register is read and no other error conditions occur.
The U2x bit is used to double the speed of the transmission during
asynchronous operation. This bit must be set to 0 during synchronous transmission
or if standard operation is required. This bit effectively cuts in half the baud rate
divider for data transmission, allowing for maximum speeds to be achieved. The final
bit of UCSRA is the multi-processor communication mode bit, or MPCM. When this
bit is set to a value of one all of the incoming frames received by the USART that do
not contain address information will be ignored. This reduces the number of frames
128
handled by the CPU, increasing the transmission speed. This is normally used when
multiple devices share the communication line so that the speed of data reception is
not lost. This process does not work when data is transmitted, because only one
source is transmitting the data.
The first three bits of the UCSRB register are used to enable interrupts for
various conditions. RXCIE enables the receive complete interrupt which is generated
when the RXC flag is set and TXCIE enables the transmit complete interrupt when
the TXC flag is set. The UDRIE bit enables the data register empty interrupt
generated by setting the UDRE flag. All of this bits are irrelevant unless global
interrupts are enabled using the sei() command in the main function.
The bits RXEN and TXEN are used to enable the receive and transmit
functions of the USART respectively. These must be set to 1 before communication
in either direction can be achieved. Also, these two bits cannot be set while a data
transmission is occurring and the bits will be ignored until the data has finished its
transfer. The UCSZ2 bit of UCSRB and the UCSZ1 and UCSZ0 bits are used to set
the size of the character in the data transmission. The size of the character can vary
between 5 and 9 bits with the bits set in the manner shown in Table 20 below:
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UCSZ2
0
0
0
0
1
UCSZ1
0
0
1
1
1
UCSZ0
0
1
0
1
1
Character Length
5 bit
6 bit
7 bit
8 bit
9 bit
Table 20: Character
Character Length as Set by UCSZ Bits (19)
RXB8 and TXB8 are the final two bits of the UCSRB register and are used in
data transmissions that are nine bits in length. These two positions hold the ninth bit
for the data receive or data transmit buffer. When these are utilized it is important to
program them so that the data is transferred along with the UDR register, because
no further transmission can occur until this bit has been sent or received.
The first bit of the UCSRC register determines the mode of operation of the
USART. When this bit is set to one synchronous operation occurs, allowing
simultaneous bidirectional communication, and when this bit is set to zero the data
transmission is either sent or received although events can occur sequentially. The
UPM1 and UPM0 bits enable and set the type of parity checking used in the USART.
When enabled the transmitter automatically generates and sends the parity of the
data transmission bits for each frame. The receiver generates a parity value for
incoming data and compares it to the setting in UPM0. If a mismatch has occurred
than the UPE flag in UCSRA is set until the data register has been cleared. When
both bits contain a value of zero the parity checker is disabled. With UPM1 is set to
130
one and UPM0 is set to zero the parity checker is enabled and set for even parity.
When UPM1 and UPM0 are both one the parity checker is enabled and the parity is
set to odd.
The USBS bit selects the number of stop bits inserted by the transmitter.
When set to 0, 1 stop bit is set and when set to 1, 2 stop bits are set. This value is
not used for the receiver function of the USART. The final bit of the UCSRC register
is the UCPOL, or USART clock polarity pin. This pin is only active in synchronous
mode, and must be written to 0 in asynchronous mode. When this bit is set to 0 the
transmitted data is changed on the rising clock edge and the received data is
changed on the falling clock edge. When this bit is set to 1 the transmitted data is
changed on the falling clock edge and the received data is changed on the rising
clock edge.
The baud rate, or speed of data transmission, is set with 12 bits using two
registers UBRRH and UBRRL. UBRRH contain the four most significant bits and
UBRRL contain the eight least significant bits. (19) The baud rate setting depends
on the oscillator frequency and the U2X bit of the UCSRA register. There are a large
number of settings that are achievable, described in detail in the Atmega169
manual. The Butterfly contains a 2 MHz and the data transfer rate used with
HyperTerminal is 19200 bps. With U2X set to 1, the value in UBRRH and UBRRL is
set to a binary values corresponding to the integer 12. (19)
131
The UDR register is the buffer that contains the data to be transmitted or
received. Both the received and transmitted data share the same register. The
transmit buffer can only be written when the UDRE flag has been set in UCSRA,
saying that the buffer is empty, if not then the data is ignored. When enabled the
data is loaded into the shift register and is serially transmitted over the TxD pin of the
RS232 port. The receive buffer is enabled from the RXE bit of UCSRC and receives
data from the microcontroller or other devices via the RxD pin.
3.9.2)
3.9.2) Communication with Matlab
In order to receive the data from Matlab two C functions are needed,
USARTInit, and IsCharAvailable. USARTInit is called first which sets the values in
each of the three control registers and the baud rate registers. The values chosen
for the registers are shown in Table 21 below:
132
Register
Bit
RXC
TXC
UDRE
U2X
MPCM
RXCIE
TXCIE
UDRIE
RXEN
TXEN
UCSZ2
RXB8
TXB8
UMSEL
UPM1
UPM0
USBS
UCSZ1
UCSZ0
UCPOL
Control
Register
UCSRA
UCSRA
UCSRA
UCSRA
UCSRA
UCSRB
UCSRB
UCSRB
UCSRB
UCSRB
UCSRB
UCSRB
UCSRB
UCSRC
UCSRC
UCSRC
UCSRC
UCSRC
UCSRC
UCSRC
UBRRH
UBBRL
Value in
Program
0
Variable
0
1
0
0
0
0
1
1
0
1
0
0
0
0
0
1
1
0
0
12
Table 21: Register Values for HyperTerminal Transmission
These settings enabled the transmitter and receiver and disabled the receive
complete and empty data register interrupts. The transmission was set to be
asynchronous, with eight bits, no parity bit, and 1 stop bit, as well as the 2x speed
change. The UBRRL register was set to 12 and UBRRH is set to 0 as shown in the
manual for a 2 MHz oscillator.
133
The program then entered into an infinite for loop to check for characters at
the USART register. The summary of this part of the program is shown in Figure 47
below:
Enters
isCharAvailable
No
Rx0 has
a character?
Yes
No
Character
‘a’
Character
‘b’
Yes
Scans
Characters
Ends Program
Changes Parameters
and Starts Program
Figure 47
47: Steps for GCC Serial Transfer
The function IsCharAvailable was called when the for loop was entered that
checked the RX0 bit for a character and indicated when a character had been
received. If a character was received, a switch-case command checked to see if it
had a value of ‘a’ or ‘b’. If the value was ‘a’ it then scanned the next 11 characters
and set them to the corresponding variables. If the value was ‘b’ then the timer, if
134
running, stopped and cleared all of the registers. The program could be restarted by
entering in new values and hitting the start button. After the values had been
received into the C program the rest of the functions proceeded as normal with the
SPI being written to first, then the PORT values being set and the timer being
initiated. It is important to note that at this time this section has not been completely
finished, but will be within a reasonable time frame to be discussed with this device.
3.9.3)
3.9.3) Communication with Microcontroller
The data was sent from the PC to the microcontroller using three functions,
ReceiveChar, sendChar and sendString. (36) RecieveChar accepted data from the
microcontroller and set flags to indicate when data had been received. The
sendChar function sent data to the microcontroller one byte at a time when the UDR
registers were changed. The sendString function was used to send data to the
microcontroller when the value is ASCII. (36) These functions updated every time a
timer interrupt occurred so that the data could be updated in the microcontroller
immediately. When the transmission completed the functions cleared any data
present, so that when the next transmission occurred a data overrun error would not
occur. It is important to note that at this time this section has not been completely
finished, but will be within a reasonable time frame to be discussed with this device.
135
4) Results and Discussion
In order to verify that the pulse generation device was working properly
several tests were performed. It was important to show that both types of waveforms
could be generated, and that the full range of amplitude could be seen with little
signal loss at low voltages. It is also important to show that the frequency values are
accurate in comparison to a function generator, and that the number of pulses
requested is correct. Finally, the variable interpulse interval for digital waveforms
must be shown at various intervals.
4.1) Register and GUI Values
Each of these functional tests requires different values to be entered into the
GUI, which then passes different values to the registers. To show how this process
works, the settings for a digital pulse for channel 2, of amplitude 9 volts, with an on
time of 10 ms, an off time of 10 ms, an initial delay of 50 ms and 15 cycles was
used.
After the values were entered and sent to Matlab they were converted into
integer values. Because a square wave was requested, software timing was used
setting the count to 0 and prescaler to 1. The wavetype variable was set to 2
136
because the square wave was chosen, and the amplitude was set to 9 volts. The
position variable was found to be 3880 out of 4095 possible. The digital to binary
converter changed the integer position to a binary value of 1111 0010 1000.
Because the square wave was selected the first register was filled with 0’s as well as
the 4 MSB’s of the second register. The 4 LSB’s of the second register were filled
with the value of 15 and the third register was set to 30. Matlab also set the channel
variable to 2, and the initial delay to 50 ms before being sent to the C program.
In C the variables were loaded, and the first values to be sent to the
microcontroller were from the SPI line to the PGA in the function SpiSendByte. The
values were converted to type U8 (unsigned integer) so that when transferred they
could be sent in a binary fashion. The channel value was sent to the ChannelSelect
function where PB6 was turned on, and PB3 and PB5 were turned off. The wavetype
was sent to the WaveType select function turning on PD6 and PD7 and turning off
PD4 and PD5. The timer values were sent to the function SquareWaveInit with the
count variable setting the OCR0A register to 0, and the prescale variable setting the
proper clock value to 1. The interrupt was set to run 15 times with the pulse being on
for 10 ms and off for 10 ms. The microcontroller first turned on the SPI, then the port
lines, and then the timers, controlling the pulse generator.
137
4.2) Square Wave Generation
In order to prove that the pulse generation device was functionally working
accurately, a comparison with a precision function generator was done for square
waves with a 50% duty cycle. In addition, the first set of examples used three
different amplitudes to show the wide range of the device and that the accuracy was
not lost over this range. The first test was done using the parameters described in
the register and GUI section above. The waveform comparison showing the
accuracy of this example is shown in Figure 48 below:
Figure 48:
48: Square Wave with 10 ms On and Off Times and Amplitude +9V
As can be seen the accuracy of the amplitude and frequency is comparable to
that of the function generator. Figure 49 shown below verifies that 15 pulses have
been sent by the pulse generator and that the initial delay is 50ms.
138
End of Initial
Delay
Pulse Before
Initial Delay
Figure 49
49: Square Wave with On and Off Times of 10ms, 15 pulses, and Initial Delay
of 50 ms
In order to show that the initial delay was working, a single clock pulse was output as
a reference. The fifteen pulses start 50ms after this pulse and retain the timing
accuracy that was present before.
The next example uses the same time parameters, but changes the
amplitude to -2V to show that a negative voltage not the direct inverse of the first
example retains the appropriate accuracy. This is shown in Figure 50 below:
139
Figure 50:
50: Wave with 10 ms On
On and Off Times and Amplitude
Amplitude -2V
It is clearly visible that the accuracy is not reduced by using a negative voltage. The
next example changes the amplitude to a low value of 0.5V, to show that the
resolution is not reduced at low voltages when noise can become an issue. This is
shown in the Figure 51 below:
Figure 51:
51: Wave with 10 ms On and Off Times and Amplitude +0.5V
0.5V
140
This figure shows that the amplitude measured by the oscilloscope is 100 mV
greater than expected because of the noise present. Now that the baseline level of
noise is known, in the near future 1% accuracy or better resistors will be used along
with a precision amplifier to reduce the noise. If necessary a dynamic filter may also
be constructed to further clean the signal.
The final two examples show the minimum and maximum frequency on and
off times required by this application, 0.1 millisecond and 1 second. This comparison
can be seen in Figures 52 and 53 below:
Figure 52
52: Square Wave with 0.1 ms On and Off Times
Figure 53:
53: Square Wave with 1 Second On and Off Times
141
In both figures the top waveform is from the pulse generation device and the bottom
waveform is from the function generator. In the 0.1 ms example the two signals are
out of phase, and the ends are a bit rounded. The on and off times are clearly the
same however, and the waveform appears to have rounded edges because the
screenshot was captured using the roll function from the oscilloscope. The base
frequency of this function is 500ms so the higher frequency ranges have less
resolution and show this characteristic. In the bottom figure, the waveforms are
slightly out of phase as well, but it is clearly visible that the 1 second waveform
generated from the pulse generator is as accurate as from the function generator.
4.3 Sine Wave Generation
Generation
As was shown below the square waves are extremely accurate when
compared with the function generator. The next example shows that the sine wave
generator works equally as well. The timing parameters for the first example are 15
cycles at a frequency of 1 kHz with 10 ms initial delay and an amplitude of 5 volts.
The screenshot is shown in Figure 54 below:
142
Figure 54
54: Sine Wave with Frequency 0.1 kHz and Amplitude 5V
As can be seen from this example, the sine wave is as accurate as the
square wave for the timing, and the filter system creates a clean sine wave. In this
example the peaks began to be squared off because the filter IC was damaged
during testing. A new part has been ordered, and when installed will create a crystal
oscillator quality sine wave.
4.4)
4.4) Square Wave with Variable Interpulse Intervals
In order to show the full functionality of the pulse generator it is important to
show examples with square wave pulses that are not at 50% duty cycle.
143
Oscilloscope snapshots showing at least one on and off pulse were captured to
verify that both times are accurate. The first example of the square wave uses the
parameters of an on time of 2 ms, and off time of 1 ms 5V pulse, 20 cycles, an initial
delay of 50ms. The output of the pulse generator can be seen in Figure 55 below:
Figure 55:
55: Square Wave with On Time of 2 ms and Off Time of 1 ms
The next example continues to use the same parameters, except that the on
time has been increased to 20 ms, which can be seen in the Figure 56 below:
144
Figure 56:
56: Square Wave with On Time of 20 ms and Off Time of 1 ms
The next example uses an off time of 200 ms, showing that even with a long
interpulse interval the accuracy is not reduced. Figure 57 shows this waveform:
Figure
Figure 57:
57: Square Wave with On Time of 200 ms and Off Time of 1 ms
145
The final example captured a pulse generation with a long off time of 20 ms and an
on time of 1ms to show that the process works in reverse. This is shown in Figure 58
below:
Figure 58:
58: Square Wave with On Time of 1ms and Off Time of 20ms
The four examples above prove that the timing intervals are as accurate as
when the on and off times are identical. This proves that software and hardware
timing are equal in resolution for both fast and slow times. In addition, it is useful to
note that the other parameters remain accurate throughout the entire range of
146
examples, meaning that this pulse generation device can be used for all
requirements of this application.
147
5) Future Work
There are two general directions that can be taken to improve the
neurophysiological pulse generator in the future. The first area that can be upgraded
is the microcontroller being used. This device was purchased for its ease of
programming and the extensive programming information that is available. However,
there are some very important limitations to this device including the lack of ports
available to the user (two), the need to use the joystick to program, and the small
size of the EEPROM.
The lacks of ports is not a problem at this time, but if
additional hardware is added, there will not be enough lines and additional
microcontrollers would need to be purchased. If a larger EEPROM was available, a
fully functional lookup table could be generated which can be used for a true DDS
synthesizer. This is possible using the Butterfly, but the size of the EEPROM is not
sufficient to generate the resolution needed. If this upgrade does take place, it would
be strongly advisable to use another Atmel device, so that the only programming
needed would be to add functions for the EEPROM and some simple register
changes. Finally, starting the device can be an inconvenience, because the joystick
must always be toggled, and this process can interfere with the functioning of the
148
unit. Some of the pins on PORTB also correspond to the control of the joystick, and
great care was taken not to overlap these pins, because it caused inconsistent
results to be seen. By purchasing a stand alone microcontroller, the program can be
initiated by shorting two pins, or by an external device.
Another change that could be made to the current design of the pulse
generator would be to use a digital to analog converter to produce the sine waves.
This would produce a purer sine wave then the Bessel filter, which could be
advantageous at lower amplitude. In addition, a sine wave with different interpulse
intervals could be generated, which is not currently possible because of the
limitations of the frequency divider. The SN74390 integrated circuit treats all digital
waves between 20 and 80 percent duty cycle as being at a 50 percent duty cycle
prohibiting the sine wave filter from receiving pulses with different times. The DAC
would eliminate this problem. Two issues that would need to be addressed in this
selection would be using a DAC with high enough resolution, and the amount of
additional programming needed. A high resolution device would most likely use SPI,
and the DAC may have different characteristics for when the data is sampled and
the clock idle polarity. This would require two separate functions for the SPI
programming, and two separate functions for the initialization.
The final recommendation for this current design would be to have the two
circuit boards professionally built. By connecting the components with wire or on a
149
breadboard, and not true solder joints, could create issues in the future as the wire
ages. It is very possible that breakages may occur which could lead to
malfunctioning or damaging of the device. In addition, the amount of noise seen in
the device would be reduced with a professionally built board, especially at high
frequencies and low amplitudes.
Beyond upgrading the microcontroller, it would be worthwhile to look into
using a DDS chip like the AD5930. The advantages of the 24 bit resolution at higher
frequencies could be beneficial in the future, as well as the ability to do multiple
frequency sweeps with one cycle of the program. In addition less circuitry would be
needed because the AD5930 can do both sinusoids and digital waves with one IC.
This would eliminate the need for the frequency divider, wavetype analog, and filter
IC’s, allowing a smaller board to be used.
If this method was pursued, however, several problems would need to be
addressed. The most important is the noise issue which stopped the development of
this design. This can only be prevented by the purchase of a development board or
the manufacturing of a custom circuit board containing this IC. Additionally, the
program would have to be modified to program the AD5930 and PGA sequentially,
with two separate SPI initialization and transfer functions necessary. This must be
done because the data is sampled on the rising edge with the PGA, and the falling
150
edge using the AD5930. Without changing the initialization function one of the
devices would not work at all.
Other issues to be resolved include the development of a method of providing
low frequencies of less than 10Hz, because the DDS does not provide frequencies
at values less than this. Additionally, a method for varying the interpulse interval
would need to be designed, because the AD5930 only uses a 50% duty cycle in the
frequency burst. One method considered in the original design was to apply one
pulse per frequency burst and a variable interpulse interval using the CTRL pin.
However, the methodology would need to be developed to stop the frequency from
increasing with each burst. Finally, the op-amp circuits would need to be modified to
take into account that the output voltage is 1.2V from the AD5930, not 5V. However,
this can simply be done by changing the resistor values. With these changes it is
likely that a true modified DDS system can be developed with a minor monetary
investment, having a considerably lower cost and greater flexibility level then
commercially available systems.
151
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21) SN74HC138 3 Line to 8 Line Decoder/Demultiplexer Manual, Texas
Instruments, 1-16, (2003)
22) DG425 CMOS Analog Switches with Latches, Maxim Electronics, 1-13 (1994)
23) MAX291-295 8th Order Lowpass, Switched Capacitor Filters, Maxim
Electronics, 1-8 (1996)
24) MAX860-861 Frequency Selectable, Switched Capacitor Voltage Converter,
Maxim Electronics, 1-11 (2003)
25) MAX864 Dual Output Charge Pump with Shutdown, Maxim Electronics, 1-12
(1996)
26) SN74390 Dual 4-Bit Decade and Binary Counters, Texas Instruments, 1-11
(1988)
27) MAX532 Dual Serial Input, Voltage Output, 12-Bit MDAC, Maxim Electronics,
1-11 (2003)
28) 5V Supply Derives Power From 3-Wire RS-232 Port, Maxim Electronics
Application Note, taken from http://www.webee.com/Schematics/5V_RS232/5V_RS232.htm
153
29) Miller J, Divide by 100--10 MHz Simple GPSDO
http://www.jrmiller.demon.co.uk/projects/ministd/frqstd.htm
30) Ambrose J, Standalone Circuit Converts Square Waves To Sine Waves,
Electronics Design Online #9493 (2005)
http://www.elecdesign.com/Articles/Index.cfm?AD=1&AD=1&ArticleID=9493
31) Laska J., Berry M., and Sachs D, Using the Serial Port with a MATLAB GUI
(2006) http://cnx.org/content/m12062/latest/
32) Land B, Physiologic Simulator for Classroom Usage, Cornell University,
http://www.nbb.cornell.edu/neurobio/land/PROJECTS/Stimulator2/
33) Microcontroller-Based Sine-Wave Generator Has Crystal Accuracy,
Electronics Design Online #6243 (1998)
http://www.elecdesign.com/Articles/Index.cfm?AD=1&ArticleID=6243
34) Charge Pumps Shine in Portable Designs, Maxim Electronics Application
Note 669, 1-15 (2001)
35) Introduction to RS232 Serial Communications, TALTech Instrumental
Software, (2003)
36) Pardue J., An Introduction to C Programming for Microcontrollers, Smiley
Micros Inc, 1-300 (2005)
154
Appendix 1: Hardware Timing Values
This table shows values between 0.1 ms and 2.67 ms and between
0.970 and 1 second to show how the process worked. The rest of the
table between 2.67 ms and 0.970s can be provided upon request. (The
table is 150 pages in length.)
Time
Frequency
Divided
by 100
time
0.0001
0.0002
0.0003
0.0004
0.0005
0.0006
0.0007
0.0008
0.0009
0.0010
0.0011
0.0012
0.0013
0.0014
0.0015
0.0016
0.0017
0.0018
0.0019
0.0020
0.0021
0.0022
0.0023
0.0024
0.0025
0.0026
0.0027
0.0028
0.0029
0.0030
0.0031
0.0032
10000.000
5000.000
3333.333
2500.000
2000.000
1666.667
1428.571
1250.000
1111.111
1000.000
909.091
833.333
769.231
714.286
666.667
625.000
588.235
555.556
526.316
500.000
476.190
454.545
434.783
416.667
400.000
384.615
370.370
357.143
344.828
333.333
322.581
312.500
0.000001
0.000002
0.000003
0.000004
0.000005
0.000006
0.000007
0.000008
0.000009
0.000010
0.000011
0.000012
0.000013
0.000014
0.000015
0.000016
0.000017
0.000018
0.000019
0.000020
0.000021
0.000022
0.000023
0.000024
0.000025
0.000026
0.000027
0.000028
0.000029
0.000030
0.000031
0.000032
x100
Frequency
Clock
Frequency
Prescaler
Register
Value
1000000.000
500000.000
333333.333
250000.000
200000.000
166666.667
142857.143
125000.000
111111.111
100000.000
90909.091
83333.333
76923.077
71428.571
66666.667
62500.000
58823.529
55555.556
52631.579
50000.000
47619.048
45454.545
43478.261
41666.667
40000.000
38461.538
37037.037
35714.286
34482.759
33333.333
32258.065
31250.000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
155
0.0033
0.0034
0.0035
0.0036
0.0037
0.0038
0.0039
0.0040
0.0041
0.0042
0.0043
0.0044
0.0045
0.0046
0.0047
0.0048
0.0049
0.0050
0.0051
0.0052
0.0053
0.0054
0.0055
0.0056
0.0057
0.0058
0.0059
0.0060
0.0061
0.0062
0.0063
0.0064
0.0065
0.0066
0.0067
0.0068
0.0069
0.0070
0.0071
0.0072
0.0073
0.0074
0.0075
0.0076
0.0077
0.0078
0.0079
0.0080
0.0081
0.0082
0.0083
0.0084
0.0085
0.0086
0.0087
0.0088
0.0089
303.030
294.118
285.714
277.778
270.270
263.158
256.410
250.000
243.902
238.095
232.558
227.273
222.222
217.391
212.766
208.333
204.082
200.000
196.078
192.308
188.679
185.185
181.818
178.571
175.439
172.414
169.492
166.667
163.934
161.290
158.730
156.250
153.846
151.515
149.254
147.059
144.928
142.857
140.845
138.889
136.986
135.135
133.333
131.579
129.870
128.205
126.582
125.000
123.457
121.951
120.482
119.048
117.647
116.279
114.943
113.636
112.360
0.000033
0.000034
0.000035
0.000036
0.000037
0.000038
0.000039
0.000040
0.000041
0.000042
0.000043
0.000044
0.000045
0.000046
0.000047
0.000048
0.000049
0.000050
0.000051
0.000052
0.000053
0.000054
0.000055
0.000056
0.000057
0.000058
0.000059
0.000060
0.000061
0.000062
0.000063
0.000064
0.000065
0.000066
0.000067
0.000068
0.000069
0.000070
0.000071
0.000072
0.000073
0.000074
0.000075
0.000076
0.000077
0.000078
0.000079
0.000080
0.000081
0.000082
0.000083
0.000084
0.000085
0.000086
0.000087
0.000088
0.000089
30303.030
29411.765
28571.429
27777.778
27027.027
26315.789
25641.026
25000.000
24390.244
23809.524
23255.814
22727.273
22222.222
21739.130
21276.596
20833.333
20408.163
20000.000
19607.843
19230.769
18867.925
18518.519
18181.818
17857.143
17543.860
17241.379
16949.153
16666.667
16393.443
16129.032
15873.016
15625.000
15384.615
15151.515
14925.373
14705.882
14492.754
14285.714
14084.507
13888.889
13698.630
13513.514
13333.333
13157.895
12987.013
12820.513
12658.228
12500.000
12345.679
12195.122
12048.193
11904.762
11764.706
11627.907
11494.253
11363.636
11235.955
156
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
0.0090
0.0091
0.0092
0.0093
0.0094
0.0095
0.0096
0.0097
0.0098
0.0099
0.0100
0.0101
0.0102
0.0103
0.0104
0.0105
0.0106
0.0107
0.0108
0.0109
0.0110
0.0111
0.0112
0.0113
0.0114
0.0115
0.0116
0.0117
0.0118
0.0119
0.0120
0.0121
0.0122
0.0123
0.0124
0.0125
0.0126
0.0127
0.0128
0.0129
0.0130
0.0131
0.0132
0.0133
0.0134
0.0135
0.0136
0.0137
0.0138
0.0139
0.0140
0.0141
0.0142
0.0143
0.0144
0.0145
0.0146
111.111
109.890
108.696
107.527
106.383
105.263
104.167
103.093
102.041
101.010
100.000
99.010
98.039
97.087
96.154
95.238
94.340
93.458
92.593
91.743
90.909
90.090
89.286
88.496
87.719
86.957
86.207
85.470
84.746
84.034
83.333
82.645
81.967
81.301
80.645
80.000
79.365
78.740
78.125
77.519
76.923
76.336
75.758
75.188
74.627
74.074
73.529
72.993
72.464
71.942
71.429
70.922
70.423
69.930
69.444
68.966
68.493
0.000090
0.000091
0.000092
0.000093
0.000094
0.000095
0.000096
0.000097
0.000098
0.000099
0.000100
0.000101
0.000102
0.000103
0.000104
0.000105
0.000106
0.000107
0.000108
0.000109
0.000110
0.000111
0.000112
0.000113
0.000114
0.000115
0.000116
0.000117
0.000118
0.000119
0.000120
0.000121
0.000122
0.000123
0.000124
0.000125
0.000126
0.000127
0.000128
0.000129
0.000130
0.000131
0.000132
0.000133
0.000134
0.000135
0.000136
0.000137
0.000138
0.000139
0.000140
0.000141
0.000142
0.000143
0.000144
0.000145
0.000146
11111.111
10989.011
10869.565
10752.688
10638.298
10526.316
10416.667
10309.278
10204.082
10101.010
10000.000
9900.990
9803.922
9708.738
9615.385
9523.810
9433.962
9345.794
9259.259
9174.312
9090.909
9009.009
8928.571
8849.558
8771.930
8695.652
8620.690
8547.009
8474.576
8403.361
8333.333
8264.463
8196.721
8130.081
8064.516
8000.000
7936.508
7874.016
7812.500
7751.938
7692.308
7633.588
7575.758
7518.797
7462.687
7407.407
7352.941
7299.270
7246.377
7194.245
7142.857
7092.199
7042.254
6993.007
6944.444
6896.552
6849.315
157
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
0.0147
0.0148
0.0149
0.0150
0.0151
0.0152
0.0153
0.0154
0.0155
0.0156
0.0157
0.0158
0.0159
0.0160
0.0161
0.0162
0.0163
0.0164
0.0165
0.0166
0.0167
0.0168
0.0169
0.0170
0.0171
0.0172
0.0173
0.0174
0.0175
0.0176
0.0177
0.0178
0.0179
0.0180
0.0181
0.0182
0.0183
0.0184
0.0185
0.0186
0.0187
0.0188
0.0189
0.0190
0.0191
0.0192
0.0193
0.0194
0.0195
0.0196
0.0197
0.0198
0.0199
0.0200
0.0201
0.0202
0.0203
68.027
67.568
67.114
66.667
66.225
65.789
65.359
64.935
64.516
64.103
63.694
63.291
62.893
62.500
62.112
61.728
61.350
60.976
60.606
60.241
59.880
59.524
59.172
58.824
58.480
58.140
57.803
57.471
57.143
56.818
56.497
56.180
55.866
55.556
55.249
54.945
54.645
54.348
54.054
53.763
53.476
53.191
52.910
52.632
52.356
52.083
51.813
51.546
51.282
51.020
50.761
50.505
50.251
50.000
49.751
49.505
49.261
0.000147
0.000148
0.000149
0.000150
0.000151
0.000152
0.000153
0.000154
0.000155
0.000156
0.000157
0.000158
0.000159
0.000160
0.000161
0.000162
0.000163
0.000164
0.000165
0.000166
0.000167
0.000168
0.000169
0.000170
0.000171
0.000172
0.000173
0.000174
0.000175
0.000176
0.000177
0.000178
0.000179
0.000180
0.000181
0.000182
0.000183
0.000184
0.000185
0.000186
0.000187
0.000188
0.000189
0.000190
0.000191
0.000192
0.000193
0.000194
0.000195
0.000196
0.000197
0.000198
0.000199
0.000200
0.000201
0.000202
0.000203
6802.721
6756.757
6711.409
6666.667
6622.517
6578.947
6535.948
6493.506
6451.613
6410.256
6369.427
6329.114
6289.308
6250.000
6211.180
6172.840
6134.969
6097.561
6060.606
6024.096
5988.024
5952.381
5917.160
5882.353
5847.953
5813.953
5780.347
5747.126
5714.286
5681.818
5649.718
5617.978
5586.592
5555.556
5524.862
5494.505
5464.481
5434.783
5405.405
5376.344
5347.594
5319.149
5291.005
5263.158
5235.602
5208.333
5181.347
5154.639
5128.205
5102.041
5076.142
5050.505
5025.126
5000.000
4975.124
4950.495
4926.108
158
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
2000000
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
0.0204
0.0205
0.0206
0.0207
0.0208
0.0209
0.0210
0.0211
0.0212
0.0213
0.0214
0.0215
0.0216
0.0217
0.0218
0.0219
0.0220
0.0221
0.0222
0.0223
0.0224
0.0225
0.0226
0.0227
0.0228
0.0229
0.0230
0.0231
0.0232
0.0233
0.0234
0.0235
0.0236
0.0237
0.0238
0.0239
0.0240
0.0241
0.0242
0.0243
0.0244
0.0245
0.0246
0.0247
0.0248
0.0249
0.0250
0.0251
0.0252
0.0253
0.0254
0.0255
0.0256
0.0257
0.0258
0.0259
0.0260
49.020
48.780
48.544
48.309
48.077
47.847
47.619
47.393
47.170
46.948
46.729
46.512
46.296
46.083
45.872
45.662
45.455
45.249
45.045
44.843
44.643
44.444
44.248
44.053
43.860
43.668
43.478
43.290
43.103
42.918
42.735
42.553
42.373
42.194
42.017
41.841
41.667
41.494
41.322
41.152
40.984
40.816
40.650
40.486
40.323
40.161
40.000
39.841
39.683
39.526
39.370
39.216
39.063
38.911
38.760
38.610
38.462
0.000204
0.000205
0.000206
0.000207
0.000208
0.000209
0.000210
0.000211
0.000212
0.000213
0.000214
0.000215
0.000216
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