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FBS-GAM02-P-C50 50V/10A Rad Tolerant Multifunction Power Module Vehicle Features Description 50V/10A Fully De-Rated Operation Independent Low and High Side Power Drivers Four Possible Configurations: Single Low Side Driver Single High Side Driver Independent High and Low Side Drivers Half-Bridge With Shoot-Through Protection Internal Shoot-Through Protection Internal Power Good Circuitry High Speed Switching Capability: 1.0MHz Rugged Compact Molded SMT Package “Pillar” I/O Pads eGaN® Switching Elements No Bi-polar technology Commercially Screened Freebird Semiconductors FBS-GAM02-P-(x) Series Radiation Tolerant Multifunction Power Module incorporates eGaN® switching power HEMTs with intended end use design within commercial satellite space environments. These development modules include two output power switches, two high speed gate drive circuits (consisting entirely of eGaN® switching elements), two power Schottky diode clamp elements, shoot-through prevention logic (for the Half-Bridge connection) and +5V gate drive bias “power good” monitoring circuitry in an innovative, space-efficient, 18 pin SMT molded epoxy package. Applications Development Vehicle for: • FBS-GAM02-P-R50 (Available) • FBS-GAM02-C-R50 (Planned) Power Switches/Actuators Single and Multi-Phase Motor Phase Drivers Commercial Satellite EPS & Avionics High Speed DC-DC Conversion FBS-GAM02-P-C50 Functional Block Diagram (10) TBST (11) VDD VBIAS (4) Level Shift PG (5) (12) TOUT (8) TOS Power Good Detection And Logic SD (7) UVA/*SD (6) TIN (2) BIN (1) 1KΩ 1KΩ (13) BOUT Shoot-Thru/ Disable Logic FBS-GAM02-P-C Rev Q11 March 7, 2017 H/S Gate Driver (14) PGND R (Pin 9 Is No Connect) TSTP (17) TCON (18) BSTP (16) BCON (15) LGND (3) H/S Gate Driver 1 www.freebirdsemi.com FBS-GAM02-P-C50 FBS-GAM02-P-C50 Configuration and Pin Assignments 18 Pin Molded SMT Package w/Pillar Pins TOP (X-Ray) VIEW 6 7 8 9 10 11 5 12 4 3 13 2 1 18 17 16 15 14 FBS-GAM02-P-C50 Configuration and Pin Assignment Table Pin # Pin Name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 BIN TIN LGND VBIAS PG UVA/*SD SD TOS N/C TBST VDD TOUT BOUT PGND BCON BSTP TSTP TCON Input/Output I I -I O I I I -I I O O -I O O I ©2017 Freebird Semiconductor Corporation Pin Function Low Side Switch Logic Input High Side Switch Logic Input Logic Ground, 0V (Low Current) +5V Gate Driver Power Supply Bias Input Voltage Power Good Logic Output (Open Drain) Under Voltage Threshold Adjustment/Low True Shutdown Input High True Shutdown Input High Side Output (Switching Node) Sense No Internal Connection High Side Bootstrap Potential Positive Power Input Supply Voltage (High Current) Top Output, High Side Switch (High Current) Bottom Output, Low Side Switch (High Current) Power Supply Return, 0V (High Current) Low Side Switch Control Input Low Side Switch Shoot Through Protection Output High Side Switch Shoot Through Protection Output High Side Switch Control Input Page 2 of 33 www.freebirdsemi.com FBS-GAM02-P-C50 Absolute Maximum Ratings TC =25 oC unless otherwise noted Symbol VDS ID VBIAS VIN TJ, TSTG Tc Tsol ESD Parameter-Conditions Power Switch Drain to Source Voltage (Note 1) Continuous Drain Current Gate Driver Bias Supply Voltage BIN or TIN Input Voltage Operating and Storage Junction Temperature Range Case Operating Temperature Range Package Mounting Surface Temperature ESD class level Value Units 50 10 -0.3 to 6.0 -0.3 to 5.0 -55 to +130 -55 to +110 260 1A V A V V oC oC oC Thermal Characteristics Symbol RθJC RθJC Parameter-Conditions Value Units Thermal Resistance Junction to Case, Either eGaN® Power Switch (Note 3) Thermal Resistance Junction to Case, Either Clamp Schottky Diode (Note 3) 10.5 45 oC/W ©2017 Freebird Semiconductor Corporation Page 3 of 33 www.freebirdsemi.com FBS-GAM02-P-C50 Bottom and Top Power Switch Static Electrical Characteristics TC =25oC unless otherwise noted PARAMETER Bottom and Top Switch Output Leakage Current Bottom and Top Switch Output ON-State Resistance Bottom and Top Switch Source-Drain Clamping Voltage SYMBOL TEST CONDITIONS MIN VDS = 50V; BIN = TIN = 0.8Vdc (Note 1) IL 25oC VDS = 25V; BIN = TIN =0.8Vdc (Note 1) Tc= RDS(ΟΝ) BIN = TIN =0.8Vdc (Note 1); ID = 10A (Note 2) Tc= 25oC VSD BIN = TIN =0.8Vdc (Note 1); ID = 10A (Note 2) Tc= 25oC Tc= 110oC Tc= Tc= 110oC TYP MAX UNITS 20 30 uA - 10 25 - 110 130 7 10 10 15 0.8 1.08 V 0.6 0.88 V MAX UNITS 9.1 A - 110oC µA mΩ Schottky Catch Diode Transient Electrical Characteristics TC =95oC unless otherwise noted PARAMETER Peak Pulse Forward Current SYMBOL IF(pk) TEST CONDITIONS MIN TYP BIN = TIN = 0.8Vdc; 13V < VDD < 22V (Notes 3,18) Top and Bottom Power Switch Transient Electrical Characteristics TC =110oC unless otherwise noted PARAMETER Peak Pulse Drain Current SYMBOL ID(pk) TEST CONDITIONS MIN TYP fs = 400kHz; 10% < Duty Cycle < 90%; 30ns < Dead Time < 50ns; 13V < VDD < 50V, VBIAS = 5.0Vdc (Notes 3, 19) MAX UNITS 15 A MAX UNITS 0.8 V BIN, TIN Logic Input Static Electrical Characteristics TC =25oC unless otherwise noted PARAMETER SYMBOL TEST CONDITIONS MIN TYP Low Logic Level Input Voltage VIL VBIAS = 5.0Vdc (Note 4) High Logic Level Input Voltage VIH VBIAS = 5.0Vdc (Note 5) 2.5 Low Logic Level Input Current IIL VBIAS = 5.0V, VIL = 0.4V -5 +/-1 5 uA High Logic Level Input Current IIH VBIAS = 5.0V, VIL = 3.0V -5 +/-1 5 uA MIN TYP MAX UNITS 0.2 V V PG Logic Output Static Electrical Characteristics TC =25oC unless otherwise noted PARAMETER SYMBOL TEST CONDITIONS Low Logic Level Output Voltage VOL VBIAS = 5.0Vdc (Notes 6,7) High Logic Level Output Voltage VOH VBIAS = 5.0Vdc (Notes 6,7) Low Logic Level Output Current High Logic Level Output Leakage Current IOL VBIAS = 5.0V (Note 8) 5 mA IOH VBIAS = 5.0V, PG = 5.5V (Note 8) 15 uA MAX UNITS 50 V MAX UNITS 5.5 V 15.5 mA 4.8 V VDD-to-PGND Static Electrical Characteristics TC =25oC unless otherwise noted PARAMETER VDD-to-PGND Operating Voltage Range SYMBOL VDDPGND TEST CONDITIONS (Note 3) MIN TYP 10 VBIAS Static Electrical Characteristics TC =25oC unless otherwise noted PARAMETER VBIAS Recommended Operating Voltage Range VBIAS Operating Current ©2017 Freebird Semiconductor Corporation SYMBOL TEST CONDITIONS VBIAS VBIAS = 5.0Vdc (Notes 3,9) IBIAS VBIAS = 5.5Vdc Page 4 of 33 MIN TYP 4.5 12.9 www.freebirdsemi.com FBS-GAM02-P-C50 PG Functional Static Electrical Characteristics TC =25oC unless otherwise noted PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS VBIAS UVLO Rising Threshold UVLO+ 4.05 4.1 4.25 V VBIAS UVLO Falling Threshold UVLO- 3.85 3.95 4.05 V VBIAS UVLO Hysteresis UVLO+ - UVLO- VBIAS OVLO Rising Threshold OVLO+ VBIAS OVLO Falling Threshold OVLO- VBIAS OVLO Hysteresis (Notes 6,7) 0.2 V 5.95 6.1 6.25 V 5.85 5.9 6.05 V OVLO+ - OVLO- 0.12 V Bottom and Top Power Switch Dynamic Electrical Characteristics TC =25oC unless otherwise noted PARAMETER BIN-to-TOUT Turn-ON Delay Time BOUT Rise Time SYMBOL TEST CONDITIONS MIN TYP MAX UNITS 42 45 ns 5.0 6.5 ns td(off) 46 50 ns tf 7.5 8.5 ns td(on) 48 60 ns 7.5 9.0 ns td(on) tr VDS = 25V; ID = 10A (See Switching Figures) BIN-to-BOUT Turn-OFF Delay Time BOUT Fall Time TIN-to-TOUT Turn-ON Delay Time TOUT Rise Time TIN-to-TOUT Turn-OFF Delay Time TOUT Fall Time tr td(off) VDS = 25V; ID = 10A (See Switching Figures) tf 65 75 ns 5.0 7.0 ns TYP MAX UNITS Module Dynamic Electrical Characteristics TC =25oC unless otherwise noted PARAMETER Top Power Switch Start Up Pre-Charge Time: Half Bridge Configuration Top Power Switch Maximum Duty Cycle Minimum Switching Frequency: Bottom Power Switch Minimum Switching Frequency: Top Power Switch Maximum Switching Frequency: Half-Bridge Configuration BIN-to-TIN and TIN-to-BIN Dead Time Shoot-Through Protection Activation Delay Time ©2017 Freebird Semiconductor Corporation SYMBOL TEST CONDITIONS tprg MIN 5 us (Notes 3,10,11,12) td/c fs 95 (Notes 3,10,11,12,13,14,15,16) 0 Hz 200 kHz 1.0 tdt (Notes 3,13,15) tst (Notes 3,14) Page 5 of 33 % 35 MHz 60 5 ns ns www.freebirdsemi.com FBS-GAM02-P-C50 Specification Notes 1.) VBIAS = +5Vdc, PGND = LGND = 0V, TOUT or BOUT = 50Vdc. 2.) Measured using 4-Wire (Kelvin) sensing techniques. 3.) Guaranteed by design. Not tested in production. 4.) When either logic input (BIN or TIN) is at the low input voltage level the associated output (BOUT or TOUT) is guaranteed to be OFF (high impedance). 5.) When either logic input (BIN or TIN) is at the high input voltage level the associated output (BOUT or TOUT) is guaranteed to be ON (low impedance). 6.) Parameter measured with a 10kΩ pull-up resistor between PG and VBIAS. 7.) PG is at a low level when VBIAS is below the UVLO- (falling) threshold level or the OVLO+ (rising) threshold level. PG is at a high level when VBIAS is above the UVLO+ (rising) threshold level or the OVLO- (falling) threshold level. 8.) PG is an open drain output referenced to LGND. 9.) VBIAS levels below the UVLO- and above the OVLO+ thresholds result in the internal bottom and top gate drivers being disabled: The logic inputs to the drivers are internally set to a logic low state to prevent damage to the eGaN® power switches. 10.) The top power switch gate driver utilizes a bootstrap capacitor to provide the proper bias for this circuit. As such, this capacitor MUST be periodically re-charged from the VBIAS supply. As a stand-alone high side switch with a ground-connected/ground-sensed load, this recharging takes place each time the switch is turned OFF and the TOUT node returns to ground potential (0Vdc). However when connected in conjunction with the bottom power switch in the Half-Bridge configuration, this connection to ground does not exist until the bottom power switch is turned ON, thus creating a low impedance connection from TOUT through the bottom power switch (BOUTPGND). The time tprg is the minimum time required to insure that the bootstrap capacitor is properly charged when power is initially applied to the FBS-GAM02-P-C50 Module. 11.) The minimum frequency of operation is determined by the internal bootstrap capacitance and the bias current required by the top power switch gate driver circuit. 12.) In order to keep the top power switch gate driver bootstrap capacitor properly charged it is recommended that the maximum duty cycle (ton/fs) of the top power switch is limited to the value shown. Accordingly, the top power switch is unsuitable for DC applications. 13.) For Half Bridge applications, a time delay (“dead time”) MUST be added between the time when the BIN input transitions HIGH-TO-LOW and the TIN input transitions LOW-to-HIGH, and also when the TIN input transitions HIGH-to-LOW and the BIN INPUT transitions LOW-to-HIGH, to avoid both power switches being actuated simultaneously. Simultaneous actuation of the top and bottom power switches causes very large, uncontrolled and destructive currents to flow through the ON-state switches from VDD to PGND. The maximum dead time prevents the Schottky clamp diodes in the power switch outputs from being overstressed and damaged by excessive power dissipation. Please refer to Figures 24 and 25. 14.) The shoot-through protection is activated if both the BIN and TIN logic inputs are set to the logic high (“1”) condition simultaneously. 15.) VDD = 50V, ID = +/-10A and fs = 1.0MHz. Half-Bridge configuration. 16.) The maximum switching frequency is limited by power dissipation in the Half-Bridge configuration, and not by throughput delay times. Faster switching frequencies are possible at reduced Vdd and Io operating levels and at reduced ambient operating temperatures. See Figures 20 through 23. 17.) Current from pin 12 to pin 11 (Top Schottky) or pin 14 to pin 13 (Bottom Schottky), not drawn simultaneously. Pulse duration = 500us. Repetition rate = 5 seconds. 18.) Current from pin 11 to pin 12 or pin 12 to pin 11 (Top Power Switch), or pin 13 to pin 14 or pin 14 to pin 13 (Bottom Power Switch), not drawn simultaneously. Pulse duration = 500us. Repetition rate = 5 seconds. ©2017 Freebird Semiconductor Corporation Page 6 of 33 www.freebirdsemi.com FBS-GAM02-P-C50 Switching Figures Figure1. TIN-to-TOUT Switching Time Test Circuit 7 8 9 10 6 +5Vdc Pulse Generator VDD 5 4 VBIAS 3 LGND 2 TIN 1 BIN +25Vdc 11 FBS-GAM02-P-C50 TOUT 12 DUT 13 PGND Rload = 2.5Ω 14 18 17 16 15 Only pins connected during testing identified. Pulse Generator set to 500kHz frequency, 5% duty cycle. Figure 2. TIN-to-TOUT Switching Time Definition Vpeak 90% Vpeak TOUT 10% Vpeak -Vf 5V TIN 2.5V 0V td(on) td(off) tr tf NOTE: Waveforms exaggerated for clarity and observability. ©2017 Freebird Semiconductor Corporation Page 7 of 33 www.freebirdsemi.com FBS-GAM02-P-C50 Switching Figures (Continued.) Figure 3. BIN-to-BOUT Switching Time Test Circuit 7 8 9 +25Vdc 10 6 11 5 +5Vdc Pulse Generator 4 VBIAS FBS-GAM02-P-C50 3 LGND DUT 2 TIN 1 BIN Rload = 2.5Ω 12 BOUT 13 PGND 14 18 17 16 15 Only pins connected during testing identified. Pulse Generator set to 500kHz frequency, 5% duty cycle. Figure 4. BIN-to-BOUT Switching Time Definition Vpeak 90% Vpeak BOUT 10% Vpeak Von 5V BIN 2.5V 0V td(on) td(off) tr tf NOTE: Waveforms exaggerated for clarity and observability. ©2017 Freebird Semiconductor Corporation Page 8 of 33 www.freebirdsemi.com FBS-GAM02-P-C50 Switching Figures (Continued.) Figure 5. VBIAS-to-PG Relationship VBIAS OVLO+ OVLOUVLO+ UVLO- 0V VOH PG VOL NOTE: Waveforms exaggerated for clarity and observability. ©2017 Freebird Semiconductor Corporation Page 9 of 33 www.freebirdsemi.com FBS-GAM02-P-C50 Typical Application Information The following figures detail the suggested applications for the FBS-GAM02-P-C50 Module. For all applications, please refer to the Implementation section, following, for proper power supply bypassing and layout recommendations and criteria. In any of the following applications, if an inductive load is driven then an appropriately-rated Schottky rectifier/diode should be connected across the load to prevent destructive flyback/”kickback” voltages from destroying the FBS-GAM02-P-C50. In all the following figures only the pins that are considered or that require connection are identified. Figure 6. Single High-Side Power Switch Configuration 7 8 9 10 6 +5Vdc PWM In 5 4 VBIAS 3 LGND 2 TIN 1 BIN FBS-GAM02-P-C50 VDD 11 TOUT 12 13 PGND 14 VDD Rload 18 17 16 15 Figure 7. Single Low-Side Power Switch Configuration 7 8 9 10 6 VDD 5 +5Vdc PWM In VDD 4 VBIAS 3 LGND 2 TIN 1 BIN FBS-GAM02-P-C50 11 12 BOUT 13 PGND 14 Rload 18 17 16 15 ©2017 Freebird Semiconductor Corporation Page 10 of 33 www.freebirdsemi.com FBS-GAM02-P-C50 Figure 8. Independent High- and Low-Side Power Switches 7 8 9 VDD 10 Rload1 6 VDD 11 TOUT 12 5 +5Vdc PWM1 In PWM2 In 4 VBIAS 3 LGND 2 TIN 1 BIN FBS-GAM02-P-C50 BOUT 13 PGND 14 Rload2 18 17 16 15 Figure 9. Independent Switch Configuration: Two-Transistor Forward Converter Output Stage 7 8 9 VDD 10 6 5 +5Vdc PWM In 4 VBIAS 3 LGND 2 TIN 1 BIN FBS-GAM02-P-C50 VDD 11 TOUT 12 BOUT 13 PGND 14 D2 D3 L VOUT T D4 D1 C Rload N:1 VOUT = (VDD • ton)/(N • T) ton 18 17 16 15 PWM T ©2017 Freebird Semiconductor Corporation Page 11 of 33 www.freebirdsemi.com FBS-GAM02-P-C50 Figure 10. Half-Bridge Configuration: POL Converter Output Stage 7 8 9 VDD 10 6 VDD 11 TOUT 12 BOUT 13 PGND 14 5 LGND PWM1 In 2 TIN PWM2 In 1 BIN BCON 3 FBS-GAM02-P-C50 BSTP VBIAS TCON 4 TSTP +5Vdc L VOUT C Rload 18 17 16 15 VOUT = ~ VDD • (ton/((2 * td) + T)) ton PWM1 PWM2 td td T ©2017 Freebird Semiconductor Corporation Page 12 of 33 www.freebirdsemi.com FBS-GAM02-P-C50 Forward 2 3 4 BIN TIN LGND VBIAS TSTP 16 BSTP 15 BCON 7 8 9 10 14 13 12 11 11 12 2 1 PWM2 In 3 Page 13 of 33 T td 18 BIN TCON PWM2 td PGND 17 PWM1 BOUT TSTP 4 +5Vdc 5 16 TIN 7 BSTP PWM1 In 8 15 LGND 9 BCON ton 14 FBS-GAM02-P-C50 10 6 ©2017 Freebird Semiconductor Corporation 13 VBIAS Speed Control VDD TOUT VDD MOTOR VDD VDD TOUT 17 FBS-GAM02-P-C50 TCON 6 5 BOUT 18 +5Vdc Reverse 1 PGND Direction Control Figure 11. Half-Bridge Configuration: Single Phase Motor Drive Stage www.freebirdsemi.com FBS-GAM02-P-C50 Figure 12. Half-Bridge Configuration: Single Phase Motor Driver Equivalent Circuit VDD PWM1 In Speed MOTOR + Forward Direction Reverse PWM2 In “H” Bridge Motor Spins Forward When Polarized + to -. Motor Spins Reverse When Polarized - to +. Motor State Truth Table PWM1 PWM2 Forward Reverse X X 0 0 Min D Max D 1 0 Max D Min D 1 0 Min D Max D 0 1 Max D Min D 0 1 Motor Result (Direction/Speed) OFF Forward/Max Speed Forward/Min Speed Reverse/Min Speed Reverse/Max Speed 0 = Switch OFF, 1 = Switch ON, X = Don’t Care, Min D = Minimum Duty Cycle, Max D = Maximum Duty Cycle. ©2017 Freebird Semiconductor Corporation Page 14 of 33 www.freebirdsemi.com FBS-GAM02-P-C50 Figure 13. Half-Bridge Configuration: Three Phase Motor Drive Stage 7 8 9 VDD 10 6 VDD 11 TOUT 12 BOUT 13 PGND 14 5 LGND PWM1 In 2 TIN PWM2 In 1 BIN BCON 3 FBS-GAM02-P-C50 BSTP VBIAS TSTP 4 TCON +5Vdc 18 17 16 15 ton PWM1 7 6 5 4 VBIAS 3 LGND PWM3 In 2 TIN PWM4 In 1 BIN 3 Phase Motor 10 FBS-GAM02-P-C50 BCON T 9 BSTP td 8 TSTP td TCON PWM2 VDD 11 TOUT 12 BOUT 13 PH2 PGND 14 PH3 VDD 11 TOUT 12 BOUT 13 PGND 14 PH1 18 17 16 15 ton PWM3 7 10 6 5 4 VBIAS T PWM5 In 3 LGND 2 TIN PWM6 In 1 BIN FBS-GAM02-P-C50 BCON T 9 BSTP td 8 TSTP td TCON PWM4 18 17 16 15 ton PWM5 PWM6 td td T ©2017 Freebird Semiconductor Corporation Page 15 of 33 www.freebirdsemi.com FBS-GAM02-P-C50 Power Good Output (PG) The FBS-GAM02-P-C50 incorporates a Power Good (PG) sensing circuit that disables both the low and high side drivers when the +5V gate drive bias potential (VBIAS) falls below an under-voltage threshold, typically 4.25V, or rises above an over-voltage threshold level, typically 5.60V – refer to Figure 5 for the proper operational nomenclature and functionality versus the state of the VBIAS power supply. During the time when the VBIAS potential is outside of the pre-set threshold(s), the PG output (Pin 5) pin is logic low (“0”). Alternatively, when the VBIAS potential is within the pre-set thresholds the PG pin is logic high (“1”). The PG pin is an open drain output, so for proper operation the PG pin must be pulled-up to VBIAS external to the module with a 10kΩ resistor. The logic condition of the PG pin may be sensed by an FPGA or Microcontroller/DSP in-order to determine when the power switches in the FBS-GAM02 may be driven with a pulse-width modulated (PWM) input signal(s) at the BIN and TIN logic inputs. If either the under-voltage and over-voltage protection features are not required or desired, then these may be disabled by connecting the UVA/*SD (Pin 6) pin to VBIAS and the SD pin (Pin 7) to LGND, as shown in Figure 14. Figure 14. PG Protection Function Disabled 7 8 9 10 6 VDD 11 TOUT 12 5 +5Vdc PWM1 In PWM2 In 4 VBIAS 3 LGND 2 TIN 1 BIN FBS-GAM02-P-C50 BOUT 13 PGND 14 18 17 16 15 “Shoot-Through” Protection The FBS-GAM02-P-C50 is also provided with a “shoot-through” or cross-conduction prevention circuit that must be utilized when the FBS-GAM02-P-C50 is connected as a half-bridge driver circuit. If both the BIN and TIN logic inputs are asserted to a high (“1”) logic condition simultaneously, the common outputs BOUT and TOUT are commanded to be open circuited – in other words turned-OFF to a high impedance condition. This action prevents destructive, uncontrolled current from passing from VDD through the two closed, low ON-resistance eGaN® power switches. If the FBS-GAM02-P-C50 is connected in the Half-Bridge configuration (where BOUT is connected to TOUT and the top and ©2017 Freebird Semiconductor Corporation Page 16 of 33 www.freebirdsemi.com FBS-GAM02-P-C50 bottom switches are closed alternatingly), then the BCON (Pin 15) pin MUST be externally connected to the BSTP (Pin 16) pin, and the TCON (Pin 18) pin must be connected externally to the TSTP (Pin 17) pin as shown in Figure 15. Figure 15. Shoot-Through Protection Function Enabled 7 8 9 10 6 5 +5Vdc 4 VBIAS 3 LGND PWM1 In 2 TIN PWM2 In 1 BIN FBS-GAM02-P-C50 VDD 11 TOUT 12 BOUT 13 PGND 14 18 17 16 15 Shutdown Inputs (SD and *SD) The low- and high-side power switches may be disabled (set to their high impedance OFF state) utilizing the SD or *SD inputs, as shown in Figures 16 and 17. To disable the FBS-GAM02-P-C50 module power outputs, the SD (Pin 7) input may be driven by an open drain or open collector that pulls this input to the VBIAS supply pin (Pin 4). Alternatively, the module may be disabled by driving the UVA/*SD (Pin 6) input with an open drain or open collector that pulls this input to LGND (Pin 3). If the SD or SD* functions are not required, these pins should be left OPEN (unconnected). Figure 16. UVA/*SD Input Function Enabled 7 6 8 9 10 UVA/*SD VDD 11 TOUT 12 5 +5Vdc SD R Q PWM1 In PWM2 In 4 VBIAS 3 LGND 2 TIN 1 BIN FBS-GAM02-P-C50 BOUT 13 PGND 14 18 17 16 15 ©2017 Freebird Semiconductor Corporation Page 17 of 33 www.freebirdsemi.com FBS-GAM02-P-C50 Figure 17. SD Input Function Enabled +5Vdc *SD R 7 Q SD 6 8 9 10 VDD 11 TOUT 12 5 PWM1 In PWM2 In 4 VBIAS 3 LGND 2 TIN 1 BIN FBS-GAM02-P-C50 BOUT 13 PGND 14 18 17 16 15 PGND Pin (Pin 14) For proper operation of the FBS-GAM02-P-C50, the PGND (Pin 14) pin MUST be connected directly to the system VDD ground return in the application circuit. If current monitoring/sensing is required or desired, this sensing should be done at the output pins (BOUT and/or TOUT) in series with the load. Top Gate Driver Bootstrap Pins (Pins 8 and 10) To facilitate lower switching frequencies by the top driver, Pin 8 (TOS) and Pin 10 (TBST) are provided for the external connection of an auxiliary bootstrap capacitor. This capacitor should be an X7R dielectric type in the range of 0.047 to 0.1uF and should have a 25Vdc minimum rating. This capacitor should be connected to pins 8 and 10 with the shortest possible PCB etch traces. If no external capacitor is utilized then Pins 8 and 10 should be left OPEN. N/C Pin (Pin 9) Pin 9 is not internally connected. This “no connection” pin is recommended to be grounded to PGND as good engineering practice to avoid coupling unwanted noise into the internal circuitry of the FBS-GAM02-P-C50. Recommended VDD-to-PGND Power Supply Bypassing The power supply pins and return pin of the FBS-GAM02-P-C50 require proper high frequency bypassing to one-another in order to prevent harmful switching noise-related spikes from degrading or damaging the internal circuitry in the FBS-GAM02-P-C50 module, or impacting operating performance. The more critical bypassing situation is related to the VDD supply to PGND (Pin 14), which bears the high rate-of-change voltages and currents associated with ©2017 Freebird Semiconductor Corporation Page 18 of 33 www.freebirdsemi.com FBS-GAM02-P-C50 the internal eGaN® power switches interacting with a load. It is recommended that a minimum of two (2) 4.7 microfarad ceramic capacitors, one (1) 1.0 microfarad ceramic capacitor and one (1) 0.1 microfarad ceramic capacitor, all with 100V ratings, be connected from VDD to PGND. All four of these capacitors should be low ESR types, if possible. It is strongly recommended that these capacitors inscribe the smallest possible loop area between VDD and PGND soas to minimize the inductance related to this loop area. Figure 19 illustrates three instances of recommended and acceptable VDD-PGND bypassing, as implemented in PCB copper etch. Regardless, different end-use implementations will require different VDD bypass capacitor placements, and it is strongly recommended that the chosen bypassing scheme be evaluated for its effectiveness. It is also recommended that a 1.0 microfarad ceramic capacitor and a 0.1microfarad ceramic capacitor, each 25V rating, be connected between VBIAS (pin 4) and FGND (pin 3). Suggested FBS-GAM02-P-C50 Schematic Symbol The suggested schematic symbol for the FBS-GAM02-P-C50 is shown in Figure 18. This symbol groups the I/O pins of the FBS-GAM02-P-C50 into groups of similar functionality. Figure 18. Suggested FBS-GAM02-P-C50 Schematic Symbol Figure 19. Recommended VDD-to-PGND Power Supply Bypassing (Not to Scale) ©2017 Freebird Semiconductor Corporation Page 19 of 33 www.freebirdsemi.com FBS-GAM02-P-C50 Acceptable 1 (PCB Top View) Acceptable 2 (PCB Bottom View) 4.7uF 0.1uF 1.0uF 4.7uF Pin 13 I/O Pad: BOUT 1.0uF 0.1uF Pin 12 I/O Pad: TOUT 4.7uF Pin 11 I/O Pad: VDD 4.7uF Pin 11 I/O Pad: VDD Pin 14 I/O Pad: PGND Pin 14 I/O Pad: PGND Acceptable 3 (PCB Top View) Top Layer PCB Etch Inner Layer 1 PCB Etch 4.7uF 0.1uF 1.0uF 4.7uF Use Abundant Vias to Connect Bottom Etch to Top Etch Pin 11 I/O Pad: VDD Isolated, highfrequency PGND current return path to PGND I/O pad (Pin 14) on the Module [beneath etch show at left] Pin 12 I/O Pad: TOUT Pin 13 I/O Pad: BOUT Pin 14 I/O Pad: PGND Use Abundant Vias to Connect Top Etch to Inner Layer Etch ©2017 Freebird Semiconductor Corporation Page 20 of 33 www.freebirdsemi.com FBS-GAM02-P-C50 Figure 20. Maximum Power Supply Voltage (Vdd)Versus Switching Frequency (fsw) Versus Module Case Temperature (Tc), Io = 10A, Half-Bridge Configuration. 60 50 Io = 10Adc Vdd (Vdc) 40 110C 30 85C 70C 20 10 0 200 300 400 500 600 700 800 900 1000 Switching Frequency (kHz) ©2017 Freebird Semiconductor Corporation Page 21 of 33 www.freebirdsemi.com FBS-GAM02-P-C50 Figure 21. Maximum Power Supply Voltage (Vdd)Versus Switching Frequency (fsw) Versus Module Case Temperature (Tc), Io = 10A, Half-Bridge Configuration. 60 50 Vdd (Vdc) 40 110C 85C Io = 10Adc 30 70C 50C 35C 20 10 0 1.0 1.2 1.4 1.6 1.8 2.0 Switching Frequency (MHz) ©2017 Freebird Semiconductor Corporation Page 22 of 33 www.freebirdsemi.com FBS-GAM02-P-C50 Figure 22. Maximum Output Current (Io)Versus Switching Frequency (fsw) Versus Module Case Temperature (Tc), Vdd = 50V, Half-Bridge Configuration. 12 10 Vdd = 50dc Io (Adc) 8 110C 6 85C 70C 4 2 0 200 300 400 500 600 700 800 900 1000 Switching Frequency (kHz) ©2017 Freebird Semiconductor Corporation Page 23 of 33 www.freebirdsemi.com FBS-GAM02-P-C50 Figure 23. Maximum Power Supply Voltage (Vdd)Versus Switching Frequency (fsw) Versus Module Case Temperature (Tc), Io = 10A, Half-Bridge Configuration. 12 10 Io (Adc) 8 Vdd = 25dc 110C 6 85C 4 2 0 1.0 1.2 1.4 1.6 1.8 2.0 Switching Frequency (MHz) ©2017 Freebird Semiconductor Corporation Page 24 of 33 www.freebirdsemi.com FBS-GAM02-P-C50 Figure 24. Maximum Dead Time (tdt) Versus Switching Frequency (fsw) Versus Module Case Temperature (Tc), Vdd = 25V, Half-Bridge Configuration (Refer to Fig. 23). 65 Maximim Dead Time (ns) 60 Vdd = 25Vdc 55 110C 85C 50 70C 50C 45 40 35 1.0 1.2 1.4 1.6 1.8 2.0 Switching Frequency (MHz) ©2017 Freebird Semiconductor Corporation Page 25 of 33 www.freebirdsemi.com FBS-GAM02-P-C50 Figure 25. Maximum Dead Time (tdt) Versus Switching Frequency (fsw) Versus Module Case Temperature (Tc), Io = 10A, Half-Bridge Configuration (Refer to Fig. 21). 65 Maximum Dead Time (ns) 60 55 50 Io = 10Adc 110C 85C 45 70C 50C 40 35 30 25 1.0 1.2 1.4 1.6 1.8 2.0 Switching Frequency (MHz) ©2017 Freebird Semiconductor Corporation Page 26 of 33 www.freebirdsemi.com FBS-GAM02-P-C50 Radiation Characteristics The FBS-GAM02-P-C50 intended utilization is as a development vehicle for our future hermetically sealed radiation hardened ceramic version, noted by Freebird Semiconductor as the FBS-GAM02-C-R50, and currently available FBSGAM02-P-R50 Epoxy, Over-Molded Commercial Space Version. Radiation hardness assured devices (under identical form-fit function) is the FBS-GAM02-P-R50: • • Freebird Semiconductor FBS-GAM02-P-R50 incorporates internally utilized eGaN HEMT technology designed, fabricated and tested per Mil-Std-750 Method 1019 for total ionizing dose validation with an in-situ Gamma Bias for (i) VGS = 5.1V, (ii) VDS=VGS=0V and (iii) VDS=80% BVDSS. Under the above prescribed conditions Freebird Semiconductor can guarantee full parametric data limits as outlined within the FBS-GAM02-P-C50 datasheet with pre/post radiation effects guarantee under a best practice commercial screened reliability level. When incorporating Freebird Semiconductors radiation validated HEMT materials the FBS-GAM02-P-R50 series are then “guaranteed by designed” to survive High Dose Rate TID to levels of no less than 100 kRad (Si) with minimum Single Event Immunity to: Heavy Ion: Au, LET= 83.7, 2482 MeV, Range = 130um ©2017 Freebird Semiconductor Corporation Page 27 of 33 www.freebirdsemi.com FBS-GAM02-P-C50 Thermal Characteristics Figure 26. Typical Top or Bottom Power eGAN® HEMT Normalized Junction-to-Case Thermal Impedance Figure 27. Typical Top or Bottom Catch Schottky Normalized Junction-to-Case Thermal Impedance ©2017 Freebird Semiconductor Corporation Page 28 of 33 www.freebirdsemi.com FBS-GAM02-P-C50 Package Outline and Dimensions Figure 28. FBS-GAM02-P-C50 Package Outline and Dimensions ©2017 Freebird Semiconductor Corporation Page 29 of 33 www.freebirdsemi.com FBS-GAM02-P-C50 Recommended PCB Solder Pad Configuration The novel I/O “pillar” pads fabricated onto the bottom surface of the FBS-GAM02-P-C50 module are designed to provide optimal electrical, thermal and mechanical properties for the end-use system designer. To achieve the full benefit of these properties, it is important that the FBS-GAM02-P-C50 module be soldered to the PCB motherboard using SN63 (or equivalent) solder. Care should be taken during processing to insure there is minimal solder voiding in the contacts to the VDD (pin 11), TOUT (pin 12), BOUT (pin 13) and PGND (Pin 14) pads on the module. The recommended pad dimensions and locations are shown in Figure 29. All dimensions are shown in inches. Figure 29. Recommended PCB Solder Pad Configuration (Top View) 10 6 1 ©2017 Freebird Semiconductor Corporation 11 14 18 Page 30 of 33 www.freebirdsemi.com FBS-GAM02-P-C50 Freebird Semiconductor Part Number Information FBS-GAM02-P-C50 50= 50V fully Derated VDD operation or C= Commercial screen or R= Commercial screen rad-hard assurance* P= Molded Plastic SMT Package C= Ceramic SMT Package Freebird Semiconductor “GaN Adaptor Module” *FBS-GAM02-P-R50 (Utilizes High Lead Content Die) & FBS-GAM02-C-R50 (Utilizes High Lead Content Die) Disclaimers ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. Freebird Semiconductor Corporation, its affiliates, agents, employees, and all persons acting on its or their behalf (collectively, “Freebird”), disclaim all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product. Freebird makes no warranty, representation or guarantee regarding the suitability of the products for any purpose. To the maximum extent permitted by applicable law, Freebird disclaims (i) all liability arising out of the application or use of any product, (ii) all liability, including without limitation special, consequential or incidental damages, and (iii) all implied warranties, including warranties of fitness for particular purpose, non-infringement and merchantability. Statements regarding the suitability of products for certain types of applications are based on Freebird market knowledge of typical requirements that are often placed on similar technologies in generic applications. Product specifications do not expand or otherwise modify Freebird terms and conditions of purchase, including but not limited to the warranty expressed therein. Except as expressly indicated in writing, Freebird products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the Freebird product could result in personal injury or death. Customers using Freebird products not expressly indicated for use in such applications do so at their own risk. Please contact authorized Freebird personnel to obtain written terms and conditions regarding products designed for such applications. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Freebird. Product names and markings noted herein may be trademarks of their respective owners. ©2017 Freebird Semiconductor Corporation Page 31 of 33 www.freebirdsemi.com FBS-GAM02-P-C50 Export Administration Regulations (EAR) The products described in this datasheet could be subjected to the Export Administration Regulations (EAR). They may require an approved export license prior to export from the United States. An export includes release of product or disclosure of technology to a foreign national inside or outside the United States. International Traffic in Arms Regulations (ITAR) The products described in this datasheet could be subjected to the International in Arms Regulations (ITAR). They require an approved export license prior to export from the United States. An export includes release of product or disclosure of technology to a foreign national inside or outside the United States. Patents Freebird Semiconductor holds numerous U.S and international patents. 15/374,756, 15/374,774, PCT/US2016/065952, PCT/US2016/065946. Any that apply to the product(s) listed in this document are identified by markings on the product(s) or on internal components of the product(s) in accordance with U.S Patent laws eGaN is a registered trademark of Efficient Power Conversion Corporation, Inc. Data and specification subject to change without notice. ©2017 Freebird Semiconductor Corporation Page 32 of 33 www.freebirdsemi.com FBS-GAM02-P-C50 Revision Datasheet Revision REV P REV Q REV # Product Status Proposal/development Characterization and Qualification Production Released Contact Freebird Semiconductor Corporation for further information and to order: Email : Phone: Website: Address: [email protected] +1 941 740 1909 www.Freebirdsemi.com 17 Parkridge Road, Unit E Haverhill, MA 01835 ©2017 Freebird Semiconductor Corporation Page 33 of 33 www.freebirdsemi.com