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Instrumentation Development Laboratory SciFi Tracker IDL_14_42 Test Report Author: Peter Orel Checked by: Gary S. Varner Approved by: Gary S. Varner Friday, May 5, 2017 Table of Contents 1 Introduction .......................................................................................................................................... 3 2 Optical inspection ................................................................................................................................. 4 3 Functional tests ..................................................................................................................................... 5 4 3.1 Voltage regulator and voltage rails ............................................................................................... 5 3.2 HV DAC .......................................................................................................................................... 6 Bugs and applied corrections ................................................................................................................ 7 4.1 Negative LDO ................................................................................................................................ 7 2 1 Introduction In this document we present the result of functional test for the IDL_14_42 board which serves as the power supply board for the CSciFi. The board has been assembled using the manual pick-&-place and LPKF oven machines located in the back of the ID Laboratory within the University of Hawaii at Manoa. The equipment: Laboratory power supply: IDL 11090059 Multi-meter: Fluke 112, IDL MM07 Soldering station: Pace ST30 The following figure shows a block diagram of the board: Figure 1: Block diagram of the Power Board 3 2 Optical inspection Figure 2: Photo of IDL_14_42 The board did not have any short circuits or defective solder bonds. The two QFN ICs have been soldered perfectly. 4 3 Functional tests 3.1 Voltage regulator and voltage rails The ability to turn on and off has been tested successfully all regulators turn on and off with at expected logic levels. The voltages measured are given, in comparison with the calculated ones, in the table below: It is to be noted that the input voltage has been sourced from a laboratory power supply. The input voltage was measured at 5.027V Voltage rail +5VA -5VA +2V5 +5VSC +2V5SW -5VASW HV_BIAS Expected voltage [V] 4.524 -4.500 2.541 5.027 2.952 -5.280 61.52 Measured voltage [V] 4.623 -4.509 2.567 5.027 2.909 -5.227 62.75 Error [%] 2.14 0.19 1.01 0 1.48 1.01 1.96 All voltage rails, including the HV voltage are within 5% error which is usually accepted. It is to be noted however that this condition is at zero load. 5 3.2 HV DAC As expected the DAC wakes up at mid-range of the internal reference 2.055V. If this will present a problem a redesign might be necessary in order to use an op-amp to reverse the slope. Following figure shows the proposed solution: Figure 3: Solution for inverting the HV_DAC slope In this case we would need to buy a version of this dame DAC that wakes up at zero. The following figure shows the characteristics of this solution in terms of Vdac vs Vout of the above op-amp: 5 4.5 4 3.5 Vout [V] 3 2.5 2 1.5 1 0.5 0 0 0.5 1 1.5 2 2.5 Vdac [V] 3 3.5 4 4.5 Figure 4: Vdac vs Vout 6 4 Bugs and applied corrections 4.1 Negative LDO On the negative LDO the REF pin 5 of U5 has been connected through a resistor to the respective negative input. The correct way would be to connect it to the ground. So the a correction was made such that the line connecting the resistor to the negative supply has been cut and a wire has been added to connect the resistor to the nearest ground. The following figure shows the correction: Figure 5: Correction for negative LDO 7