Download Applying FPGA to Biological Problems

Applying
Field Programmable
Gate Arrays
to Biological Problems
Presented by
Debbi Ryle
Daryl Popig
Accelerated Data Concepts
June – 2006
Accelerated Data Concepts
Introductions
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Accelerated Data Concepts
Specializing in Reconfigurable Computing Development
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Debbi Ryle, Co-founder
Daryl Popig, Co-founder
Collaborations
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Dr. Eric Stahlberg, OpenFPGA.org
David Pellerin, Impulse Accelerated Technologies
June – 2006
Accelerated Data Concepts
FPGA Technology
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FPGA (field programmable gate array) are
digital logic chips containing:
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Programmable logic blocks
Programmable interconnects & switch matrices
Programmable I/O
Block RAM
PowerPC processors
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June – 2006
used in embedded systems
Accelerated Data Concepts
FPGA Technology
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Inherently parallel device
Performs spatial processing of work
Reconfigurable - “Reconfigurable Computing”
 Loadable sets of logic blocks
 Specialized tasks
Eliminates bottlenecks associated with generalpurpose processors
Alternative direction to exploit Moore’s Law
June – 2006
Accelerated Data Concepts
Why is Digital Logic Faster Than Software?
Spatial vs. Temporal Computation
Processors divide computation across time, dedicated logic divides across space
y = Ax2 + Bx + C
Temporal Computation
t1
t1 = x
t2 = t1 * A
t2 = t2 + B
t2 = t2 * t1
y = t2 + C
Spatial Computation
x
*
*
t2
A
B
C
A
*
+
C
+
Y
June – 2006
B
Accelerated Data Concepts
Using FPGAs for Acceleration
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Identify algorithms that can exploit FPGA finegrained parallelism
Look for candidate code using low-level data
parallelism
Exploit digital logic blocks ready to execute:
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Computationally intensive calculations
Excessive multiple inner looping or backtracking
June – 2006
Accelerated Data Concepts
Candidate Applications
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Drug Docking - prescreening small module compounds
for drug interaction
Medical Imagining - Cat Scanning
Molecular Simulation
Matlab
June – 2006
Accelerated Data Concepts
Computational Challenges
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Smith-Waterman algorithm used to identify similarities
among bioinformatics sequences
Floyd-Warshall algorithm performing graph network
analysis
Searches through unstructured data (video, audio,
instrument signals, etc.)
June – 2006
Accelerated Data Concepts
FPGA - Design Approach
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Code application in C language
Find the computational “hot spots”
Partition the algorithm into software and hardware
processing
Use interactive optimization tools to analyze and
improve the performance of hardware-accelerated
functions
Use a C-to-hardware compiler to generate
synthesizable hardware
Load the resulting bitmap file to the FPGA device
June – 2006
Accelerated Data Concepts
FPGA - Design Approach
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Find the program’s “hot
spots”
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Parallel threads
Computational routines
Nested N loops
June – 2006
Accelerated Data Concepts
FPGA - Design Approach
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Partition the algorithm
into software and
hardware processing
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Use data streaming,
message passing and/or
shared memory to
partition the algorithm
into multiple
communicating software
and hardware processes
June – 2006
Accelerated Data Concepts
FPGA - Design Approach
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Use interactive optimization tools to analyze and
improve the performance of hardware-accelerated
functions
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Emerging FPGA tools:
 Impulse-C
 Nallatech DimeTalk
 Mitronics
 SRC
June – 2006
Accelerated Data Concepts
FPGA - Design Approach
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Use a C-tohardware
compiler to
generate
synthesizable
hardware
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Load the
resulting bitmap
file to the FPGA
device
June – 2006
Accelerated Data Concepts
Programming Tools
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New tools simplifying FPGA programming at a
higher level of abstraction
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Allows software developers to code without intense
hardware knowledge
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Allows easier Hardware/Software co-simulation
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Converts C code to a Hardware Descriptive
Language which is then converted to a net list and
then the place and route tools make a FPGA
loadable bitmap
June – 2006
Accelerated Data Concepts
FPGA Hardware
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Latest chip capacity denser with million gate devices
Requires less energy consumption
Reduce costs
Major Chip manufactures:
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Xlinix
Altera
Available on wide variety of hardware platform:
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SRC
CRAY Linux
Linux based
Windows based
June – 2006
Accelerated Data Concepts
Performance Gains
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Searching speed-up by 45x
Smith-Waterman implementation speed ups by
64x
Network Graph analysis problems speed ups by
30x
June – 2006
Accelerated Data Concepts
Summary
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General Processor limitations - Moores law
driving for alternatives
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Hardware - chip capacity denser allowing more
complex algorithms
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Software tools simplifying FPGA programming
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World wide researcher’s interest OpenFPGA.org
June – 2006
Accelerated Data Concepts
Acknowledgements
Special Thanks to OCCBIO
Conference
For more information on FPGA
Technology, visit:
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http://acceleratedata.com
http://www.openfpga.org
http://implusec.com
June – 2006
Accelerated Data Concepts
References
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Givaris, T., Reconfigurable Computing,
http://www.ics.uci.edu/~dutt/ics212-wq05/reconfig.pdf
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Lysaght, P. 2006, FPGAs in the decade after Von Neuman Century,
DATE06 conference proceedings, Munich, Germany
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Pellerin, D., 2006, Hardware/Software co-design, FPGA II, DATE06
conference proceedings, Munich, Germany
June – 2006
Accelerated Data Concepts