Download An improved transformerless grid connected photovoltaic inverter

Energy Conversion and Management 88 (2014) 854–862
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Energy Conversion and Management
journal homepage: www.elsevier.com/locate/enconman
An improved transformerless grid connected photovoltaic inverter with
reduced leakage current
Monirul Islam ⇑, Saad Mekhilef ⇑
Power Electronics and Renewable Energy Research Laboratory (PEARL), Department of Electrical Engineering, University of Malaya, Kuala Lumpur 50603, Malaysia
a r t i c l e
i n f o
a b s t r a c t
Article history:
Received 7 May 2014
Accepted 4 September 2014
Available online 29 September 2014
Transformerless inverters are most preferred for grid connected photovoltaic (PV) generation system due
to higher efficiency and lower cost. However, to meet the safety regulations, the leakage current which
deteriorates the power quality and generates electro-magnetic interference in transformerless PV inverter, has to be addressed carefully. In order to eliminate the leakage current, an improved H5 topology is
proposed in this paper. The operating principle, common mode (CM) characteristics, and the impact of
junction capacitance of the switches on the CM voltage are investigated in details. The desired relationship
among the junction capacitances is proposed to eliminate the CM leakage current. Three-level output voltage is achieved in the improved inverter employing unipolar sinusoidal pulse width modulation (SPWM).
Furthermore, the European efficiency is improved by replacing the high frequency IGBT switches with
MOSFETs. The proposed topology is compared with other transformerless topologies in terms of leakage
current, different mode (DM) characteristics, and efficiency. The improved inverter topology is simulated
in MATLAB/Simulink software to validate the accuracy of the theoretical explanations. Finally, a 1 kW
laboratory prototype has been built and tested. The experimental results show that the proposed inverter
has a maximum efficiency of 98.0% and 97.45% European efficiency with 16 kHz switching frequency.
Ó 2014 Elsevier Ltd. All rights reserved.
Keywords:
Common mode voltage
Converter
Grid connected
Leakage current
Photovoltaic
Transformerless inverter
1. Introduction
The energy crisis is one of the most crucial problems in recent
time and renewable-energy sources play an important role to
address these problems. Among a variety of renewable-energy
sources, the photovoltaic generation system has rapidly increased
during recent years. Based on the newest report on installed PV
power, the milestone of 100GW PV system was achieved at the
end of 2012, and the majority of these were grid-connected [1–3].
A single-phase converter is used in low power (less than 5 kW) single phase grid-connected applications, but its design embeds generally a line-frequency transformer or a high-frequency transformer
that adjusts the converter DC voltage and separates the PV arrays
from the grid [4,5]. Because of size, weight and price in favor of
high-frequency transformers, the tendency is to remove the line frequency transformers when designing the new converter. Furthermore, the existence of high-frequency transformer desires several
power stages, as a result, reducing cost and increasing efficiency will
be a challenging task [6,7]. In contrast, the transformerless grid
connected PV inverters are manifested to offer the benefits of lower
⇑ Corresponding authors.
E-mail addresses:
(S. Mekhilef).
[email protected]
(M.
http://dx.doi.org/10.1016/j.enconman.2014.09.014
0196-8904/Ó 2014 Elsevier Ltd. All rights reserved.
Islam),
[email protected]
cost, higher efficiency, smaller size, and weight. However, a galvanic
connection is formed between the power grid and the PV module
when the transformer is omitted. Therefore, a varying CM voltage
is generated; as a result, leakage current flows through the loop consisting of the parasitic capacitors, the filter inductors, the bridge,
and the utility grid [8–10]. This CM leakage current increases the
grid current harmonics and system losses and creates a strong
conducted and radiated electromagnetic interference and more
specifically, leads to a safety threat [11–13].
Many topologies have been investigated to minimize the CM
leakage current and improve the efficiency of the transformerless
grid-connected PV inverters, which can be classified into two
groups: (1) half-bridge inverter topology, (2) full-bridge (FB) inverter topology. The half-bridge inverter topology eliminates the fluctuating CM voltage and produces almost zero leakage current. The
main drawback of the half-bridge topology is the necessity of high
input voltage (700VDC) corresponds to 230VAC application [14].
On the other hand, in the full-bridge inverter, this required input
voltage is only 350 VDC for the same application. Nevertheless, the
main disadvantage of the full-bridge inverter is that it can employ
only bipolar-SPWM with two-level output voltage. Consequently,
high ripples in the output current are produced and thus, the
efficiency of the entire system is reduced. To overcome these problems, many advanced topologies have been proposed in the
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M. Islam, S. Mekhilef / Energy Conversion and Management 88 (2014) 854–862
literature [15–23] as shown in Fig. 1, which are based on the fullbridge topology. These topologies can achieve three-level output
voltage by employing unipolar SPWM and also can keep the CM
voltage constant during all operational modes.
The main two issues for the transformerless PV inverters are;
(1) the inverter should not have any leakage current and (2)
achieve high efficiency over a wide load range. In order to obtain
these advantages, an improved single-phase transformerless gridtied PV inverter topology is proposed in this paper. The main features of the proposed improved inverter are: (1) the efficiency of
the inverter is improved by replacing the high frequency IGBT
switches with MOSFETs because the supper MOSFETs has low conduction and switching losses, (2) proposed relationship among the
switches’ junction capacitance and disconnection of PV module
from the grid at the freewheeling mode ensure not to produce
ground leakage current, (3) dead time is not required at both
high-frequency switching commutation and grid zero-crossing
instant which improves the output power quality and increases
the efficiency. Detail operation principle, unipolar SPWM scheme
and CM leakage current characteristics of the proposed inverter
are illustrated in this paper. The efficiency of the improved inverter, H5 inverter and FB bipolar inverter are measured and a comparison among these topologies has been summarized to ensure
the effectiveness of the proposed topology.
This paper is prepared as follows: The analysis of leakage current of the transformerless topology is described in Section 2.
The proposed improved topology structure, operation principle
with the unipolar SPWM control scheme, and the impact of junction capacitance on the CM voltage are investigated in Section 3.
Design consideration for the improved topology is discussed in
Section 4. The experimental and simulation results from a 1 kW/
50 Hz rated prototype are presented in Section 5 and the conclusion is given in Section 6.
2. Leakage current analysis
When the transformer is removed from the PV inverter, a galvanic connection is formed between the PV module and the grid,
which can create a CM resonant circuit. A fluctuating CM voltage
(a)
(b)
(LB*LA/LA+LB)
Vtcm=Vcm+Vd/2(LB-LA/LA+LB)
N
CPVg
Zg
icm
Fig. 2. Leakage current analysis: (a) equivalent model for full-bridge PV inverter (b)
simplest form.
P
P
(a)
S4
S3
D2
PV
LA
Vpv
Cdc
PV
Vg
S2
LB
D3
D4
(d)
S5
S1
S3
LA
S1
LA
S3
S5
A
Cdc
Co
S2
Vpv
Vg
PV
Cdc1
Co
LB
S4
S2
P
(f)
S5
Cdc1 D7
S3
S4
LB
P
S5
Cdc1
S6
LA
A
Co
PV
Cdc2 D8
Vpv
B
S2
S4
Vg
S1
S3
LB
LA
A
Co
PV
Vg
B
Cdc2
S6
N
S6
N
S1
Vg
B
N
Vpv
LB
S4
B
(e)
Vg
P
A
PV
Co
B
N
P
Vpv
LA
A
S2
N
(c)
Cdc1
S6
B
S1
S3
S5
A
Vpv
S1
(b)
S2
S4
LB
N
Fig. 1. Some existing transformerless topologies for grid-tied PV inverter (a) topology proposed in [17], (b) topology proposed in [22], (c) H5 topology proposed in [19], (d)
HERIC topology proposed in [21], (e) H6 topology proposed in [20], and (f) oH5 topology proposed in [15].
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M. Islam, S. Mekhilef / Energy Conversion and Management 88 (2014) 854–862
can electrify the resonant circuit and may induce leakage current.
Huafeng et al. and Bin et al. derive the simplified form of the resonant circuit as shown in Fig. 2. The total CM voltage can be defined
as follows [16,24,25]:
V tcm ¼ V cm þ
V dm LB LA
2 LA þ LB
ð1Þ
where LA and LB are the filter inductors, Vcm and Vdm are CM and DM
voltages, respectively, which are given in Eqs. (2) and (3):
V cm ¼
1
ðV AN þ V BN Þ
2
ð2Þ
V dm ¼ V AN V BN
ð3Þ
where VAN and VBN are the voltages of the full-bridge inverter from
mid-point A and B of the bridge-leg to the reference terminal N. In
the half-bridge inverter family, one of the filter inductors LA or LB is
commonly zero. On the other hand, LA and LB are usually designed
with equal values for the full-bridge inverter family. As a result,
the condition of eradicating CM leakage current is concluded that:
V tcm ¼ V cm
1
¼ ðV AN þ V BN Þ ¼ constant
2
ð4Þ
3. Improved topology and modulation strategy
3.1. Circuit structure of the improved topology
3.2. Operation principle
Grid-tied photovoltaic system generally operates at unity
power factor. Fig. 3(b) shows the gate signals of the improved
inverter. The additional switch S5 commutates at the switching
frequency to ensure the DC de-coupling states. In the positive
half-cycle of grid current, S1 is always on and S4 and S5 commutate at the switching frequency with the identical commutation
order to create +VPV and 0 state. Likewise, in the negative halfcycle, S3 is always on and S2 and S5 commutate at the switching
frequency. Consequently, four operational modes are proposed
that produce the output voltage states of VPV, 0, and VPV. Fig. 4
shows the operational principles of the proposed improved
inverter.
Mode I: When S4 and S5 are turned on, the inductor current iL,
flowing through S1, S4 and S5, is increased. In this mode,
VAB = +VPV and the CM voltage can be calculated as follows:
V cm ¼
(a)
P
S5
S1
S3
A
Vpv
PV
Cdc
Co
Vg
B
S2
S4
LB
1
1 V PV V PV
V PV
¼
ðV AN þ V BN Þ ¼
þ
2
2 2
2
2
ð6Þ
Mode III: This mode starts when S2 and S5 are turned-on and
the inductor current increases reversely through S2, S3 and
S5. Therefore, the output voltage VAB = VPV and the CM voltage
become:
V cm ¼
1
1
V PV
ðV AN þ V BN Þ ¼ ð0 þ V PV Þ ¼
2
2
2
ð7Þ
Mode IV: In the negative half-cycle of grid current, freewheeling
mode starts when S2 and S5 are turned-off which is shown in
Fig. 4(d). In this mode, VBN falls and VAN rises until their values
are equal. Therefore, VAB = 0 and the inductor current decreases
through S3 and the body diode of S1, like as mode II. The CM
voltage is calculated as:
V cm ¼
LA
ð5Þ
Mode II: Fig. 4(b) shows the freewheeling path when S4 and S5
are turned-off. In this mode, VAN falls and VBN rises until their
values are equal. Therefore, VAB = 0 and the inductor current
decreases through S1 and the body diode of S3. Thus, the CM
voltages can be calculated in (6):
V cm ¼
Fig. 3(a) shows the improved circuit structure which is based on
the H5 topology. The high-frequency IGBT switches from each
phase leg are replaced by MOSFET switches. In order to eliminate
the CM leakage current, two extra capacitors are connected across
the switches S2 and S4. LA, LB, and Co construct the LC type filter,
coupled to the grid. The proposed improved topology can achieve
three-level output voltage with unipolar SPWM and meet the
condition of constant CM voltage.
1
1
V PV
ðV AN þ V BN Þ ¼ ðV PV þ 0Þ ¼
2
2
2
1
1 V PV V PV
V PV
¼
ðV AN þ V BN Þ ¼
þ
2
2 2
2
2
ð8Þ
It is clear that, during the aforementioned four commutation
modes, Vcm almost remains at constant value, Vcm = 1/2VPV [from
(5)–(8)]. Therefore, the improved inverter can keep the CM voltage
constant during all operational modes with unipolar SPWM.
N
(b)
Fig. 3. Improved transformerless grid-tied PV inverter: (a) circuit configuration and
(b) gate signals with unity power factor.
3.3. Impact of junction capacitance
The analysis made in the previous section is applicable only for
ideal condition. However, when the inverter commutates from
each non-decoupling state to decoupling state, the slopes of voltage VAN and VBN depends on the junction capacitance of the
switches. As a result, the CM voltage gets affected. The aforesaid
four operational modes can be divided into two groups based on
the decoupling and non-decoupling states.
In the active mode (mode I and mode III), the PV module and
the grid are directly coupled through the output filter inductor.
Therefore, the effect of switches junction capacitance on the CM
voltage is insignificant in this mode. However, in the freewheeling
mode (mode II and mode IV), the PV module is disconnected from
the grid by the additional switch S5 and the CM voltage is influenced by the switches’ junction capacitance. The complexity of
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M. Islam, S. Mekhilef / Energy Conversion and Management 88 (2014) 854–862
(a) P
(b)
S5
S1
P
S5
S3
S1
LA
A
Vpv
Cdc
PV
Co
Vg
S3
Vpv
Cdc
PV
Co
B
S2
S2
N
LB
S4
N
(c) P
(d)
S5
S1
P
S5
S3
S1
LA
A
Vpv
Vg
B
LB
S4
LA
A
Cdc
PV
Co
Vg
S3
Vpv
Cdc
PV
B
LB
S4
S2
N
Vg
Co
B
S2
LA
A
LB
S4
N
Fig. 4. Equivalent circuit of four operational modes. (a) Active and (b) freewheeling modes in the positive half cycle of grid current. (c) Active and (d) freewheeling modes in
the negative half cycle of grid current.
eliminating leakage current is increased, when the switches’ junction capacitance is taken into consider.
There are always two phases when the inverter commutates
from each non-decoupling state to decoupling state (from mode I
to mode II as an example) because of the symmetry of the operation modes.
Phase I: An equivalent transient circuit can be drawn by considering the commutation from mode I to mode II as shown in Fig. 5,
where C1–C5 symbolizes the junction capacitors of the switches
S1–S5. The transient charging or discharging circuits are drawn
up by the junction capacitors C2, C3, C4, and C5, when the switches
(a)
S5
P
ic5
ic3
i1
C5
C1
C3
S1
LA
Vdc
ic2
ic4
S2
C2
i3
C4
LB
S4
ic5
N
i2
(b)
ic5 (Vdc) ic3
(Vdc)
ð11Þ
where i1, i2, and i3 are the charging or discharging current of the circuit and ic2, ic3, ic4, and ic5 are respectively the current flowing
through C2, C3, C4 and C5.
The equivalent circuit model for the transient state is presented
in Fig. 5(b). It is seen that C4 is charged by C2 and C5 in parallel
through the output filter inductors LA and LB. Therefore, the voltage
across C4 will increase and the voltage across C2 will decrease until
their values are equal. According to the charge conversion theory, it
is found that:
V AN ¼ V BN ¼ V PV
C2 þ C5
C2 þ C4 þ C5
LB
(0)
ic4
C4
i2
Fig. 5. Transient circuit by considering the switching from mode I to mode II. (a)
Transient circuit and (b) simplified circuit.
ð12Þ
Phase II: In the meantime, the body diode of S3 conducts to freewheel and the transient state is ended. According to (12), the
equivalent resonant circuit can be drawn as Fig. 6. It can be seen
that the voltage VAN and VBN will be equal to VPV/2 only if
C4 = C2 + C5 at the end of transient state. Therefore, the CM voltage
will remain constant at mode II.
i c5
C2+C5
V dc
C2+C4+C5
ic3
i3
ic2
i3 ¼ ic2 þ ic3 þ ic5
C5
LA
C2
ð9Þ
ð10Þ
(V dc )
C3
i1
C5
i1 ¼ ic3 þ ic5
i2 ¼ ic4 ¼ ic2 þ ic5
S3
i3
S4 and S5 are turned-off but the body diode of S3 has not conducted to flow the freewheeling current. The following equations
are given by applying Kirchhoff’s current law:
i c2
(0)
C2
C4
i6
LB
LA
i c4
C PV
i6
Fig. 6. Simplified equivalent resonant circuit in mode II.
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M. Islam, S. Mekhilef / Energy Conversion and Management 88 (2014) 854–862
At the end of transient state, if C4 – C2 + C5 the voltage VAN, VBN
and Vcm will not be equal to VPV/2. Therefore, the condition of eliminating CM leakage current will be broken. As a result, a high-frequency leakage current will flow through the junction capacitors,
parasitic capacitors and filter inductors as shown in Fig. 6.
In the proposed improved inverter, there are always two commutations from non-decoupling modes to decoupling modes.
When the inverter commutates to mode IV from mode III, it can
be analyzed same as before and summarized in the following equations to get VAN = VBN = VPV/2 when the transient state is ended.
(1) Commutation from mode I to mode II: C4 = C2 + C5
(2) Commutation from mode III to mode IV: C2 = C4 + C5
Therefore, the condition of junction capacitor for eliminating
the CM leakage current is concluded that C5 = 0 and C2 = C4.
Nevertheless, for practical application, the junction capacitance
of the switches cannot be zero. Therefore, the theoretical value is
amended for practical application as follows:
C2 ¼ C4 C5
ð13Þ
capacitor with lower values of equivalent series resistance (ESR),
reduce high-frequency voltage ripple.
4.3. Output filter
As analysis in the Section 3.2, the DM voltage of the improved
inverter varies between VPV, 0 and VPV. Thus, a low-pass output
filter would be optimized. In order to reduce the high-frequency
voltage fluctuation between the PV module and the ground, two
split inductors with identical values are adopted to the proposed
improved inverter. The entire solution can be considered equivalent to the LC type filter. The value of the DM inductor can be calculated by considering the instant when the output current ripples
reach maximum value. The factor representing such instant is
calculated by the maximum value of (17) as [17]:
2
DIfactor ¼ M sinðxtÞ M 2 sin ðxtÞ
ð17Þ
where M is the modulation index, x is the angular frequency. Fig. 7
shows the waveform of DIfactor for different modulation indexes. It
can be seen that the maximum value of DIfactor is 0.25. The value
of the output filter inductor could be as follows:
V PV DIfactor
f s DiL
4. Design consideration
L¼
4.1. Semiconductors
where VPV is the input voltage, fs is the switching frequency and DiL
is the maximum ripple on the output current. A higher ripple value
reduces the output filter size and also the inductor losses. However,
the higher ripple at the output increases RMS current cause’s higher
conduction losses. Therefore, by considering these two issues, a
value not higher than 20% is suggested. The output filter capacitor
is calculated using Eq. (19) by selecting the cutoff frequency [28].
Voltage stress across the switches S1 and S3 are maximum and
equal to the input voltage. The root mean square (RMS) current
flowing through them can be calculated in (14) as:
irms
S1
sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
Z T g =2
1
¼
½I2out ðtÞ dt
Tg 0
ð14Þ
Co ¼
where Tg is the grid period and Iout(t) is the output current.
On the other hand, switching voltage across the switches S2, S4,
and S5 operating at the switching frequency are equal to the half of
the input voltage. The RMS current flowing through these switches
can be calculated in (15), where D(t) is the duty cycle of the
selected switches, that varies from zero to one depending on the
amplitude of the sinusoidal reference.
irms
S2
¼
sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
Z T g =2
1
½I2out ðtÞ:DðtÞ:dt
Tg 0
ð15Þ
4.2. DC side capacitor
DC link capacitor works as an energy storage device to make
sure the stable operation of the inverter at maximum power point
(MPP). The precise design of the DC link capacitor is most important, because having an excessive amount of capacitance causes
some safety concern. If the inverter is powered down, the large
amount of energy stored in the DC link capacitor can be dangerous
for the repairing persons. The minimum capacitor value could be
calculated in Eq. (16), considering the approach presented in
[26,27].
C PV ¼
Pout
2 x D% V in min V in
1
2
4p2 f c L1
ð18Þ
ð19Þ
4.4. Losses due to the additional capacitors
In order to verify the proposed relationship among the junction
capacitances which was analyzed in Section 3.3, two additional
capacitors whose values are much greater than the junction capacitance of S5, are connected in parallel to S2 and S4 as shown in
Fig. 3(a). Depending on two constraints, first, increasing switching
losses and second, minimization of CM leakage current, additional
capacitor’s value is selected as 650pF. The additional current
induced in the capacitor connected across the switches could be
as follows:
IC d ¼ C d
DV CE
0:5V PV
¼ Cd
Dt
T on
ð20Þ
ð16Þ
min
where Pout is the output power, D%Vin_min is the percentage of ripple
on the input voltage, Vin_min is the minimum input voltage (used for
worth case calculation), and x is the grid angular frequency.
Since the DC link capacitor buffers the energy at the freewheeling stage with high frequency and also the film capacitor is not
limited by the ripple current; hence it is advantageous to use some
low inductance film capacitors. Therefore, the use of a film
Fig. 7. Waveform of DIfactor at different modulation indexes highlighting the
maximum value.
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M. Islam, S. Mekhilef / Energy Conversion and Management 88 (2014) 854–862
where Cd = additional capacitor value, VCE = blocking voltage of the
switches, and Ton = turn-on time. By fixing the value of the parameters in (20), the additional current flowing through the switches
during the turn on transient time is calculated as Icd = 2.8A. Therefore, the additional switching losses during turn-on can be calculated by the Eq. (21) as:
W Cd ¼ C d
V 2PV F s
2
!
ð21Þ
where Fs is the switching frequency. From (21), the switching loss
due to the additional capacitor is calculated 0.832 W. Therefore,
the total switching loss for the two additional capacitors is 1.6 W.
Since the high frequency switches are replaced with MOSFETs
which reduces the switching losses considerably; hence the additional losses due to the added capacitors have very low impact on
the overall efficiency.
5.2. Test layout and control circuit
The experimental test layout is shown in Fig. 8, where modules
‘‘Leg1U’’, ‘‘Leg1L’’, ‘‘Leg2U’’, and ‘‘Leg2L’’ are the leg switches of the
conventional full-bridge inverter. Modules ‘‘DC Bypass’’ and
‘‘Clamping Branch’’ are selected based on the topology structure
of H5 and bipolar FB inverter. The measurement point of leakage
current is indicated in Fig. 8.
The control block of the proposed inverter is shown in Fig. 9,
where a maximum power point algorithm is not included. The grid
voltage is sensed and fed to a phase locked loop (PLL) to generate a
unity sinusoidal signal which is in phase with the grid voltage. A PI
current controller is used to control the output voltage. The output
of the PI controller is multiplied with the unity sinusoidal signal
resulting in the AC current reference. In the inner loop, the load
current is controlled by a PI controller.
5.3. Results
5. Simulation and experimental results
In order to verify the performance of the proposed improved
topology, a 1 kWp PV array is simulated in the MATLAB/Simulink
software environment, having the frame of panels connected to
the ground with the parasitic capacitance of 75 nF. Also, a 1 kW
prototype has been built and tested. The specifications of the prototype are listed in Table 1.
5.1. Specification and Project
(1) Semiconductors: By considering the maximum input voltage
given in Table 1 and a derating factor of 60% to maintain
high-level of safety, the switches S1 and S3 need to have a
minimum collector-emitter voltage VCE 900V. The minimum
current rating of the switches is 12 A. Very fast PowerMESH™ IGBT STGW30NC120HD (1200 V, 30 A) from STMicroelectronics were chosen as S1 and S3. On the other
hand, assuming the same derating factor, the switches S2,
S4, and S5 shall have collector–emitter voltage VCE of not less
than 500 V. The minimum current rating of these switches is
12 A. CoolMOS™ power MOSFET SPW47N60C3 (650 V, 47 A)
were chosen as the switches S2, S4 and S5.
(2) DC link capacitor: By applying the specifications in Eq. (16),
the value of the DC link capacitor is calculated as 400 lF.
The voltage rating is specified to be 600 V.
(3) Output filter: In Fig. 7, the maximum value of DIfactor is 0.25.
By considering the maximum ripple factor of 20% and applying the parameters in Eq. (18), the value of output filter
inductance is calculated approximately 6 mH. The cutoff frequency of the output filter is considered in the range
between 30 times of grid frequency and one-tenth the
switching frequency. The output filter capacitance is then
calculated in Eq. (19) and a value of 2.2 lF is used.
Fig. 10 shows the waveforms of VAN, VBN, and Vcm when the
switches’ junction capacitances are identical. The condition of
junction capacitance narrated in (13) for constant CM voltage is
not fulfilled. As a result, the CM voltage fluctuation is relatively
large. The simulated waveform shows the result VAN = VBN = 130 V
at the end of transient state for each commutation of non-decoupling modes to decoupling modes, and the CM voltage is fluctuating from 130 V to 200 V. The experimental results are similar to the
simulation results as shown in Fig. 10(b).
The experimental waveforms of VAN, VBN, and Vcm are presented
in Fig. 11 when the two additional capacitors of value 650 pF are
connected in parallel to the switches S2 and S4. As a result, the
simulation results presented in Fig. 11(a) show that the voltages
VAN = VBN = 200 V at the end of the transient period. Consequently,
the CM voltage remains constant at 200 V and the ground leakage
current is reduced significantly, since VAN and VBN are fully complementary in the switching periods. The experimental results are
DC Bypass
P
Ground current
measuring point
i pv
Leg1U
Cdc1
Leg2U
LA
A
V pv
N
Vg
Co
B
V AN
Cdc2
C pvg2
ig
Clamping
Branch
PV
V BN
Leg1L
LB
Leg2L
DC Bypass
C pvg1
ZG
i Leakage
Fig. 8. Test layout.
Table 1
Specifications of the prototype.
LA
Inverter parameter
Value
Nominal input voltage
Grid voltage/frequency
Rated power
Nominal AC current
Switching frequency
DC bus capacitor
Filter capacitor
Filter inductor LA, LB
PV parasitic capacitor Cpv1, Cpv2
Controller
380–550 VDC
240 V/50 Hz
1000 W
4.2 A
16 kHz
470 lF
2.2 lF
3 mH
75 nF
dSPACE 1104
VPV PV
Co
Power
Stage
Vg
Co
LB
SPWM
PI
sin
ig
+
iref
_
PI
Vref
θ
PLL
_ +
Fig. 9. Control block of the proposed topology.
860
M. Islam, S. Mekhilef / Energy Conversion and Management 88 (2014) 854–862
(a)
ig(5A/div)
Vg
200V/div
t=5ms/div
iLeakage
10mA/div
(b)
Fig. 12. Experimental waveforms of grid current ig, grid voltage Vg and leakage
current iLeakage.
160V
Fig. 10. Waveforms of VAN, VBN, and Vcm by applying unipolar SPWM when the
switches junction capacitances are identical: (a) simulated waveform and (b)
experimental waveform.
Fig. 13. Gate signal of the switches S1, S4, and S5 at (a) grid cycle and (b) PWM
cycle.
Fig. 11. Waveforms of VAN, VBN, and Vcm after adding two additional capacitors: (a)
simulated waveform and (b) experimental waveform.
completely in agreement with the simulation results which are
shown in Fig. 11(b). The RMS value of CM leakage current are measured 13.3 mA as shown in Fig. 12, even though the practical
switches junction capacitances are non-linear and challenging to
be matched accurately. This peak and RMS values are lower in
magnitude corresponding to the German standard VDE0126-1-1.
The gate signals across the switches S1, S4 and S5 during experiment are shown in Fig. 13 for the grid cycle and PWM cycle. It is
clear that the gate signals are in agreement with the theoretical
analysis made in Section 3.2 and the gate drive voltages are kept
constant at the desired level. The drain-source voltage of the MOSFET switches is shown in Fig 14 under symmetric transient condition. The switching voltages are clamped to the half of the input
voltage without any overstress. As a result, the switching losses
are reduced considerably.
As per Fig. 15, the inverter output voltage VAB has three levels as
VPV, 0, VPV. It indicates that the proposed topology employs unipolar SPWM and the DM characteristic is excellent. The grid-connected
current and voltage are also shown in Fig. 15. It is clear that the
proposed inverter can inject PV power into the utility grid with unity
power factor and lower harmonic distortion (THD = 2.54%) under
full load condition which is shown in Fig. 16. According to the IEEE
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M. Islam, S. Mekhilef / Energy Conversion and Management 88 (2014) 854–862
(a)
t=5ms/div
(b)
Fig. 14. Drain-source voltage waveform of the switches S2, S4, and S5 at (a) grid
cycle and (b) PWM cycle.
Std 1547.1™-2005 [29], the total harmonic distortion must be less
than 5%; thus, the power quality is well accepted. It can be seen from
Fig. 16 that the value of DC current injection is less than 0.5% of the
output current which meets the requirement of IEEE Std 1547.1™2005.
The experimental result of the system dynamic response under
different step load change is presented in Fig. 17. At point t1, the
load current is changed from 4.20 Arms (load resistor, R = 50 O;
output voltage = 215 Vrms) to 5.1 Arms (R = 42 O) until t2. At point
t2, the load current is again changed from 5.1 Arms to 5.95 Arms
(R = 36 O) until t3. In contrast, at point t3 and t4, the load current
is decreased to 5.1 Arms and 4.15 Arms, respectively. It can be clearly
seen that the fast and effective response of the load changes are
achieved without affecting the output voltage.
The efficiency comparison of the proposed, H5 and conventional
bipolar FB topologies are illustrated in Fig. 18. The YOKOGAWA
WT1800 precision power analyzer is used to measure the efficiency. Note that the presented efficiency diagram covers the total
switching losses and the output filter losses but it does not include
the losses for the control circuit. It can be seen that the efficiency of
the H5 and proposed topologies is almost same. Therefore, the
effect of additional capacitors on the efficiency is negligible. In contrast, the efficiency of the proposed improved topology is better
than the bipolar FB topology. The maximum efficiency of the proposed inverter is measured 98%. In the PV inverter, it is important
to achieve higher efficiency over a wide load range and this performance can be evaluated by the European efficiency which is
defined as follows [20]:
gEU ¼ 0:03g5% þ 0:06g10% þ 0:13g20% þ 0:10g30% þ 0:48g50%
þ 0:2g100%
ð22Þ
Vrms
irms
t2
t3
t1
t4
Fig. 15. Experimental waveforms of grid current ig, grid voltage Vg, and differential
voltage VAB.
Fig. 17. Experimental result of the system dynamic response under different step
load change.
Efficiency (%)
100
98
96
94
Proposed
92
H5
90
Bipolar FB
88
0
200
400
600
800
Grid-tied Power (P)
Fig. 16. Current harmonic distribution.
Fig. 18. Efficiency comparison curve.
1000
1200
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M. Islam, S. Mekhilef / Energy Conversion and Management 88 (2014) 854–862
Table 2
Performance comparison among proposed, H5, and conventional bipolar FB
topologies.
Parameters
Bipolar FB
H5
Proposed
PWM pattern
DM characteristics
CM voltage
Leakage current (mArms)
European efficiency (%)
Bipolar
Poor
Constant
16.8
95.06
Unipolar
Excellent
Floating
45.6
97.29
Unipolar
Excellent
Constant
13.3
97.45
The European efficiency of the proposed, H5 and bipolar FB
topologies are calculated 97.45%, 97.29%, and 95.06%, respectively.
It can be seen that the European efficiency of the H5 and proposed
topologies are almost identical, and better than conventional
bipolar FB inverter. Finally, the performance comparison among
these three topologies is summarized in Table 2. It is clear that
the proposed topology can combine the superior performance of
DM and CM characteristics with high efficiency.
6. Conclusions
In this paper, an improved transformerless inverter topology is
presented to reduce the CM leakage current and increase the efficiency. The operation modes of the improved topology and the
impact of junction capacitance of the switches on the CM voltage
are analyzed. The desired relationship among the junction capacitance is proposed which ensure not to produce the CM leakage
current because the condition of eliminating CM leakage is met
completely. Moreover, the three-level output voltage employing
unipolar SPWM is achieved in the proposed inverter with excellent
DM characteristics. No dead time is required at both the PWM
commutation and the zero crossing instant of grid cycle. Consequently, the higher quality and lower THD of the grid-connected
current are obtained. The efficiency of the inverter is measured
and compared with the conventional FB and H5 topologies. The
European efficiency is improved by replacing IGBTs with MOSFETs.
The maximum efficiency and European efficiency of the proposed
inverter are measured 98.0% and 97.45%, respectively. Therefore,
it can be concluded that the proposed inverter is very suitable
for grid-connected PV system.
Acknowledgements
The authors would like to thank the Ministry of Higher
Education of Malaysia and University of Malaya for providing
financial support under the research grant No.UM.C/HIR/MOHE/
ENG/16001-00-D000024.
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