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LETTER
IEICE Electronics Express, Vol.9, No.24, 1900-1905
A high-speed hybrid Full
Adder with low power
consumption
Kamran Delfan Hemmati1a), Mojtaba Behzad Fallahpour2,
Abbas Golmakani3, and Kamyar Delfan Hemmati4
1
Pouyandegan e danesh Institute of Higher Education
Roshd, Chalus 46617–53771, Iran
2
Young Researcher Club, Lahijan Branch, Islamic Azad University, Lahijan, Iran
3
Sadjad Institute of Higher Education
62 Jalale Ale Ahmad, Mashhad 4664–91375, Iran
4
Young Researcher Club, Chalus Branch, Islamic Azad University, Chalus, Iran
a) [email protected]
Abstract: In this paper a new high speed hybrid Full Adder with
low power consumption is presented. Furthermore, after determining
topology a proposed CAD (Computer Aided Design) with a proposed
multi objective genetic algorithm will be used to optimize the high
speed hybrid Full Adder. The size of generative Full Adder
transistors is introduced to algorithm as the inputs and the average
power consumption and max delay are introduced as the outputs.
After performing the algorithm, several results will be obtained as
they have no priority to each other, so designer can select whichever
according to his need. Simulation results show that, proposed
structure uses less average power. Algorithm program is written in
MATLAB and the circuit simulated by Hspice with 0.18 technology.
Keywords: a high speed hybrid Full Adder, inverter, power
consumption, multi objective genetic algorithm, non dominated
answers
Classification: Integrated circuits
References
© IEICE 2012
[1] K. Navi, M. R. Saatchi, and O. Daei, “A High-Speed Hybrid Full Adder,”
Eur J Sci Res, ISSN 1450-216X, vol. 26, no. 1, pp. 29–33, 2009.
[2] K. Navi, M. H. Moaiyeri, R. Faghih Mirzaee, O. Hashemipour, and B.
Mazloom Nezhad, “Two novel low-power full adders based on majority-not
gates,” Elsevier Microelectronics Journal, doi:10.1016/j.mejo.2008.08.020,
2008.
[3] K. Navi, R. Faghih Mirzaee, M. H. Moaiyeri, B. Mazloom Nezhad, O.
Hashemipour, and K. Shams, “Ultra high speed Full Adders,” IEICE
Electron Express, vol. 5, no. 18, pp. 744–749, 2008.
[4] E. Zitzler, “Evolutionary Algorithms for Multiobjective Optimization:
Methods and Applications,” PhD thesis, Swiss Federal Institute of
Technology, Zurich, Switzerland, 1999.
DOI: 10.1587/elex.9.1900
Received September 16, 2012
Accepted September 28, 2012
Published December 28, 2012
1900
IEICE Electronics Express, Vol.9, No.24, 1900-1905
1. Introduction
Full Adder is one of the most important parts of each processor which is
used in arithmetic logic unit (ALU). Increasing the performance of a 1-bit
Full Adder cell is very effective to increase performance of whole system
because the 1-bit Full Adder cell is a key building block of a logic unit in the
system. This is why many researchers are trying to present various
structures for 1-bit Full Adder and improve its performance [1].
After determining the circuit structure, finding the appropriate
amounts of constituent elements, has high significance. Although the size
of transistors can be obtained by using analytical equations but, after
simulating the circuit with this initial amounts desirable results will not be
obtained; mostly due to the approximate nature of relationship and failure
to consider non-linear effects in designing. At this stage, the designer can
change the values of circuit elements to achieve optimal conditions, which is
very difficult and time consuming because the output parameters are in
contrast with each other and the improvement of an index may cause
weakness of another one. Here the importance and necessity of using CAD
for designing become clearer.
In this paper a proposed CAD with a proposed multi objective genetic
algorithm is presented. In this CAD, no extra calculation is needed and
designer just determines the allowed range of parameter changes, to
increase the algorithm convergence.
This paper is organized as follow: a brief background of a high speed
hybrid Full Adder is given in section II. In section III, providing an
improvement in the circuit is presented. In section IV, Implementing of
Proposed CAD is presented and finally simulation and results given in
section V.
2. A high speed hybrid full adder
The Full Adder in Fig. 1-a, b has 16 transistors. Furthermore, 6 transistors
are used to generate the inverse inputs. carry is produced by majority
function and sum is produced by DCVS (Differential Cascade Voltage
Switch) technology. This Full Adder is described in reference [1] completely.
This kind of design has several advantages: first, the circuit works very fast
because the sum and carry are produced at the same time and in separate
circuits. Second, on the base of simulation results in [1], the Full Adder cell
© IEICE 2012
DOI: 10.1587/elex.9.1900
Received September 16, 2012
Accepted September 28, 2012
Published December 28, 2012
1901
IEICE Electronics Express, Vol.9, No.24, 1900-1905
Fig. 1. The Full Adder cell a) Sum, b) carry [1]. c)
Applying two new voltages to the tips of first
inverter. d) Suggested plan to reduce power
consumption of output of carry generative circuit
provides perfect voltage swing even at low supply source (Vdd = 1.5 volt) [1,
2, 3]. So we choose it for its perfect advantages but this circuit has a great
disadvantage. It consumes extra average power. For solving this problem,
we present an improvement in circuit structure to reduce power
consumption.
3. Providing an improvement in the circuit
© IEICE 2012
DOI: 10.1587/elex.9.1900
Received September 16, 2012
Accepted September 28, 2012
Published December 28, 2012
The simulation results of Fig. 1-a, b described in [1], show that despite the
high speed, Full Adder has not a proper PDP (Power-delay product),
because it consumes extra average power. Furthermore, a high percentage
of the total power consumption of Full Adder is used by generative circuit
of carry out, especially in its first inverter. In fact, x-node and y-node which
are input and output out of first inverter orderly, had not perfect zerological or one-logical in 6 positions of their 8 positions. In these 6 positions,
input-node of inverter differs about 0.8v in comparison with ideal amount.
Also output-node of inverter has distanced about 0.5v from one and zerological. So we can conclude that, the difference in level of input voltage and
the ideal states is the main reason of high power consumption, and reducing
these differences will lead to lower power loss. For this purpose we changed
the amount of Vdd and GND voltages, which are attached to up and down
of first inverter. As a result, we made one-ideal and zero-ideal closer to levels
of input voltage of the inverter. This is done by applying two new voltages
to the tips of the first inverter (Fig. 1-c). After finding suitable voltage
changes for two tips of the inverter, we observe that wastes of power reduce
considerably. But our plan encounters problem, because there may not be
such a voltage in our chip, and we also need to compare our suggested plan
with original structure in the same condition. So to provide the needed
voltage for mentioned places, we suggest following structure (Fig. 1-d).
With following considerations, finding proper sizes for transistors is a hard
and time-consuming task. Furthermore, we are not sure to obtain the best
answer. First: providing a proper voltage for two tips of inverter to
minimize the power consumption.
Second: maximuming optimal delay.
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IEICE Electronics Express, Vol.9, No.24, 1900-1905
We have used a proposed CAD that described in section 4, to gain the
mentioned goals. By this CAD, we can find proper size of transistors to
optimize multi objects at the same time. At first, we optimize the circuit in
reference [1] with this mentioned CAD, without any change in its topology
and better results will be found. This issue approves the good performance
of CAD, furthermore approves our idea, in which we claimed that obtaining
the ideal result by manual design and trial and error is hard and maybe
impossible. Then, we optimize the suggested circuits and compar the results.
4. Implementing of proposed CAD
Most of actual optimizing questions are naturally multi objective. To solve
this problem, many algorithms have suggested in recent years such as
“SPEA” and “NSGA2”. [4]. In this paper we have used two combined
algorithms, “SPEA” and “NSGA2”, the as follows:
First, we form a random primal N sized population. By using usual
operators of genetic algorithm other N members are made. Then all
members will be gathered in a new collection with 2N size. Here, a
non - dominated classification, similar to NSGA2 should be done. In
NSGA2, if the first rank numbers are more than N, the numbers that don’t
have a good crowding possibility, will be removed until they make balance
with N. But on this condition we act like SPEA. We keep these numbers
into external archives and avoid pruning them (This increases the speed of
algorithm convergence because most of the time proper answers that have
been achieved after several repetitions may be eliminated by pruning).
Among the archive members which have more crowding distance, it is
possibile to make next generation.
Flow chart of proposed multi objective genetic algorithm and the circle
of Hspice performance with Matlab (proposed CAD) are shown in Fig. 2-a
and Fig. 2-b. The meaning of optimization in this paper is finding the best
inputs (The size of generative Full Adder transistors and V) To obtain
the optimum power consumption and delay. Therefore, the fitness function
© IEICE 2012
DOI: 10.1587/elex.9.1900
Received September 16, 2012
Accepted September 28, 2012
Published December 28, 2012
1903
IEICE Electronics Express, Vol.9, No.24, 1900-1905
Fig. 2. a) Flow chart of proposed multi objective genetic
algorithm. b) The proposed CAD. c) Comparing
the results of optimizing in reference [1] and
suggested structure in this paper
in this optimization is minimizing power consumption and delay. The value
of power consumption and delay are calculated with Hspice software and
will be reported to MATLAB software. After that, according to these
reported values, the algorithm written in MATLAB find the appropriate
amounts of inputs and offers to Hspice for determining power consumption
and delay again. So the outputs of Hspice will be better in every iteration of
proposed CAD and thus we can approach the answer step by step. Since the
Hspice is used in this circle, all of the transistor parasitic effects such as
body effect, capacitors and etc are considered in our designing. To increase
the algorithm convergence speed, the allowed range of input parameters are
determined. The range in which sizes of the elements change is shown in
blue box of table I, to determine the range of searching optimization
Table I. The allowed range of input parameters and the
results of optimization (Each place in figure (2)
is an answer for a particular circuit = Answer1, 2,
3,.... c = Moscap transistor, W, L = length and
width of transistors)
© IEICE 2012
DOI: 10.1587/elex.9.1900
Received September 16, 2012
Accepted September 28, 2012
Published December 28, 2012
1904
IEICE Electronics Express, Vol.9, No.24, 1900-1905
algorithm.
As the circuit that makes Full Adder in this paper is made of two
separate circuits, each part is optimized separately. In this paper the length
of whole transistors assumed by 0.18 m except Moscap transistors. Each of
the capacitors that generate majority function are made by a Moscap
transistor. According to majority function, all of these capasitors have the
same capacity so the Moscap transistors have the same dimensions that will
be obtained in optimization. The numbers of population for both circuits
are 50 and algorithm will continue to 150 generations.
5. Simulation results
To compare the suggested circuit in this paper with reference circuit [1],
first of all, we have searched the optimal sizes of transistors to minimize
delay and power consumption without any changes in structure of the
reference circuit [1].
At the next stage, in addition to optimizing on transistors size, we used
algorithm to find the optimal amount of v (Fig. 1-c). In this condition the
power consumption is extremely reduced, so this condition is suitable for
those chips which have such voltages. The third point is optimizing
transistor size of suggested structure in this paper (Fig. 1-d). To compare
the structures better, the results of above optimizations are shown together
in one figure (Fig. 2-b). Each place in this figure is an answer for a particular
circuit. The answers don’t have any priority to each other, so the designer
can select each of them according to his need. By observing this figure we
realize that; suggested structure uses less power with respect to the
reference circuit [1], without further delay compared to it. For example, we
have compared above designs together in table I to design a Full Adder
with 80 ps max delay.
Conclusion
In this paper, a new high speed hybrid Full Adder with low power
consumption is presented. Furthermore, after determining topology, by
using a proposed CAD with a proposed multi objective genetic algorithm
the optimize size of transistors will be obtained. Simulation results confirm
that; suggested structure uses less power with respect to the reference
circuit [1], without further delay compared to it.
© IEICE 2012
DOI: 10.1587/elex.9.1900
Received September 16, 2012
Accepted September 28, 2012
Published December 28, 2012
1905