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Development of
I2C CONTROLLED DIGITAL TOSA (Transmitter Optical Sub Assembly) PACKAGE
For high speed telecommunication/networking/optical
communication or related electronics industry:
Zahid Khan1
Department of Electrical and Electronic
Engineering
Universiti Teknologi PETRONAS
Bandar Seri Iskandar
31750 Tronoh, Perak
[email protected]
Various
embodiments
of
optical
subassembly (OSA) such as transmitter optical subassembly
(TOSA), transistor outline (TO) packages, arrangements and
manufacturing for an electro-optical assembly are disclosed
here. This embodiment comprises an optical subassembly
(OSA) for an electro-optical assembly. An electro-optical
assembly comprises an optical semiconductor device, Printed
Circuit Board/Flex (PCB) and active electronic semiconductor
devices. Thus embodiments disclosed herein related is I2C
serial interface controlled Digital optical subassembly (DOSA) such as Digital transmitter optical subassembly (DTOSA),Digital transistor outline (D-TO) packages,
arrangements and manufacturing for an electro-optical
assembly & optoelectronic transceiver.
Abstract—
Keywords-component; TOSA, OSA, MPD, LD, I2C.
I.
INTRODUCTION
The purpose of development of
I2C CONTROLLED
DIGITAL TOSA ( Transmitter Optical Sub Assembly)
PACKAGE to present the invention relates generally to Fiber
optics/optoelectronic related technology. More specifically,
the present invention relates to Digitizing of optical
subassembly (OSA) and methods to replace Analog systems
of optical subassembly (OSA) to hybrid Digital systems of
optical subassembly (D-OSA) for accurate measurement, Fast
control, cheaper testing for manufacturing optoelectronic
devices.
The development of the Analog TOSA has been an
interesting topic among researchers and a lot of sophisticated
accurate measurement indeed had been developed all over the
world.
Prof Hisham2
Department of Electrical and Electronic
Engineering
Universiti Teknologi PETRONAS
Bandar Seri Iskandar
31750 Tronoh, Perak
[email protected]
II.
LITERATURE REVIEW IN DETAIL
A. BACKGROUND
This invention relates to a TO & TOSA( Transmitter
Optical Sub Assembly) systems & more particularly to a
laser-diode & photo-diode used in optical transceivers and
other applications like optoelectronic equipments used for
optical communication networking industry and related field.
The sourcing of light intensity by means of laser diode and
sensing of light intensity by means of photo diodes normally
requires the use of current source & current measurement
circuits. These current source & current measurement circuits
are placed externally on the printed circuit boards of optical
transceivers and similar devices for facilitating transmission
and reception of digital data through optical signals over
optical fiber cables. Also in optical communication
networking, it is often desirable to use modular
electrical/optical components to reduce manufacturing costs. It
is common to use electro-optical assemblies to transmit &
receive optical signals over optical fibres. Typical electrooptical comprises various modular components combined in a
package assembly. For example a TOSA (typical electrooptical assembly comprises a transmitter optical sub assembly),
a ROSA( receiver optical sub assembly ) and an electronic sub
assembly. The TOSA generally comprises a light source for
transmitting optical signal and control circuitry for biasing the
laser and modulating the light source according to an input
digital data signal from the electronic sub assembly. The
ROSA generally comprises a photo-diode for detecting optical
signal and sensing circuitry for converting the optical signal to
digital signal provided to the electronic sub assembly. Both
TOSA & ROSA are typically formed in a sub assembly having
analog electronic sub assembly and plug type receptacles for
optically connecting to an optical fibre or fibre optic
connectors.
D-TO & D-TOSA packages manufacturing, characterized,
calibration and diagnostic can be performed digitally which is
more accurate, faster & cheaper. D-TOSA package can be
mounted on the mini multilayer PCB to form optoelectronic
transceiver or any related product. It is accordingly an object of
present invention to provide a simple D-TO Packages. It is
another object to present invention to provide a simple,
cheaper optoelectronic transceiver in the datacom / Telecom
industry. it is yet a further object of this invention to provide an
integrated circuit including TO packages.
detection sites simultaneously. The efficiency of such a scheme
can obviously exceed that of the unfocused case, provided that
the optical elements have suitable efficiency. However, the
disadvantage of the focused interconnect technique is the very
high degree of alignment precision that should be achieved and
maintained to ensure that the focused spots are the appropriate
places on the chip.
B. Methodology (Experimental)
An Optical communication system is similar in basic
concept to any type of communication system. The function of
a general communication system is to transmit the signal from
the information source through the transmission medium to the
destination. A block diagram of a typical optical interconnect
system is shown in Figure 2.1
Figure 1. A block diagram of a typical optical communication system
It consists of a transmitter, optical source, optical media,
optical detector, and a receiver. At the transmitter, the
information source provides electrical signal to a transmitter
circuitry and it drives an optical source such as a laser and a
LED to give modulation of the light wave carrier. The optical
source converts electrical signal to optical signal and the light
output is propagated through the optical media such as optical
fiber and free space. The light signal from the optical media is
collected on an optical detector such as avalanche photo diodes
and p-i-n photo diodes and converted to the electrical signal.
Finally, the electrical signal is amplified and recovered by the
optical receiver.
For optical interconnects, optical transmission media is
categorized into free space, optical fibers, and integrated
optical waveguides [1]. The difficulties associated with the
fiber-optic approach stem from the alignment requirements for
the fibers and detectors. Also, the fibers cannot be allowed to
bend too much since bends cause radiation losses. In
waveguide approach, the difficulties lie on the requirement to
efficiently couple into and out of the guides. Careful alignment
of the sources with the integrated waveguides is required.
The other major category of optical interconnects is freespace techniques which light is propagated in the free space.
Free-space interconnects can be distinguished between two
types of techniques, unfocused [37] and focused [38-40].
Unfocused interconnections are established simply by
propagating the optical signals to the entire electronic chip.
However, the system is very inefficient since only a small
fraction of the optical energy might be absorbed on the
photosensitive areas of the detectors and the rest is wasted.
Therefore, inefficient use of optical energy may result in
requirements for the extra amplification of the detected signals
on the chip. In focused interconnections, the optical source is
actually imaged by an optical element onto a multitude of
Figure 2. The light output versus current characteristic of Laser and LED
There are two broad kinds of lasers, edge emitting lasers
and vertical cavity surface emitting lasers (VCSELs). VSCEL
has been interested because it has low threshold current and a
symmetric output for efficient optical coupling to the fiber.
However, it has shortcomings including small lifetime, high
cost and short wavelength because of the lack of mirrors for 1.3
to 1.55 μm. 1.3 to 1.55 μm wavelengths has been of interest for
fiber optic communication since the optical fiber has zero
dispersion near the 1.3 μm wavelength and has lower loss near
1.55 μm wavelength although 0.85 μm range is still useful
since the wavelength is compatible with on-chip Si detectors.
Several kinds of structure have been developed such as Gainguided lasers, Index guided lasers, and Quantum-well lasers for
edge emitting lasers. The simplest and least expensive laser is
the double heterostructure Fabry-Perot (DH FP) laser.
However, the modulation bandwidth is limited by relaxation
oscillations which is the oscillation between the carrier and
photon population when the current is suddenly increased. In
addition, it shows frequency chirp which is the critical for long
haul communication due to fiber dispersion. For long haul
communication, distributed feedback (DFB) lasers has been
developed with single frequency operation. The structure is the
distributed Bragg diffraction grating which provides frequency
selective feedback in the optical cavity. For the high-speed
communication faster than 10 Gbps, lasers cannot be used with
direct modulation due to chirp but they can be used with
external modulator such as electro-absorptive modulator and
mach-zehnder modulator. As a result, the optical source should
be selected carefully in terms of the application area.
III. RESULTS AND DISCUSSION
In this section, main part of the Electronic design of system
is reviewed named as Laser Diode Driver with I2C controlled
Circuit Design which drives optical sources and generate light
signal related to the driving current.
A. GENERAL DESCRIPTION
Laser diode driver:
The A3907 is heart of the circuit and is ideal for driving
low power laser diodes. It operates from 2.3 to 5.5 V, so is
compatible with Li+ battery operation. It is WLCSP package
for minimum footprint,Ramp control circuit,10-bit D-to-A
converter,100 μA resolution with capable of peak output
currents to 102 mA,Low voltage I2C serial interface, Low
current draw sleep mode-active low, Internal circuit protection
includes thermal shutdown with hysteresis, fly back clamp
diode.
flows through the laser diode. The pin is active High.
High = LD current flowing to set point. LO = LD
current attenuated. The input is TTL compatible.

DELAYED / SLOW START:-Once power is applied,
current at the attenuated level will flow (~100-500nA
when configured with Power Up Delay of 10uSec).
After 10usec, current will rise to the level dictated by
the set point (Resolution Target 100uA/LSB), I_out =
DAC * 100uA …..where DAC = 1 to 1023. This delay
of 39uS ensures that all control electronics are
functioning before significant current flows to the laser
diode. The delay time is set with internal components.
Typical Delayed / Slow Start typical sequence

OUT PUT PROTECTION:-Clamp Diode. When the
output is turned off the load inductance will cause the
output voltage to rise. A clamp diode, from IOUT to
VDD, is integrated in the IC to ensure the output
voltage remains at a safe level.

B. OPERATION
 RESET / ENABLE FUNCTION:-For Standby Mode
Control,pin SLEEPZ. A logic low input will disable all
of the internal circuitry and prevent the IC from
draining battery power. When low, this pin attenuates
the output current amplitude to near zero (~500nA
when configured up to 100 mA max.) Current still
VS & VDD:-Headroom. The current may not reach the
programmed level if there is not adequate headroom in
the output circuit. The IC output voltage must be over
350mV to guarantee normal linear operation. Vdd,
Iload, Rload can be adjusted to ensure the device
operates in the linear range. When the below equation
is not satisfied the load current will be limited by the
series impedance and may not reach the programmed
level.
VDD(min) – Rload (max)*Iout(max) >= 350mV
Iout Errors Defined
Relative accuracy (INL): This error is calculated by
measuring the worse case deviation from a straight line defined
from endpoints. The straight line endpoints are defined by the
actual measured values at code=63 and code= 1023. See Figure
A.
Differential nonlinearity (DNL): A measure of the
monotonicity of the DAC. The slope of the line must always be
positive for each incremental step.
DNL = [Iout(n+1) - Iout(n)]/LSB -1 LSB (n = 64 to 1023)
the A3907 (slave). The clock input to SCL is generated
by the master, while SDA functions as either an input
or an open drain output, depending on the direction of
the data. The I2C input thresholds do not depend on
the VDD voltage of the A3907. The levels are fixed at
approximately 1V. The fixed levels allow the
SDA/SCL lines to be pulled up to a different logic
level than the VDD supply of the 3907.
Timing Considerations-The control sequence of the
communication through the I2C interface is composed of
several steps in sequence:
1. Start Condition. Defined by a negative edge on the SDA
line, while SCL is high.
2. Address Cycle. 7 bits of address, plus 1 bit to indicate write
(0) or read(1), and an acknowledge bit. The address setting is
0x18, 0x1A, 0x1C or 0x1E.

OPERATION AS DRIVERS:-
Offset error:The measured output current at input code=64
compared to the ideal value according to the transfer function
(6.4mA).
Gain Error:The difference in the slopes of the ideal transfer
function and the actual transfer function. The gain error is
calculated by subtracting out the offset error at code 16 from
the actual transfer function. This calculated value is compared
to the ideal transfer function and reported as a percentage of the
ideal full scale value (102.3mA). See Figure B.
Gain Error Drift:Change in slope of the transfer function due
to temperature,expressed as LSB/C.
3. Data Cycles. Write - 8bits of data addressing internal
control register, followed by an acknowledge bit.
4. Stop Condition. Defined by a positive edge on the SDA
line, while SCL is high.
Except to indicate a Start or Stop condition, SDA must
be stable while the clock is high. SDA can only be changed
while SCL is low. It is possible for the Start or Stop condition
to occur at any time during a data transfer. The A3907 always
responds by resetting the data transfer sequence. The
Read/Write bit is set to low, to indicate a write cycle. Multiple
writes are allowed. If desired, the read back bit can be set to
“1” to check what was last written. The Acknowledge is used
by the master to determine if the slave device is responding to
its address and data. When the A3907 decodes the 7-bit address
field as a valid address, it responds by pulling SDA low during
the ninth clock cycle. During a data write from the master, the
A3907 pulls SDA low during the clock cycle that follows the
data byte, in order to indicate that the data has been
successfully received. In both cases, the master device must
release the SDA line before the ninth clock cycle, in order to
allow this handshaking to occur.
C. Equations Adjust the set point current:
The A3907 output current is controlled by programming
the DAC value via the I2C serial port. The target output current
can be calculated by:
I_out = DAC * 100uA …..where DAC = 1 to 1023
Code = 0 is a disable state for the output sink drive. The
DAC will be set to code = 0 upon power up or fault condition
on VDD.

I2C OPERATION FOR DRIVER:-I2C Interface.
This is a serial interface that uses two bus lines, SCL
and SDA, to access the internal Control registers. Data
is exchanged between a micro-controller (master) and
Photo diode Monitoring :
be transferred at rates up to 100k/s in the standard mode and up
to 400k/s in the fast mode. The VCC power should not be
removed from the device when the I2C bus is active to avoid
loading the I2C bus lines through the internal ESD protection
diodes.
Each device on the I2C bus is recognized by a unique address
stored in that device and can operate either as a transmitter or
receiver, depending on the function of the device. In addition
to transmitters and receivers, devices can also be considered as
masters or slaves when performing data transfers. A master is
the device which initiates a data transfer on the bus and
generates the clock signals to permit that transfer. Devices
addressed by the master are considered a slave. The address of
the LTC2451 is 0010100.
MEASURMENT OF PHOTO CURRENT:
The reverse bias across the photo diode is held at a low
value for small input currents to minimize dark current. The
VSET voltage of ADL5315 increases in a linear manner at the
higher input currents to maintain accurate photo diode
responsivity. The LTC2451 uses a single 2.7V to 5.5V supply,
accepts a single-ended analog input voltage from AD8305 and
communicates through an I2C interface.
The LTC2451 can only be addressed as a slave. It can only
transmit the last conversion result. The serial clock line, SCL,
is always an input to the LTC2451 and the serial data line,
SDA, is bidirectional. Figure 2 shows the definition of the I2C
timing.
The START and STOP Conditions:A START (S) condition
is generated by transitioning SDA from HIGH to LOW while
SCL is HIGH. The bus is considered to be busy after the
START condition. When the data transfer is finished, a STOP
(P) condition is generated by transitioning SDA from LOW to
HIGH while SCL is pulled HIGH. The bus is free after a STOP
is generated. START and STOP conditions are always
generated by the master.
When the bus is in use, it stays busy if a repeated START (Sr)
is generated instead of a STOP condition. The repeated
START (Sr) conditions are functionally identical to the
START (S).
IV.

I2C OPERATION FOR ADC.
Input Voltage Range: Ignoring offset and full-scale errors, the
converter will theoretically output an “all zero” digital result
when the input is at VREF– (a zero scale input) and an “all
one” digital result when the input is at VREF+ (a full-scale
input). In an underrange condition, for all input voltages less
than the voltage corresponding to output code 0, the converter
will generate the output code 0. In an overrange condition, for
all input voltages greater than the voltage corresponding to
output code 65535, the converter will generate the output code
65535.
I2C INTERFACE: The LTC2451 communicates through an
I2C interface. The I2C interface is a 2-wire open-drain
interface supporting multiple devices and masters on a single
bus. The connected devices can only pull the data line (SDA)
LOW and never drive it HIGH. SDA is externally connected to
the supply through a pull-up resistor. When the data line is free,
it is pulled HIGH through this resistor. Data on the I2C bus can
CONCLUSION
This paper has set out the framework for the development
of I2C CONTROLLED DIGITAL TOSA ( Transmitter Optical
Sub Assembly) PACKAGE system through discussions on
important technical aspects such as Laser mechanism,
monitoring photo sensing schemes and control algorithms. The
plans outlined in the text will be executed in the next phase of
the study.
ACKNOWLEDGMENT
The authors express their gratitude to Universiti Teknologi
PETRONAS (UTP) for the facilities provided to carry out this
work.
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