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Fakulti:
FAKULTI KEJURUTERAAN ELEKTRIK
Semakan
Tarikh Keluaran
Pindaan Terakhir
No. Prosedur
Nama Matapelajaran: Makmal Mikrolelektronik
Kod Matapelajaran : SKEL 4722
:1
: 2014
: 2014
: PK-UTM-FKE-(0)-14
SKEL 4722
FAKULTI KEJURUTERAAN ELEKTRIK
UNIVERSITI TEKNOLOGI MALAYSIA
KAMPUS SKUDAI
JOHOR
MICROELECTRONICS LABORATORY
Characterization of deep submicron n-channel
MOSFET using TCAD Tools
Disediakan oleh
Nama
: Pensyarah
: Dr. Suhaila Isaak
Disahkan oleh : Ketua Jabatan
Nama
: Dr. Shaikh Nasir b. Shaikh
Husin
Tandatangan
Cop
:
:
Tandatangan
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:
Tarikh
: 11 September 2014
Tarikh
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1. Introduction
As the Integrated Circuits (IC) industry advances into the ULSI era, use of modeling
tools for sub-micron devices has become part and parcel in building up process
architectures. The conventional “trial and error” approach in experimenting with process
and device design is both expensive and time-consuming. Over the past decades, the
MOSFET has continually been scaled down in size, typical MOSFET channel lengths
were once several micrometers, but today’s integrated circuits are incorporating
MOSFETs with channel lengths of about a tenth of a micrometer. Transistor scaling, in
practice, has not followed exactly the constant E-field scenario. For performance reasons
and due to product requirements, scaling of supply voltage did not happen as fast as
geometrical scaling, such as gate length and gate oxide thickness. In addition, this may
influence the non-ideal effect of a MOSFET design such as short channel effects.
For a fully integrated modeling system, a virtual semiconductor device undergoes
processes like ion implantation, diffusion, etching etc.,to form the MOSFET device
structure. This finished “product” is then exported into a device simulator to “test” its
electrical functionality. After the parameter extraction, SPICE simulation can be activated
to simulate at circuit level, where the devices are connected through interconnects. In this
simulation exercise, the subject of interest is that of the process flow of a typical n-MOS
device and its impact on the electrical characteristics of the device.
2. Theory
2.1 MOS transistor device characteristics
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Figure 1: MOS transistor structure showing three dimensional view
From Figure 1, it can be seen that a MOS transistor is essentially a MOS structure with
two overlapping pn junctions on either side of the gate. For a MOSFET device, there are
basically 4 regions of operation: linear, saturation, breakdown and cut-off as shown in
Figure 2.
2.2 Linear Region
This is the region in which Ids increases linearly with Vds for a given Vgs. Ids can be
expressed as:
(1)
Where µ is the mobility of the carriers in the channel, COX is the gate oxide capacitance
per unit area, W/L is the device width-to-length ratio, and Vth is the threshold voltage.
2.3 Saturation Region
From Figure 2(1), it can be seen that Ids no longer increases linearly, as Vds increases to
higher values. Ids in the saturation region can be expresses as:
(2)
showing the independence of Ids on Vds.
2.4 Breakdown Region
This occurs at high values of Vds and is characterized by a super-linear increase of Ids
with increasing Vds. This may occur due to punchthrough or avalanche breakdown.
2.5 Cut-off Region
This occurs at very low values of Vgs (<Vth) and is characterized by extremely low Ids.
The gate IV characteristics are also shown in Figure 2(ii).
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(i)
(ii)
Figure 2 (i) Typical enhancement MOSFET drain current (Ids) drain voltage (Vds) characteristics
with gate voltage (Vgs) as a parameter, showing different regions of device operation; (a) linear,
(b) saturation, (c) cut-off, and (d) breakdown regions
(ii) Typical MOSFET transfer characteristics showing all regions of device operation
3. Short Channel Effects (SCEs)
The gate voltage controls most of the space charge induced in the channel area of a long
channel device during inversion. MOSFET scaling developments are forced to face the
challenges of short channel effect (SCE). SCE is one of the most critical problems of
deep submicron MOSFET devices. SCE has become the main technological barrier as a
MOSFET is scaled down approaching nano scale region. It has caused performance
degradation and altered the electrical characteristics of a device and summarized as
follow threshold voltage roll-off, drain induced barrier lowering (DIBL), voltage
saturation, punch through effect, etcs.
4. Threshold voltage roll-off (VT)
Threshold voltage roll off is defined as the reduction of threshold voltage with shrinking
channel length. The amount of the charges in the channel region control by the gate will
be affected the threshold voltage (VTH). VTH will be shifted negative direction as the
channel length decreases. This VT roll off is typically measured in mV/nm.
5. Punchthrough
When a small Vgs (<Vth) is applied and Vds =0, the device is off as there exists an energy
barrier between the source and the region under the gate. This is the barrier that holds the
electrons in the source, stopping any substantial current flow. As both the source and
drain are at the same potential, the space-charge depletion width at the source and drain
ends are symmetrical (note: dashed line a in Figure 3).
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If Vds is increased with Vgs held constant, then the drain depletion region starts to spread
towards the source region. This means that the depletion edge of the drain comes closer
to the source (note: dashed line b in Figure 3). Eventually when Vds is increased further, a
point will be reached when the drain depletion edge touches the source depletion edge
resulting in lowering of energy barrier of the source (note: dash-dot line c in Figure 3).
The result is that there will be a large current flow even though the gate has been biased
to turn the device off. This means the gate loses control over the drain current and the
device fails to function normally. This is called the punchthrough phenomena and the
corresponding induced current is termed punchthrough current.
Figure 3: Illustration of punchthrough phenomena in a MOSFET
Punchthrough causes source/drain breakdown in short-channel devices. The
characteristics are shown in Figure 4. When the device is in punchthrough, the drain
current increases superlinearly with the drain voltage even at gate voltages below the
threshold voltage.
Figure 4: MOSFET Output characteristics showing punchthrough phenomena DIBL
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6. Drain Induced Barrier Lowering (DIBL)
Drain induced barrier lowering or DIBL is a secondary effect in MOSFETs and originally
referring as a reduction of threshold voltage of the transistor at higher drain voltages. For long
channel devices, the gate is completely responsible for depleting the semiconductor. However,
parts of the depletion in short channel devices are performed by the drain and source bias. Hence,
less gate voltage is required to MOS transistor depletion. The reduction in channel length would
decrease the barrier for electron injection from source to drain. This phenomenon is known as
drain induced barrier lowering (DIBL).
In Figure 5 it is found that the threshold voltage is reduced at higher drain voltage. The DIBL can
be defined as the difference between threshold voltage (VTH) divided by the drain to source
voltage, VDS. As channel gets shorter, the effect gets more pronounced and referred as DIBL. VTH
decrease at large VDS and the gate has reduced control over the channel current.
DIBL can be calculated by the following formula (refer to Figure 6):
𝐷𝐼𝐵𝐿 =
∆𝑉𝑇𝐻
∆𝑉𝑑
Figure 5: DIBL effects
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Figure 6: I-V plotted graph
7. Subthreshold Leakage Current
A MOSFET operates in the weak inversion (subthreshold) region when the magnitude of
the gate-source voltage is less than the magnitude of the threshold voltage. In the weak
inversion mode, current conduction between the source and the drain (the substreshold
leakage current) is primarily due to diffusion of the carriers. The transistor off-state
current (IOFF) is the drain current when the gate to source voltage is zero. IOFF is affected
by the threshold voltage, channel length, channel width, depletion width beneath the
channel ara, channel/source doping profiles, drain/source junction depths, gate oxide
thickness, supply voltage and the junction temperature. Figure 7 (i) shows the drain
current (IDS) versus gate voltage (VGS) and Figure 7 (ii) shows the log IDS-VGS.
(i)
(ii)
Figure 7: (i) IDS-VGS plotted graph
(ii) inverse IDS-VGS shows the subtreshold slope
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The threshold voltage of a MOSFET is reduced with decreasing channel length. The
effects of scaling the channel length on the threshold voltage and subtreshold leakage
current characteristics of a MOSFET are called short channel effects (SCEs). As with
respect to the gate voltage is approximately linear in subtreshold region. The subtreshold
slope, S (mV/decade) can be evaluated by choosing two points in the subthreshold region
of an ID-VGS plotted graph such that the subthreshold leakage current changes by a factor
of 10.
Subthreshold slope defines the inverse slope of log (ID) versus VGS plotted graph, as
shown in Figure 8. The typical value of subthreshold slope is 60 mV/decade. A device
characterized by steep subthreshold slope exhibits a faster transient between off-on states.
Subthreshold slope can be evaluated by equation 4.
𝑆𝑢𝑏𝑡ℎ𝑟𝑒𝑠ℎ𝑜𝑙𝑑 𝑆𝑙𝑜𝑝𝑒 =
∆𝑉𝐺𝑆
𝑙𝑜𝑔∆𝐼𝐷
Figure 8: Subthreshold Slope Calculation
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9.
Problem
A group of trainee engineer in Hannah I.C Design are required to fabricate a short
channel MOSFET at atomic size by early 2014. They have assigned you to establish a
physical device simulation on n channel MOSFET by considering deep submicron
device. The structure design must be implemented using the Silvaco (Athena-Atlas)
as a process and device simulation tool. Therefore, you are required to familiarize
yourselves with Silvaco in order to complete the task. All given the reference parameters
for device structure as given in Attachment 1 (Flow of an n channel MOSFET Process
Simulation) and Attachment 2 (ATHENA command) and Table 1 (Attachment 3).
Triggers/Approach:


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


Learn and understand the use of Silvaco's TCAD software
Create an initial device design using reference material (Appendix 1 and 2)
Identify the device structure and physical parameters
Vary device parameters and study resulting effects upon performance
Determine optimal values for each device parameter
Combine the optimal parameters into a final, fully optimized device
The following instructions are issued to make sure your task is aligned with their
expectation.
The I-V characteristics should be performed to investigate the effectiveness of the
advanced method in order to prevent the varying of threshold voltage or short channel
effect of a MOSFET device.The most common effect that generally occurs in the short
channel MOSFETs are channel modulation, drain induced barrier lowering (DIBL),
punch-through and hot electron effect. Several advanced method such as lightly-doped
drain (LDD), halo implant and retrograde well can be applied to reduce the short
channel effects.
Report should be submitted on the 5th week of the lab session to the lab technician,
Mr. Helmy.
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