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318-595 Electronic Design
Digital Design
Jeff Kautzer
Univ Wis Milw
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Programmable Logic
• PLD: Programmable Logic Device
– Typically has defined routing and deterministic function delays.
– Smaller and less complex than other forms
• FPGA: Field Programmable Gate Array
– Routing and ultimate function delay is part of the design process
– Complex array of central logic block functions and peripheral I/O
functions amidst block-block routing resource
– Embedded functions available such as CPU’s (Ex. Altera NIOS)
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Basic Sum-of-Products PLD architecture
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PLD Connection Nomenclature
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Blank PROM
Programmed
Architecture
PROM
Architecture
Comparison of PROM Architecture (Fixed AND, Programmable OR)
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Simple PLD Architecture (Programmable AND, Fixed OR)
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Routing Resource
Simple FPGA Architecture (Central Logic Block Array, Peripheral I/O Blocks)
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Example:
Xilinx Virtex II
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Inside the Conf Logic Block
Virtex II Series
Facts:
1: Each FPGA capable of having 11668 CLB
2: Each CLB has 4 Slices
3: Each Slice
- 2 Functional Generators
- Arithmetic Login Block
- Large Multiplexers
- Fast carry look ahead chain
- Horizontal chain of OR gates
4: Functioning at 420MHz
5: 3Mb RAM
6: 12 Digital Clock Managers
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Different HDL Options
VHDL
Verilog
ADA like syntex and lots of redundancy
(can provide more flexibility)
C like syntex. Built-in types and logic
representations.
Design is composed of entities and are
different for different architectures.
Design is composed of modules (functions).
Much easier to learn.
Harder to learn and complex.
More cumbersome test bench design.
Much stronger test bench design.
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VHDL Basics
Very High Speed Integrated Circuit (VHSIC) Hardware Description Language
IEEE Std 1076.1 (VHDL87 & VHDL93)
Required by DOD for all ASIC designs
• Designs are generally captured in modules which have 2 parts;
•Entity Description - Blackbox description including all inputs
and outputs
• Architecture Description - Describes the internal signals and
overall relationship of entity inputs to outputs
Best learned by studying examples and not formal language rules
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Example - 8 bit comparator
VHDL keywords and library options are in bold
Comments follow “--”
8
x
z
8
y
library ieee;
use ieee.std_logic_1164.all;
entity jeff is
port (x, y: in std_logic_vector (7 downto 0);
z: out std_logic);
end jeff;
architecture john of jeff is
begin
z <= ‘1’ when x = y else ‘0’;
end john;
-- 1 Use IEEE standard library
-- 2 Use IEEE standard data type
-- 3 entity description, black box name is “jeff”
-- 4 input pin description, 2 eight bit variables, x & y
-- 5 output pin z, single bit
-- 6 end of entity description
-- 7 separate name for architecture is “john”
-- 8 keyword
-- 9 z is “assigned” the value 1 if x = y, else z = 0
-- 10 end of architecture
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Example - 4:1 Multiplexer
VHDL keywords and library options are in bold
Comments follow “--”
mux0
mux1
zout
mux2
mux3
2
ssel
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Example - 4:1 Multiplexer
VHDL keywords and library options are in bold
Comments follow “--”
library ieee;
use ieee.std_logic_1164.all;
entity jeffs_mux is port
(mux0, mux1, mux2, mux3: in std_logic;
ssel: in std_logic_vector (1 downto 0);
zout: out std_logic);
end jeffs_mux;
architecture jeffs_mux of jeffs_mux is
begin
with ssel select zout <=
mux0 when “00”,
mux0 when “01”,
mux0 when “10”,
mux0 when others;
end jeffs_mux;
-- 1 Use IEEE standard library
-- 2 Use IEEE standard data type
-- 3 entity description, black box name is “jeffs_mux”
-- 4 input pin description, Four input signals, mux0-3
-- 5 input pin description, 2 bit selection signal “ssel”
-- 6 output pin zout, single bit
-- 7 end of entity description
-- 8 can have same name for entity and architectures
-- 9 keyword
-- 10 VHDL construct called “with, select, when”
-- 11 select mux0 with ssel = 00
-- 12 select mux1 with ssel = 01
-- 13 select mux2 with ssel = 10
-- 14 select mux3 with ssel = 11 or all other possible
-- 15 end of architecture description
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Example - 4:1 Multiplexer
VHDL keywords and library options are in bold
Comments follow “--”
mux0
mux1
mux2
mux3
2
zout
library ieee;
use ieee.std_logic_1164.all;
entity jeffs_mux is port
(mux0, mux1, mux2, mux3: in std_logic;
ssel: in std_logic_vector (1 downto 0);
zout: out std_logic);
end jeffs_mux;
architecture jeffs_mux of jeffs_mux is
begin
with ssel select zout <=
mux0 when “00”,
mux0 when “01”,
mux0 when “10”,
mux0 when others;
end jeffs_mux;
-- 1 Use IEEE standard library
-- 2 Use IEEE standard data type
-- 3 entity description, black box name is “jeffs_mux”
-- 4 input pin description, Four input signals, mux0-3
-- 5 input pin description, 2 bit selection signal “ssel”
-- 6 output pin zout, single bit
-- 7 end of entity description
-- 8 can have same name for entity and architectures
-- 9 keyword
-- 10 VHDL construct called “with, select, when”
-- 11 select mux0 with ssel = 00
-- 12 select mux1 with ssel = 01
-- 13 select mux2 with ssel = 10
-- 14 select mux3 with ssel = 11 or all other possible
-- 15 end of architecture description
ssel
•Single quotes used when describing the value assignment to a std_logic type variable
•Double quotes used when describing the value assignment to a std_logic_vector type variable
•The IEEE std_logic type specifies 9 (nine) possible values including ‘0’, ‘1’, ‘Z’ (high impedance), ‘-’ (don’t care)
among others (not discussed in this basic intro)
•Each bit therefore has 9 possible values, A 2 “bit” variable actually has 2 9 = 81 possible states
•“with-select-when” construct useful only if one signal is assigned based on values of input. Another construct called
“case-when” inside of a process statement can be used if more than one signal needs assignment.
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Example - 4 bit D type latch
VHDL keywords and library options are in bold
Comments follow “--”
4
data
x
D Latch
4
q
aclk
reset
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Example - 4 bit D type latch
VHDL keywords and library options are in bold
Comments follow “--”
library ieee;
-- 1 Use IEEE standard library
use ieee.std_logic_1164.all;
-- 2 Use IEEE standard data type
entity jeffs_flop is port
-- 3 entity description, black box name is “jeffs_flop”
(aclk, reset: in std_logic;
-- 4 input pin description, clock and reset pins
data: in std_logic_vector (3 downto 0);
-- 5 input pin description, 4 D type inputs
q: out std_logic_vector (3 downto 0));
-- 6 output pin description, 4 latch outputs, q3 - q0
end jeffs_flop;
-- 7 end of entity description
architecture jeffs_flop of jeffs_flop is-- 8 can have same name for entity and architectures
begin
-- 9 keyword
p1: process (aclk, reset) begin
-- 10 VHDL process construct called “if-then”
if reset = ‘0’ then q <= (others => ‘0’);
-- 11 q is assigned ‘0’ when reset = 0
if rising_edge (aclk) then q <= data;
-- 12 q is assigned ‘data” when, reset = 1 and clocked
end if;
-- 13 end of “if” cases
end process;
-- 14 end of VHDL case-when
end jeffs_flop;
-- 15 end of architecture description
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Example - 4 bit D type latch
VHDL keywords and library options are in bold
Comments follow “--”
4
data
x
D Latch
aclk
4
q
library ieee;
use ieee.std_logic_1164.all;
entity jeffs_flop is port
(aclk, reset: in std_logic;
data: in std_logic_vector (3 downto 0);
q: out std_logic_vector (3 downto 0));
end jeffs_flop;
architecture jeffs_flop of jeffs_flop is
begin
p1: process (aclk, reset) begin
if reset = ‘0’ then q <= (others => ‘0’);
if rising_edge (aclk) then q <= data;
end if;
end process;
end jeffs_flop;
-- 1 Use IEEE standard library
-- 2 Use IEEE standard data type
-- 3 entity description, black box name is “jeffs_flop”
-- 4 input pin description, clock and reset pins
-- 5 input pin description, 4 D type inputs
-- 6 output pin description, 4 latch outputs, q3 - q0
-- 7 end of entity description
-- 8 can have same name for entity and architectures
-- 9 keyword
-- 10 VHDL process construct called “if-then”
-- 11 q is assigned ‘0’ when reset = 0
-- 12 q is assigned ‘data” when, reset = 1 and clocked
-- 13 end of “if” cases
-- 14 end of VHDL case-when
-- 15 end of architecture description
reset
•VHDL Process construct used to embody an algorithm, starts with a label, “p1”
•Process contains “sensitivity” list which contains all signals that can possible cause the value of output q to change
•The process can be thought of an algorithm although the implication is that all cases are evaluated concurrently because
the implementation is in hardware and not software!
•The signal “data” is not in the sensitivity list because it can change at any time and does directly effect the output, q
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Example - State Machine
Bus Arbitor
req0 * /req1
idle0
gnt0=1
gnt1=1
/req0 * req1
/req0
/req
1
req0 * req1
ack1
gnt0=1
gnt1=0
req0 * /req1
req0 * req1
/req0 * req1
ack0
gnt0=0
gnt1=1
idle1
gnt0=1
gnt1=1
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Example - State Construct
VHDL keywords and library options are in bold
Comments follow “--”
library ieee;
use ieee.std_logic_1164.all;
entity state_example is port
(clk, rst, req0, req1: in std_logic;
gnt0, gnt1: out std_logic);
end state_example;
-- 1 Use IEEE standard library
-- 2 Use IEEE standard data type
-- 3 entity description, name is “state_example”
-- 4 input pin description, clock, reset & request pins
-- 5 outputs (not necessarily the state variables)
-- 6 end of entity description
-- 7
architecture jeff of state_example is
-- 8 architecture name is “jeff”
type state_type is (ack0, ack1, idle0, idle1);
-- 9 type declaration (list of state names)
signal state, next_state: state_type;
-- 10 two types of signals, current state & next state
begin
-- 11 keyword
transitions: process (state, req0, req1) begin
-- 12 VHDL process construct called “case-when”
case state is
-- 13
when ack0 =>
-- 14
gnt0 <= ‘0’; gnt1 <= ‘1’;
-- 15 When in state ack0, gnt0 = 0 & gnt = 1
if req0 = ‘1’ and req1 = ‘0’ then next_state <= ack1;
-- 16 active low req1 acknowledged
elsif (req0 and req1) = ‘1’ then next_state <= idle0;
-- 17 no request, go back to idle0
else next_state <= ack0;
-- 18 if no change in inputs, loop here
end if;
-- 19
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Example cont’d - State Construct
VHDL keywords and library options are in bold
Comments follow “--”
when ack1 =>
-- 20
gnt0 <= ‘1’; gnt1 <= ‘0’;
-- 21 When in state ack1, gnt0 = 1 & gnt = 0
if req0 = ‘0’ and req1 = ‘1’ then next_state <= ack0;
-- 22 active low req0 acknowledged
elsif (req0 and req1) = ‘1’ then next_state <= idle1;
-- 23 no request, go back to idle1
else next_state <= ack1;
-- 24 if no change in inputs, loop here
end if;
-- 25
when idle0 =>
-- 26
gnt0 <= ‘1’; gnt1 <= ‘1’;
-- 27 When in state idle1, gnt0 = 1 & gnt = 1
if req1 = ‘0’ then next_state <= ack1;
-- 28 active low req1 acknowledged**
elsif (req0 = ‘0’ and req1 = ‘1’) then next_state <= ack0;
-- 29 active low req0 acknowledged
else next_state <= idle0;
-- 30 if no change in inputs, loop here
end if;
-- 31
when idle1 =>
-- 32
gnt0 <= ‘1’; gnt1 <= ‘1’;
-- 33 When in state idle1, gnt0 = 1 & gnt = 1
if req0 = ‘0’ then next_state <= ack0;
-- 34 active low req0 acknowledged**
elsif (req0 = ‘1’ and req1 = ‘0’) then next_state <= ack1;
-- 35 active low req1 acknowledged
else next_state <= idle1;
-- 36 if no change in inputs, loop here
end if;
-- 37
end case;
-- 38 End Case construct
end process;
-- 39 Process ending statement
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Example cont’d - State Construct
VHDL keywords and library options are in bold
Comments follow “--”
operation: process (rst, clk) begin
-- 40 define 2nd process “operation”
if rst = ‘1’ then state <= idle0;
-- 41 when, rst = 1 then state = idle0 (asynchrounous)
elseif rising_edge (clk) then state <= next_state
-- 42 define basic state >> next_state operation
end if;
-- 43 end of “if” cases
end process;
-- 44 end of process “operation”
end state_example;
-- 45 end of architecture description
•New data type (called state_type) is used in this example (enumeration type) to give names to the states.
•Process contains “sensitivity” list which contains all signals that can possible cause the value of output state to change
•The process “operation” describes the basic flip-flop operation in a state machine with a clock.
•The process “transitions” describes the basic state transition logic depicted in the bubble chart.
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Clocks and Timing Analysis
-Most large scale ASICs and systems built with
these ASICs have several synchronous clock
domains connected by asynchronous
communication channels
- Flexibility due to different rate clocks on
same chip.
- Different polarities also available.
- Timing analysis plays a big role in analysis and
design verification
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Memory Technology
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Memory Terminology
General Memory Operation
CPU-Memory Connection
ROM
ROM Architecture
Types of ROM
Flash Memory
ROM Applications
Semiconductor RAM
RAM Architectures
SRAM
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DRAM
DRAM Structure and Operation
DRAM R/W Cycles
DRAM Refreshing
DRAM Technology
Expanding Word Size and Capacity
Special Memory Functions
Troubleshooting RAM Systems
Testing ROM
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Memory Terminology
• Capacity: Density of Device
- 4096 20-bit words
= 81,920 bits = 4096*20 = 4K*20
- 1 M or 1 meg = 220
- 1 G or 1 giga = 230
• Address: Binary numerical selection input
• Control: Various enable inputs for entire memory device
or for output buffer control
• Read Operation: fetch data from memory
• Write Operation: store data in memory
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• Access Time: Time from first input in to data out
• Volatile Memory: Any type of memory that looses data when
power is compromised
• RAM: Random Access Memory is memory that can be read or
written in normal operation. Access time is the same for any
address in memory
• ROM: Read Only Memory is memory that can be programmed
but is generally not written to in normal operation.
• Static RAM (SRAM): RAM which uses internal flipflops to
store data and no dynamic refresh operation is required to store
the data.
• Dynamic RAM (DRAM): Stored data on internal capacitors
will only remain for a short period, typically ~2-5mSec, before
it must be read and re-written in a “refresh” operation.
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Typical Memory Read/Write Operation
1.
2.
3.
4.
5.
Apply the address that is being accessed for the operation
Assert read or write control as well as enables
If the cycle is a write cycle, assert the input data to be
stored in memory during the write operation
If the cycle is a read cycle, latch the output data coming
from memory during the read operation
Enable (or Disable) the memory so that it will (or will
not) respond to the address and r/w command.
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FIG 12-3 (a) Diagram of a 32  4 memory; (b) virtual arrangement of memory cells into 32 four-bit words.
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Fig 12-12 (a) Logic symbol for 27C64 Erasable PROM; (b) typical EPROM package showing ultraviolet window; (c) 27C64 operating modes.
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Summary
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MROMs are programmed during manufacturing process.
PROMs are programmed one time by the user.
EPROMs can be erased using UV light.
EEPROMs and flash memory are electrically erasable and
can have their contents altered after programming.
• Data are retained in a RAM device only as long as power
is applied.
• SRAM uses storage elements that are basically latch
circuits.
• DRAM uses capacitors to store data by charging or
discharging them.
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Contents
General Memory Organization
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Fig 12-4 (a) writing the data word 0100 into memory location 00011; (b) reading the data word 1101 from memory location 11110.
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12-3 CPU-Memory Connections
• Write Operation
1. CPU supplies the binary address of the location
2. CPU places the data on the data bus line
3. CPU activates the appropriate control signals
4. Memory decodes the binary address
5. Data are transferred to the selected location
• Read Operation
1. CPU supplies the binary address of the location
2. CPU activates the appropriate control signals
3. Memory decodes the binary address
4. Memory places data onto the data bus
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Fig 12-5 Three groups of lines connect the main memory ICs to CPU.
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12-4 ROM
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12-5 ROM Architecture
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12-6 ROM Timing
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12-7 Types of ROMs
Fig 12-9 MOS MROM (Mask-programmed ROM)
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A14
Fig 12-10 Logic symbol for TMS47256 ROM made using NMOS/CMOS technology. (MROM)
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Fig 12-11 Programmable ROMs (PROMs) use fusible links that can be selectively blown open by the user to program a logic 0 into a cell.
PROMs = one-time programmable ROMs
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Fig 12-13
(a) Symbol for the 2864 Electrically EPROM;
(b) operating modes;
(c) timing for the write operation.
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CD ROM
• The disks are manufactured with a highly reflective surface
• Digital data are stored on the disk one bit at a time by
burning or not burning a pit into the reflective coating
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12-8 Flash Memory
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Fig 12-15 (a) Logic symbol for the 28F256A flash memory chip;
(b) control inputs
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Fig 12-16 Functional diagram of the 28F256A flash memory chip. (Courtesy of Intel Corporation.)
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12-9 ROM Applications
• Firmware: OS programs and language interpreters
• Bootstrap Memory: when the computer is powered on, it
will execute the instructions that are in bootstrap program
• Data Tables
• Data Converter
• Function Generator
• Auxiliary Storage
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Fig 12-17 Function generator using a ROM and a DAC
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Fig 12-18 The ML2035 programmable sine-wave generator (Courtesy of MicroLinear)
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Example
• Design a combinational circuit using a ROM. The circuit
accepts a 3-bit number and generates an output binary
number equal to the square of the input number.
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12-10 Semiconductor RAM
• When the term RAM is used with semiconductor
memories, it is usually taken to mean read/write memory
(RWM) as opposed to ROM.
• Major disadvantage: volatile
• Main advantage: can be written into and read from rapidly
with equal ease
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12-11 RAM Architecture
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Fig 12-19 Internal organization of a 64  4 RAM
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Fig 12-20 Logic symbols for (a) the 2147H RAM chip;
(b) the MCM6206C RAM.
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12-12 Static RAM
SRAM can store data as long as power is applied to the chip
Fig 12-22 Typical timing for static RAM: (a) read cycle; (b) write cycle
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Fig 12-23 Symbol and mode table for the CMOS MCM6264C
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Fig 12-24 JEDEC standard memory packaging
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12-13 Dynamic RAM (DRAM)
• Store 1s and 0s as charges on a small MOS capacitor
• Because of the tendency for these charges to leak off after
period of time, DRAMs require periodic recharging of the
memory cells (refreshing)
• Larger capacities and lower power consumption
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12-14 DRAM Structure & Operation
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Fig 12-25 Cell arrangement in a 16K  1 DRAM
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Fig 12-26 Symbolic representation of a dynamic memory cell. During a WRITE operation, semiconductor switches SW1 and SW2 are closed. During a read operation, all switches are
closed except SW1.
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Fig 12-27 (a) Simplified architecture of the TMS44100 4M  1 DRAM; (b) RAS/CAS timing. (Courtesy of Texas Instruments.)
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Fig 12-28 (a) CPU address bus driving ROM or SRAM memory;
(b) CPU addresses driving a multiplexer that is used to multiplex the CPU address lines into the DRAM
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Fig 12-29 Timing required for address multiplexing
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12-15 DRAM R/W Cycles
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Fig 12-30 Signal activity for a read operation on a dynamic RAM. The R/W input (not shown) is assumed to be HIGH.
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Fig 12-31 Signal activity for a write operation on a dynamic RAM.
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12-16 DRAM Refreshing
Fig 12-32 The RAS-only refresh method uses only the RAS signal to load the row address into the DRAM to refresh all cells in that row. The RAS-only refresh can be used to perform a
burst refresh as shown. A refresh counter supplies the sequential row addresses from row 0 to row 1023 (for a 4M  1 DRAM).
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Fig 12-33 TMS44100 refresh modes
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12-17 DRAM Technology
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Memory modules
FPM (Fast Page Mode) DRAM
EDO (Extended Data Output) DRAM
SDRAM (Synchronous DRAM)
DDRSDRAM (Double Data Rate SDRAM)
SLDRAM (Synchronous Link DRAM)
DRDRAM (Direct Rambus DRAM)
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12-18 Expanding Word Size and Capacity
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Fig 12-34 Combining two 16  4 RAMs for a 16  8 module.
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Fig 12-35 Eight 2125A 1 K  1 chips arranged as a 1K  8 memory
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Fig 12-36 Combining two 16  4 chips for a 32  4 memory
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Fig 12-37 Four 2K  8 PROMs arranged to form 8K  8
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Fig 12-38 A system with incomplete address decoding
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Fig 12-39 A memory map of a digital dashboard system
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Fig 12-40 Eight 4M  1 DRAM chips combined
to form a 4M  8 memory module
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12-19 Special Memory Functions
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Power-Down Storage
Cache Memory
FIFO
Circular Buffers
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Fig 12-41 In FIFO, data values are read out of memory (b) in the same order that they were written into memory (a)
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12-20 Troubleshooting RAM Systems
Fig 12-42 4K  8 RAM memory connected to a CPU
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12-21 Testing ROM
• Socket approach
• Reference ROM chip approach
• Checksum
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Fig 12-45 Checksum method for an 8  8 ROM:
(a) ROM with correct data; (b) ROM with error in its data
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