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SOLUTIONS - SEMESTER ONE –REPEAT - 2007 MODULE: Digital Circuits and Systems (EE201) COURSE: B.Eng. in Info and Communications Engineering B.Eng. in Mechatronic Engineering B.Eng. in Electronic Engineering B.Eng. in Digital Media Engineering YEARS: 2 (two) and 3 (three) EXAMINERS: Mr. David Bermingham Dr. R. Millar Dr. F. Derek TIME ALLOWED: 2 hours INSTRUCTIONS: Answer FOUR questions. All questions carry equal marks ___________________________________________________________________________________________ EE201 - Digital Circuits and Systems - Semester One - 2006/2007 page 1/10 QUESTION 1 A) Design a 1-line to 4-line demultiplexer using logic gates and briefly describe its operation. How can this demultiplexer be used as a 2-line to 4-line decoder? A demultiplexer transfers its input to one of the outputs depending on the binary code provided at the select inputs. O0 O1 I DMUX ON-1 S0 S1 SM-1 1:4 line Demultiplexers: 1 data line (I), 2 select line (S0 & S1) and 4 output lines(O3-O0) S 0 0 1 1 S O2 O3 0 0 1 0 0 0 1 I O1 0 0 0 I I 0 0 0 O0 I 0 0 0 Using logic gates I O0 S0 S1 O1 O2 O3 ___________________________________________________________________________________________ EE201 - Digital Circuits and Systems - Semester One - 2006/2007 page 2/10 By connecting the data line to 1, the 1:4 demultiplexer can be used as 2:4 line decoder. For every input sequence on S0, S1 a single output bit will set. (10 Marks) B) Implement the following logic function using only 4-line to 1-line multiplexers: F A.B.C.D A.B.C.D A.B.C.D A.B.C.D Question 2 A) Compare the serial and the parallel interfaces between computers and peripherals by indicating their advantages and disadvantages. Serial Interface – advantages Peripheral ca be located far from the computer Lower cost of wiring Less susceptible to noise More flexible in terms of transmission technologies Serial Interface – disadvantages Low transmission rate Requires parallel-serial and serial-parallel conversion Parallel Interface – advantages High transmission rate Does not require conversion Parallel Interface – disadvantages Peripheral has to be located close to the computer High cost of wiring More susceptible to noise Less flexible in terms of transmission technologies (8 Marks) ___________________________________________________________________________________________ EE201 - Digital Circuits and Systems - Semester One - 2006/2007 page 3/10 b) Draw a block diagram of an ACIA type serial interface controller. Clock Generator Transm. Status Parity Generator Data/Shift Register Register Control Register IR Q Reception RCLK Clock Generator Data/Shift Register Parity Generator TxCL K Data Bus Tx D CTS RTS RxD (7 Marks) C) Describe the function of each block of the diagram drawn in Q2 b) Transmission Data/Shift Register – accepts parallel data from Data Bus, inserts necessary parity bits and shifts data, one-bit at a time, to TxD serial line Reception Data/Shift Register – receives serial data from RxD line, shifts the data, removing also the parity bits and delivers parallel data to the Data Bus Control Register – determines the format of the serial data (transmission frequency, number of data bits, parity), the clock to be used (external or built-in) and enables interrupts during the transmission and reception of data respectively Status Register – gives information about the status of the conversion process transmit/receive (e.g. errors, parity, interrupts, handshaking signals, etc.) Clock Generator – generates clock signal for transmission and reception of data respectively Parity Generator – generate parity bits for transmission and reception of data respectively (10 Marks) ___________________________________________________________________________________________ EE201 - Digital Circuits and Systems - Semester One - 2006/2007 page 4/10 Question 3 A) Compare the three possible output configurations possible when using TTL circuits. Compare and contrast the methods when applied to data bussing. Open collector output: +5V 4k A Q1 1.6k F Q2 Q2B Q3 1k 0V The output signal F changes between floating high (1) and logic 0 when Q3 is ON. Open collector output can only sink current with an additional pull-up resistor at the output to allow current to be sourced for the next logic stage. The resistor value will determine how fast an open-collector TTL circuit can be switched. TTL Totem-Pole: +5V 4k A B 1k Q3B Q1 Q3 Q2 Q2B D1 Q4B F Q4 1k 0V In totem pole configuration and additional pair of BJTs are added to the TTL logic to ensure both proper logic levels and faster operation. The figure above shows a TTL NAND gate using totem-pole configuration B) Describe, using a diagram, the structure and operation of a CMOS NAND gate. Why does its power dissipation depend on the frequency of operation? C) A 74LS00 NAND gate is used to drive similar NAND gates. Given the following parameters for a 74LS00 NAND, IIH=20µA, IOH=-0.4mA, IIL=0.4mA, IIH=8mA. Determine the fanout of a single 74LS00 NAND gate. ___________________________________________________________________________________________ EE201 - Digital Circuits and Systems - Semester One - 2006/2007 page 5/10 Determine Fanout when logic high: Fanout when high => IOH / IIH = 400/20 => 20 Gates Determine Fanout when logic low: Fanout when low => IIH / IIL = 8/0.4 => 20 Gates To determine the Fanout you select the lower of the two figures. For 74LS00 NAND gate the Fanout is the same for both states. => Each NAND gate can drive 20 gates. (5 Marks) Question 4 A) An 8-bit ripple carry adder is constructed using NAND logic. If the propagation delay for a NAND gate is 250 pS what is the maximum addition time for the adder? Ripple carry adder has 2 gates in the critical path, an AND gate and OR gate. Both gates are comprised of a NAND array with 2 NAND delays. The overall delay for a single NAND RCA cell is 4 NAND gates. For an 8-bit RCA, there will be 8*4 NAND gates in the critical path. => 8 * 4 * 250ps = 8nS adder delay (5 Marks) B) Outline an algorithm for addition of two floating-point numbers. Lets assume that A*2a and B*2b will be added In order for the addition to be performed, the exponents of the two numbers have to be equalised and their mantissas shifted accordingly: Test the values of a and b using either a comparator or subtractor If a>b, B is right shifted a-b places, obtaining B’ If a<b, A is right shifted b-a places, obtaining A’ If a=b, no shift is required To obtain the mantissa of the result If a>b => MANTISSARES = A + B’ If a<b => MANTISSARES = A’ + B If a=b => MANTISSARES = A + B ___________________________________________________________________________________________ EE201 - Digital Circuits and Systems - Semester One - 2006/2007 page 6/10 To obtain the exponent of the result: If a>b => EXPRES= a If a<b => EXPRES= b If a=b => EXPRES= a or b Normalise result by shifting right until bits either side of decimal point are different. C) Multiply using the Booth algorithm +8 and –12. Design the hardware required for this multiplication. Indicate the major signals required. Multiplicand Load Md A3 A2 A1 A0 !Add/Sub B3 B2 B1 B0 !Nop/Op Multiplier Reset R7 R6 R5 R4 R3 R2 R1 R0 Load Mr R-1 Reset R Shift the 8-bit register R is cleared using the signal Reset the multiplicand is loaded using Load Md the multiplier is loaded using Load Mr Depending on the values of R0 and R-1 addition, subtraction or no operation is performed at every Clock: when the R0R-1 are 10 SUB is performed when the R0R-1 are 01 ADD is performed when the R0R-1 are 00 or 11 no operation is performed register R is right shifted at every Clock using signal R Shift ___________________________________________________________________________________________ EE201 - Digital Circuits and Systems - Semester One - 2006/2007 page 7/10 Multiplicand (Y) 0 1 0 0 0 Multiplier (X) 1 0 1 0 0 Result (R) Step (+810) 0 (-1210) Action 0 0 0 0 0 0 0 0 0 0 Initialisation 0 0 0 0 0 0 0 0 0 0 00 => NOP 0 0 0 0 0 0 0 0 0 0 A. Right Shift 0 0 0 0 0 0 0 0 0 0 00 => NOP 0 0 0 0 0 0 0 0 0 0 A. Right Shift 0 1 0 0 0 10 => SUB (R, Y) 1 0 1 1 1 A. Right Shift 1 1 0 0 0 01 => ADD(R,Y) A. Right Shift 11 => NOP A. Right Shift Verif. Result = -9610 Question 5 A) Briefly describe the dynamic RAM cell and its operation. How does it compare with a single static RAM cell in terms of area, speed, control circuitry and power ___________________________________________________________________________________________ EE201 - Digital Circuits and Systems - Semester One - 2006/2007 page 8/10 DRAM Structure To access such a cell one needs to have access to a word line and a bit line. To write the memory cell, the bit line is charged to a logic 1 or 0 voltage while the word line is asserted. This enables the access transistor, making it possible to charge up the storage capacitor with the desired logic voltage. The read operation takes place by asserting the word line. The access transistor is turned on, sharing the voltage on the capacitor with the bit line. Sensitive amplifier circuits detect small changes on the bit line to determine whether a 1 or 0 was stored in the selected memory element. The destructiveness of the read operation makes DRAMs complex. To read the contents of the storage capacitor, we must discharge it across the bit line. Thus, external circuitry in the DRAM must buffer the values that have been read out and then write them right back. The second problem with DRAMs, and the most significant one is that their contents decay over time. Every once in a while (measured in milliseconds), the charge on the storage capacitors leaks off. To counteract this, the DRAM must be refreshed. Periodically, the memory elements must be read and written back to their storage locations. To make this operation reasonably efficient, the DRAM's memory array is a two-dimensional matrix organized as follows: The figure shows the block diagram of a 4096 by 1-bit DRAM. Rather than refresh individual bits, a refresh cycle reads out and writes back an entire row. This happens about once every few microseconds. The row is typically a multiple of the DRAM's word size. In this case, it is 64 bits wide. The refresh cycles are generated by an external memory-controller. ___________________________________________________________________________________________ EE201 - Digital Circuits and Systems - Semester One - 2006/2007 page 9/10 Comparison to SRAM Advantages of DRAM o Denser : Smaller Area required o Cheaper: Cost per bit is less o Power: More power efficient than high speed SRAM However SRAM can be designed to consume little power B) Disadvantages of DRAM o Control Logic : Requires memory controller to ensure data is refreshed automatically unlike SRAM o Interface: Much more complicated to interface than simple address/data bus structure of SRAM o Speed: Difficult to scale DRAM to ultra high performance without long latencies, errors, etc. High speed memory like processor cache uses SRAM cells o Power: Power consumption analysis must include additional control circuitry in calculations. PD(SRAM) = Power dissipated by SRAM cells at freq f PD(SRAM) = Power dissipated by DRAM cells at freq f + Power dissipated by DRAM controller (15 Marks) Compare the architecture of PROM and PLA and state the advantages, disadvantages and suitable applications of each? ___________________________________________________________________________________________ EE201 - Digital Circuits and Systems - Semester One - 2006/2007 page 10/10