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Circuit Design and
Theory of Operation
THE NOSTALGIC FOUR
ECE 477 Group 5
Jorge Marcet
ECE 477
Digital Systems Senior Design Project
Fall 2004
Introduction
The idea of developing a new and innovative game console that would integrate the
continuously growing usage of USB memory sticks as the means for data portability as well as
the interface of different silicon components in order to deliver maximum performance led to the
idea of creating the N4 video game console [01]. This game console is intended to reach the
beginner gaming market by offering the ability to the user of programming games, downloading
them through the USB interface and playing them through the console. The purpose of this
document is to explain in detail how each main component is interfaced and what is the task it
performs within the game console.
The Nostalgic 4 (N4) features three main interfaces to the microprocessor:
1. Handheld Nintendo Controller(s)
2. Universal Serial Bus (USB) Memory-stick Reader
3. RGB-to-NTSC Video Encoder
The handheld controllers are the interface between the player and the machine. These will
function as the primary means for the user to interact with the game being played. The USB
memory-stick reader represents the interface which enables the user to load a game. The USB
Host/Slave controller will aid in the conduct of data between USB memory-stick and the
system’s main RAM. The RGB-to-NTSC video encoder is the means for the console to display
the game on a normal NTSC TV screen.
The main components of the console are as follows:
1. MC9S12A256 Motorola Microprocessor
2. XC95108 Xilinx CPLD
3. AD724 RGB to NTSC Analog Devices Encoder/Decoder
4. CY7C109 Cypress RAM
5. USB Memory-Stick
6. SL811HS Cypress USB Host/Slave Controller
7. 74VHC573 Fairfield High-Speed Latches
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8. MAX831 and MAX832 Maxim DC-DC Step-Down Converters and Regulators
The Theory of Operation and respective schematics for the devices are listed below.
Theory of Operation
When the power switch of the N4 console is closed, the user will be able to interact with the
console through the Nintendo controllers. The controllers are directly connected to the Motorola
microprocessor through PULSE, LATCH and DATA lines. On booting up, the microprocessor
will start executing the game that is already stored in memory. By using the “load game” button,
the game console prepares to extract the information upon the interface of a USB memory stick.
Once it has read the game data on the USB memory-stick through the USB Host, it will move the
game data into the Cypress RAM for storage prior to execution. On execution, the game transfers
the video display to the Xilinx CPLD. This frees up the microprocessor from handling the NTSC
video output. The microprocessor will then continually update the changes in video data directly
to the CPLD, hence leaving extra cycles for the execution of game code. The details of each
main component are explained in the following sections.
MC9S12A256 Motorola Microprocessor
The MC9S12DP256 microcontroller unit (MCU) (Fig. 1) is a 16-bit device composed of
standard on-chip peripherals which main functional blocks are: a 16-bit central processing unit
(HCS12 CPU), 256K bytes of Flash EEPROM, 12K bytes of RAM, 4K bytes of EEPROM, two
asynchronous serial communications interfaces (SCI), three serial peripheral interfaces (SPI), an
8-channel IC/OC enhanced capture timer, an 8-channel pulse-width modulator (PWM), 29
discrete digital I/O channels (Port A, Port B, Port K and Port E) and 20 discrete digital I/O lines
with interrupt and wakeup capability. The large Flash EEPROM capability as well as the
significant number of I/O ports available for interfacing were the main characteristics that led to
the selection of this particular MCU. Since all the code required to drive the USB Host controller
will be stored in the Flash EEPROM, this MCU’s Flash capacity was a perfect fit for the project.
From the schematics, all the different components that will be interfaced to the MCU can also be
seen. A big range of I/O ports must be available for driving all these components. The MC9S12
provided this capability as well.
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To support the fast gaming interface, timing is the essence. Hence, the MC9S12A256
microprocessor will be run at 16 MHz to allow for fast graphics update, leaving sufficient
processing power for game processing. In the event that 16 MHz is insufficient speed for
efficient game management, the microprocessor will be run at 25 MHz. The MC9S12 requires a
voltage of +5VDC to function; this voltage is supplied by the power supply which will be
discussed later in this document. The microprocessor also has an internal step-down voltage of
+3.3VDC [02].
The MCU has several decoupling capacitors in accordance with the data sheet. In addition,
the microprocessor will be interfaced with the 128 KB RAM (2 Cypress 64 KB RAM Chips)
module were the game will be stored. Also, the microprocessor will be interfaced with a USB
Host Controller for the ability to read external game data for execution. This innovative idea
would enable the console to be more competitive in an actual gaming market. Graphic data will
be sent to a Xilinx CPLD for handling prior to actual video display. For programming purposes,
the microprocessor will be directly attached to an RS232 driver—MAX233A—which will
function as the channel between programming software and microprocessor chip. The
MAX233A was chosen over the MAX232 because it features charge pump capacitors which are
already integrated in the package that would help save Printed Circuit Board (PCB) space [03].
More concrete details are displayed on the attached schematic.
From Fig. 1 it can be seen that 8 I/O port pins (PM0..PM7) are devoted to the transfer of data
from the USB Host controller to the microprocessor. Then, 16 I/O port pins are designated to
interface the microcontroller with the 2 main system RAMs (PB0..PB7 and PA0..PA7). The
PULSE, LATCH and DATA lines from both controllers are also interfaced with 3 I/O port pins
each (For controller one PT0 for data, PP1 for latch and PP2 for pulse, for controller two PS2 for
data, PH5 latch and PH6 pulse). PP1 and PP2 are Pulse Width Modulation (PWM) ports that will
be turned into I/O port pins when programming the microprocessor. VSSPL (VDDPL pin),
VDDPLL (VDDPLL pin) and XFC (XFC pin) are used to drive a Phase Lock Loop Filter [01]
(page 60) that is required due to microprocessors data sheet. PT6 and PT7 are devoted to drive
the power safety device for the USB controller which will be explained later in this document.
PK4 and PK5 are the “Output Enable” pins for each system main RAM chip. The Transistor-ToTransistor Logic portion (both Receive - RX and Transmit - TX) of the RS232 chip [03] is
interfaced to pins PS0 and PS1.The last main chip interfaced to the microprocessor is the Xilinx
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CPLD. DISP, XWRD, XWR and XWAIT which are the main signal in the chip are interfaced to
PH0..PH3. All capacitors values and external circuitry are taken from the data sheet. Finally,
headers have been added to the main ports of the microprocessor in order to facilitate debugging.
Fig. 1 MC9S12A256 Freescale Microprocessor
XC95108 Xilinx CPLD
The XC95108 [04] is a high-performance CPLD providing advanced in-system programming
and test capabilities for general purpose logic integration. It is comprised of eight 36V18
Function Blocks, providing 2,400 usable gates with propagation delays of 7.5 ns. This CPLD is
the graphics updating arm of the N4 console. Some of the features that were considered when
selecting this chip were its programmable power reduction mode in each macrocell and its
capability to handle 3.3V or 5V I/Os.
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The CPLD has 84 pins, which are programmed to control the video output from the console.
Each video pixel will be kept in a fast SRAM (Cypress 64 KB RAM) for access by the CPLD.
The CPLD will be clocked at 4 times the NTSC rate (3.579 MHz), i.e. 14.31818 MHz [04] (The
oscillator circuitry for the CPLD can be seen in Page 2 of the schematic attached). This speed
will allow for color bursting, which indicates the color associated with each pixel. The voltage
required by the CPLD to operate is +5VDC at a typical supply current of 100mA. This voltage
will be provided by the power supply which will be discussed later in this document. The
original video system design was obtained from elm-chan.org [05]. The TDI, TMS, TCK and
TDO pins are also connected to a JTAG which will be used for debugging the CPLD software in
case problems are encountered once the chip is already soldered to the PCB.
Fig. 2 Xilinx CPLD
AD724 RGB-To-NTSC Encoder/Decoder
The AD724 [06] is a low cost RGB to NTSC/PAL Encoder that converts red, green and blue
color component signals into their corresponding luminance (base-band amplitude) and
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chrominance (sub-carrier amplitude and phase) signals in accordance with either NTSC or PAL
standards. These two outputs are also combined to provide composite video output. This chip
will be used to convert the Red-Green-Blue (RGB) output from the CPLD to NTSC format for
TV output. Although the AD724 has the ability to output in S-Video, this feature will not be
utilized as NTSC is being used. The operating voltage required by the chip in order to operate is
+5VDC ad a supply current of 42mA. This voltage will be provided by the power supply which
will be discussed later in this document. The AD724 was designed to have three allowable
modes of applying a clock via the FIN pin. These are FSC (frequency of sub-carrier) mode with
CMOS clock applied, FSC mode using on-chip crystal oscillator, and 4FSC mode with CMOS
clock applied. The FSC frequency is 3.579545 MHz for NTSC, this frequency will be generated
by pin 47 (SCCLK) of the Xilinx CPLD. All resistor and capacitor values for the external
circuitry of the chip are taken from the data sheet [06].
Fig. 3 RGB to NTSC Converter
CY7C109 Cypress RAM
The 64 KB RAM Chips [07] are used mainly for game storage. Two of these RAM chips
would allow for 128 KB of RAM game storage prior to execution. The CY7C109 is a highperformance CMOS static RAM. Writing to the device is done by taking Chip Select One (CS1)
and Write Enable (WE) inputs LOW and Chip Select Two (CS2) input HIGH (this can be seen in
Page 1 of the attached schematics). Data on the eight I/O pins (I/O0..I/O7) is then written into the
location specified on the address pins (A0..A16). Reading from the device is accomplished by
taking Chip Select One (CS1) and Output Enable (OE) LOW while forcing Write Enable (WE)
and Chip Select Two (CS2) HIGH. Under these conditions, the contents of the memory location
specified by the address pins will appear on the I/O pins.
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The RAM chips were specifically chosen for their high-speed capability—tAA = 12 ns [07].
The voltage required by each RAM chip to operate is –0.5V to +7.0V due to spec at a typical
supply current of 90mA. A +5VDC voltage will be provided by the power supply which will be
discussed later in this document.
Fig. 4 CY7C109 Cypress RAM
SL811HS Cypress USB Host/Slave Controller
The SL811HS Cypress USB Host/Slave Controller [08] would be responsible for reading the
external game data stored on the USB memory-stick. The USB Controller will be used in Host
mode. This ensures that a DMA controller is not needed. This mode is attained by setting the
M/S pin HIGH. The chip has 7 main parts: an active LOW chip select pin (!CS), an active LOW
read (!RD), an active LOW write (!WR), and active HIGH interrupt signal, an address bus pin
(A0) and an 8-bit data bus (D0..D7). The chip select pin enables the USB controller to READ or
WRITE and it has to be asserted by the microcontroller at least 65ns for any transaction to be
valid. The READ pin signals a register or memory READ. The WRITE pin signals the WRITE
of an address, register or memory WRITE. For both READ and WRITE to take place, the
address of the location in memory has to be written to the USB first. This is done with A0 pin.
When the A0 (ADDRESS) pin is LOW during a WRITE, the WRITE goes to an address pointer
register. When the A0 pin is HIGH during a WRITE, the WRITE goes to a register or memory
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location pointed to by the address pointer register. For instance, if we want to write to the
register at address 00h we would first perform a write with D0..D7 set to 00h and A0 set LOW.
Then we would perform another write with D0..D7 set to the register value and A0 set HIGH.
The interrupt (INTRQ) and data bus (D0..D7) pins are self explanatory. From Fig. 5 it can be
seen that the USB controller also has a power protection and that the chip is clocked at 48 MHz.
The external circuitry for the clock and for the chip itself was taken from the data sheet [08]. The
chip also has a built in 256 byte RAM buffer in order to facilitate data transmission. The USB
memory-stick will be the commonly used Type A. The USB Host will ensure that the memory
stick be read fast enough for minimization of loading times. The voltage required by USB
controller to operate is +3.0VDC minimum at a typical supply current of 25mA. A +3VDC
voltage will be provided by the power supply which will be discussed later in this document.
Fig. 5 USB Host Controller
74VHC573 High-Speed Latches
This 8-bit D-type latch [09] is controlled by an active LOW latch enable input (LE) and an
active LOW Output Enable input (OE). When the OE input is HIGH, the eight outputs are in a
high impedance state.
The multiplexed address from the CPLD is not stable for long. The specifications on the data
sheet of the CPLD state that the minimum time between ECLK to the end of address is tMAH = 2
ns. This can be increased to approximately 5 ns by using ECS instead of ECLK. To accomplish
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this, a high-speed transparent latch is required. For this reason the 74VHC573 was chosen,
because it has a typical speed of tPD = 5 ns [09]. The voltage required by each latch to operate is
–0.5V to +7.0V due to spec at a typical supply current of 40µA. A +5VDC voltage will be
provided by the power supply which will be discussed later in this document.
Fig. 6 High Speed Latches
Power Supply Design (MAX831, MAX832 DC-DC Step-Down Converters and Regulators)
The majority of the components that comprise the video game console are powered at +5VDC.
The only component that is powered at +3.3VDC is the USB Host Controller. The power supply
will be constructed with a +12VDC at 1500mA AC to DC power adapter that will be the
responsible to convert the AC voltage from the power outlet to DC. Then this +12VDC input
will be fed into two different step down DC-DC regulator chips. The real voltage from the ACto-DC adapter as suspected was greater than advertised, it was measured to be ~+15VDC. This
problem was overcame by choosing the DC-DC regulators to have a variable input voltage from
8-40VDC. The MAX831 chip [10] converts a DC input from 8-40VDC to a steady +5VDC
output, the MAX832 [10] performs the same task but gives an output of +3.3VDC.
The typical operating circuits for these chips were available in the MAXIM data sheet [10].
From specs it was also noted that clip-style heat-sinks and wide copper traces to connect the
leads to reduce thermal resistance and dissipate heat have to be used. The chips have a maximum
thermal temperature of +125ºC so it was a perfect fit for our design as our input DC voltage of
~+15VDC at continuous load current produces a temperature of 50-70ºC from spec.
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Fig. 7 Power Supply Design
Miscellaneous
The connections of the Nintendo controllers to the microprocessor were in accordance to the
amateur data found on the internet [11] (Please refer to Fig. 8). In order to add a safety feature in
case of Electrostatic Discharge from the controller into the microcontroller, optical isolators were
added to each line (PULSE, LATCH and DATA). The basic optical isolator circuitry was taken
from the EE362 Notes [12]. The resistor values were taken from typical values used in industry.
Fig. 8 NES Controllers
Conclusion
The attached schematics are arranged for simple referral. The main components of the game
console (Xilinx CPLD and Microprocessor) are positioned in such a way that each of the
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components interfaced to them can be found easily in the same page as their main chip. Each
component is labeled with its name which also helps for quick referral. The use of USB
interfaces in video game consoles is a challenge that The Nostalgic Four have decided to tackle
and hopefully succeed at it.
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List of References
[01] Reference Design, Sparky, S04-Grp08
[02] MC9S12A256B, Motorola, 9S12DP256BDGV2.pdf
[03] MAX233A, Maxim, MAX220 thru_MAX249.pdf
[04] XC96108, Xilinx, pdfds066.pdf
[05] Elm-Chan, elm-chan.org/works/crtc/report.html
[06] AD724, Analog Devices, 40671345AD724_b.pdf
[07] CY7C109B, Cypress, CY7C109B.pdf
[08] SL811HS, Cypress SL811HS.pdf
[09] 74VHC573, Fairchild, 74VHC573.pdf
[10] MAX831 and MAX832, Maxim, MAX830-MAX833.pdf
[11] NES/SNES Controller Information, www.gamesx.com/controldata/nessnes.htm
[12] EE362 Notes, http://shay.ecn.purdue.edu/~dsml/ece362/Notes/PDF/3-Mod4.pdf
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