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SPEED OPTIMIZED ARRAY ARCHITECTURE FOR FLASH EEPROMS AMIN, AAM IEE-INST ELEC ENG, IEE PROCEEDINGS-G CIRCUITS DEVICES AND SYSTEMS; pp: 177-181; Vol: 140 King Fahd University of Petroleum & Minerals http://www.kfupm.edu.sa Summary The paper describes a new architecture for a split-gate flash EEPROM memory array. The new array architecture provides increased speed and less susceptibility to soft writes during read operations. A unique circuit design and operation method obviates the need for applying high erase voltage in the path between the memory array and the sense amplifier. This allows all the transistors in this speed path to be fabricated as low voltage minimum channel length devices, thereby increasing their speed of operation and consequently the speed of the memory device as a whole. The new architecture, however, requires the addition of two extra rows of nonmemory cell transistors in addition to following a strict programming sequence to guard against spurious programming of unselected cells. References: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. © ALI SB, 1988, IEEE JSSC, V23, P79 AMIN A, 1991, 4999812, US, APPL AMIN AAM, 1992, IEE PROC-G, V139, P370 CERNEA RA, 1989, FEB ISSCC, P138 CONTI F, 1972, SOLID STATE ELECTRON, V15, P93 GILL M, 1988, INT EL DEV M, P428 KUME H, 1987, IEDM, P50 KYNETT VN, 1989, IEEE J SOLID-ST CIRC, V24, P1259 MASUOKA F, 1987, IEEE J SOLID-ST CIRC, V22, P548 MCCONNELL M, 1991, IEEE J SOLID-ST CIRC, V26, P484 MUKHERJEE S, 1985, IEDM, P616 PRALL K, IEEE T EDUC, V34, P2463 SAMACHISA G, 1987, ISSCC DIG TECH PAPER, P76 VERMA G, 1988 P IEEE REL PHYS, P158 Copyright: King Fahd University of Petroleum & Minerals; http://www.kfupm.edu.sa For pre-prints please write to: [email protected] © Copyright: King Fahd University of Petroleum & Minerals; http://www.kfupm.edu.sa