Download 3 Data Conversion I

3. Data Conversion I: Quantisation
3.1 Quantisation
Data Conversion:
The purpose of Data Conversion is to convert data acquired from a
measurement or recording from analogue form into digital form in
order to exploit the benefits, primarily the noise immunity, of binary
coding. Coded values can then be either: stored for future retrieval,
subjected to further processing or transmitted to another location for
use there.
Resolution:
It is evident that even for theoretically perfect signals values cannot
be encoded with infinite resolution.
For example, for the signal below in Fig. 3.1, if the value at t = 250 ms
is measured with unlimited resolution V = 54.3467234…………..mV, it
would take an infinite number of binary digits or bits to encode only a
single value of the signal. This is clearly not sustainable as we could
never convert even a small part of the continuous analogue signal into
digital form.
Relative
Amplitude
Time
Fig. 3.1 Sampled Signal
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Effects of Noise:
When noise is superimposed on a signal of interest it introduces a
degree of uncertainty into the value of the signal at any point in time.
This means that the accuracy and therefore the resolution with which
we can measure the signal are limited. In the case of the noise
contaminated signal below:
Value at t = 250 ms could be
V250 = 54.3467234 V
or it may be
V250 = 54.3467458 V
or it may be
V250 = 54.3467186 V
Relative
Amplitude
uncertainty
introduced
by noise
Time
Fig. 3.2 Noise Contaminated Sampled Signal
The value shown can only be resolved as V = 54.3467 V. The value
below this is 54.3466 V and the value above it is 54.3468 V. This
means that the resolution of measurement for this signal is limited to
0.1 mV. There is no point in specifying values to a higher degree of
resolution as they will simply not be accurate. This means that for any
signal there is a band of uncertainty applying to each value measured.
In practice one cannot have a dependable resolution that is finer than
the level of uncertainty. However, there may often be scenarios where
the level of accuracy attainable is not required and in this case the
resolution may be restricted and kept much lower than that which it is
possible to attain.
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Quantisation:
The process of quantisation is essentially one of imposing a finite
degree of resolution on the range of a signal. The range is divided into
a number of defined levels equally spaced throughout the range
covered by the signal. The levels are shown in the diagram of Fig. 3.3
normalised as a fraction of a reference voltage, VREF. A signal to be
encoded, V, can then only have a value equal to one of these quantum
values. Actual signal values in between quanta are rounded to the
nearest quantum value as shown. Note that 0V is a level in this system
so that the number of available levels stops one short of the reference
voltage. This means that for the example shown the maximum or fullscale signal voltage, VFS, that can be accommodated is one level less
than the reference voltage so that VFS = (7/8)VREF. This leads to
efficiency in the subsequent binary encoding process as will be seen
later.
V/VREF
8/8
7/8
6/8
5/8
4/8
3/8
2/8
1/8
0/8
t
Fig. 3.3 Quantisation Levels
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This means that we are essentially limiting the resolution of the signal
to a finite degree. This is, in fact, the same as making a crude
approximation of the signal with lower resolution than the original
signal. This approximation is represented by the staircase-like function
shown in Fig. 3.4.
Each of the levels can then be assigned a unique binary code to
represent it in digital ‘bit’ form. A simple binary counting progression
has been used here to encode the 8 levels involved (Note: zero is a
level). This requires 3 binary digits or bits to represent all 8 levels. For
example a voltage at 5/8 of the maximum voltage would be encoded
as Binary 5 or 101. In this way values of the signal can be converted to
binary data which can be stored and then recovered at a later stage.
The same quantised staircase-like approximation of the signal shown
in Fig. 3.4 can then be reconstructed from the stored digital data when
recovered.
V/VREF
8/8
Binary
Code
7/8
111
6/8
110
5/8
101
4/8
100
3/8
011
2/8
010
1/8
001
0/8
t
Fig. 3.4 The Quantisation Process
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000
3.2 Examples of Quantised Signals
An example of a sinewave quantized to 8 levels is shown in Fig.
3.5. It can be seen to be a staircase-like approximation of the
sinewave itself. With only 8 levels the approximation is crude but
nonetheless it can be seen to follow the variation in the signal
amplitude of the sinewave. Fig. 3.6 shows a sinewave quantised to 16
levels where it is evident that the staircase approximation is much
closer with twice the number of steps. Therefore it is evident that the
process of quantisation introduces and error into the resulting
quantised signal when compared with the original input signal and
that this error depends directly on the number of quantisation levels
used.
Fig. 3.7 shows a speech signal for a single word lasting less than
1s in time quantised to 16 levels. It can be seen that the distinct
nature of the signal profile or envelope is preserved in quantisation
but the quantised signal is more ‘choppy’ or ‘steppy’ in form.
Fig. 3.8 shows a quantised ECG signal obtained from the surface
of the human body. This signal is by nature noisy as can be seen. The
interesting feature which is evident here is that at low and slowly
changing levels of the signal the quantisation appears to have little
detrimental effect as the signal quality remains limited by the noise
present. At higher and more rapidly changing signal levels the
staircase-like effect of the finite number of quantisation levels can be
seen. This is only visible for fast changing elements of the signal and
leads to the conclusion that time is also factor in the digitisation
process. This will be dealt with at a later stage. For the present,
however, it is evident that there is no point in having a number of
quantisation levels in the process which provides a higher degree of
resolution than the noise which is present allows.
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Fig. 3.5 A Sinewave Quantised to 8 Levels
Fig. 3.6 A Sinewave Quantised to 16 Levels
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Fig. 3.7
A Quantised Speech Signal Having 16 Levels
Fig. 3.8
A Quantised Electrocardiogram Signal
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3.3 Analogue-to-Digital Conversion
The process of converting a continuous analogue signal, with
potentially infinite resolution into coded digital form is referred to as
Analogue-to-Digital Conversion. This involves the two steps of
quantising the signal to a finite resolution and then encoding it into
binary coded form. Normally, however, these two steps are
simultaneous and very often cannot be distinguished as separate parts
of the conversion process.
The conversion process can be thought of as an input-to-output
operation which has a continuous analogue signal as input and a
binary digital code as output as shown in Fig. 3.9.
Input
Analogue
Signal
Fig. 3.9
Analogue
to Digital
Converter
b2
b1
b0
Output
Binary
Code
Block Diagram Illustrating Analogue-to-Digital Conversion
An input-to-output Transfer Characteristic for the system can be
drawn up as shown in Fig. 3.10, which provides a plot of output binary
code verses input signal voltage. The transfer characteristic is
compared with a line representing infinite resolution, which essentially
means an infinitesimally fine quantisation. It can be seen that as the
input voltage is increased from zero to full-scale, VFS, the output code
changes in binary steps. The code can be seen to change from one
value to the next at the halfway point between quantisation levels. For
example, any input voltage up to half of the first level of 1/8 VREF is
coded as zero, 000. Any input voltage, between this point and the
halfway point between the first and second quantisation levels, is
quantised to the first level of 1/8 VREF and encoded as binary level 1 or
001. This pattern continues through the rest of the range to the
highest level of VFS = 7/8 VREF. This gives the staircase like
characteristic as shown. The higher the number of quantisation levels
used, the finer the staircase characteristic and the higher the
resolution. For the 8 levels shown, 0 to 7/8 VREF inclusive, three binary
digits are needed to encode the 8 quantised values of the signal. The
example shown is therefore referred to as being a 3-bit analogue-todigital converter.
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Output
Binary
Code
b2b1b0
111
110
101
100
011
010
001
000
0
1/8
2/8
3/8 4/8
5/8
6/8 7/8
VFS
Vin / VREF
Input
Voltage
Fig. 3.10 Transfer Characteristic of 3-Bit Analogue-to-Digital Converter
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3.4 Digital-to-Analogue Conversion
The process of converting a digital binary input code into an output
analogue voltage is known as Digital-to-Analogue Conversion. Clearly
this is the converse process of Analogue-to-Digital Conversion. It
involves reproducing a quantised analogue voltage level from an input
binary code.
The conversion process can be thought of as an input-to-output
operation which has a binary digital code as input and a continuous
but quantised analogue signal as output as illustrated in Fig. 3.11.
Input
Binary
Code
Fig. 3.11
b2
b1
b0
Digital to
Analogue
Converter
Output
Analogue
Voltage
Code
Block Diagram Illustrating Digital-to-Analogue Conversion
Ideally the output voltage should have a one–to-one relationship with
the input binary code. That is, there should be one precise value of
output voltage for each binary code and this should correspond exactly
to the quantisation level as shown in Fig. 3.12. However, in practice
there is an error in generating the output voltage and this means that
it can be a little above or below the intended quantisation level as
shown in Fig. 3.13. Normally the error is kept within ± ½ of a
quantisation level in order to avoid overlap of voltages associated with
different binary codes.
However, the input-output Transfer Characteristic for the digital-toanalogue conversion process is by convention plotted as a parallel of
that for the digital-to-analogue process and is shown in Fig. 3.14. The
difference is that binary code and voltage scales are interchanged as
input and output. It can be seen that the error of ± ½ a level in
generating the output voltage gives the characteristic the same
staircase-like look. The horizontal lines on the diagram do not actually
represent anything.
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V0 \ VREF
(VFS) 7/8
6/8
5/8
4/8
3/8
2/8
1/8
0
000 001 010 011 100 101 110 111 b2b1b0
Input Binary Code
Fig. 3.12 One-to-One Operation of 3-Bit Digital-to-Analogue Converter
I
n
p
u
t
V0 \ VREF
(VFS) 7/8
V
o
l
t
a
g
e
6/8
5/8
4/8
3/8
2/8
1/8
0
000 001 010 011 100 101 110 111 b2b1b0
Input Binary Code
Fig. 3.12
Quantised Operation of 3-Bit Digital-to-Analogue Converter
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I
n
V0 \ VREF
(VFS) 7/8
6/8
5/8
4/8
3/8
2/8
1/8
0
000 001 010 011 100 101 110 111 b2b1b0
Input Binary Code
Fig. 3.12 Transfer Characteristic of a 3-Bit
I Digital-to-Analogue
Converter
n
p
u
t
V
o
l
t
a
g
e
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