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Analysis of SOI technologies based on the TRAPPISTe prototype measurements E. Martin ¹, P. Álvarez ¹, L. Soung Yee ², E.Cortina ², C. Ferrer ¹ ¹ Universitat Autònoma de Barcelona, Bellaterra, Spain ² Université catholique de Louvain, Louvain-La-Neuve, Belgium Corresponding author: [email protected]; [email protected] Poster ID: N14-140 Abstract Monolithic pixel detectors in fully depleted (FD) Silicon On Insulator (SOI) technology have been developed and characterized. This poster presents the first measurements of the electrical characterization on single transistor test structures and a 3-transistor readout circuit. The results show how the substrate bias condition during the laser test play a dramatic role on the behavior . TRAPPISTe Diode Silicon-on-Insulator CMOS technology SOI technology can be used to create a particle detector by the realization of a diode in the bottom handle wafer and the integration of the readout electronics in the top active layer. The readout circuits are electrically insulated from the rest of the silicon wafer by means of a thick oxide layer (Buried Oxide) . Each layer can be optimized for its intended application; the bottom handle layer for the sensor can be made of high resistivity silicon. The possibility to deplete the sensor layer greatly improves the charge collection efficiency [1]. TRAPPISTe-1 Summary of TRAPPISTe process technology properties TRAPPISTe-1 WINFAB TRAPPISTe-2 LAPIS 2 µm FD-SOI 0.2 µm FD-SOI Top Active Layer Thickness 100 nm 50 nm Buried Oxide Layer Thickness 400 nm 200 nm ~500 µm ~300 µm P-type N-type 15-25 Ωcm 700 , 10K Ωcm Metal Layers 1 5 Polysilicon Layers 1 1 Properties Process Bottom Handle Layer Thickness Handle Layer Type Handle Layer Resistivity TRAPPISTe-2 The WINFAB technology is a 2um technology with thicker layer and a low resistivity handle wafer. A low resistivity handle wafer requires higher biasing to achieve full depletion which can affect the behavior of the devices in the top active layer. This technology was used to construct the first TRAPPISTE-1 test amplifier and readout circuits. TRAPPISTe is a research and development project with the aim of studying the feasibility of using SOI technology to develop monolithic particle detectors. Two chips have been fabricated: The LAPIS technology provides a ten times smaller feature size and a high resistivity handle wafer [2]. The smaller feature size and higher number of metal layers allows higher label of integration. The first TRAPPISTE pixel sensors with integrated amplifiers were a part of the TRAPPISTE-2 test device. Characterization of the TRAPPISTe-2 transistor Threshold Voltages Method of 2nd derivative Transistor in Test Area 2nd derivative for NMOS with Standard threshold voltage. Transistor Type Place Voltage Threshold T51, T52, T53 NMOS Core Standard Voltage T61, T62, T63 NMOS Core Low Voltage All of the transistors have a W/L of 10µm/2µm except for the I/O n-type Depleted MOS (DMOS) transistors which are size 2µm/10µm. Use of 2 methods (Linear-extrapolation F1(VG) and minimum of 2nd derivative F2(VG)) at two different biasing conditions (Vd=20mV and 50mV) to obtain Vth [3]. F1 (VG ) = F2 (VG ) = ID gm 3 = ( ( A · VG −Vth A 2 · VG −Vth ) ) F2(VG) is a more refined version of this measurement technique, which accounts for more complex mobility reduction mechanisms and effective channel length. Note that the second derivative shows a peak related to the charge control so that the determination of Vth from the peak position should be quite insensitive to the VG-dependent mobility and series-resistance effects due to the rapidly changing derivative near Vth. where: W A= μ0Cox VD L A= μ0Cox W L eff VD 3T readout circuit of the TRAPPISTe-2 3T transfer curves for TRAPPISTe-2 Laser Test Degradation of response due to back gate effect. A reset transistor M1 is used to place a bias voltage (Vvnreset) onto the detector node which clears any charge accumulated on the detector. Transistor M3 buffers the signal and is biased by transistor M8. The selection transistor M4, controlled by the signal Vnstore, places the signal onto a 37.5fF storage capacitor. When the signal on the storage capacitor is to be read out at the output, transistor M6 is opened via signal Vnread. The signal on the capacitor is buffered by transistor M5 which is biased by transistor M7. When a column is activated, the read transistors M6 in each pixel throughout the column are activated so that the information in that column is placed on the output pads. Electrical characterization of 3T Matrix with sweep of VBACK The pixels number six have a homogenous behavior due to their located near to the channel readout Conclusions The TRAPPISTe project is an R&D project to study the feasibility of developing monolithic radiation detectors in two SOI technologies. The measurement of test structures so far exhibits a strong dependence on back gate voltage. Future iterations of the TRAPPISTe chip will try to mitigate this effect. IEEE NSS/MIC 2012. Nuclear Science Symposium, Medical Imaging Conference October 29 - November 3, 2012, Disneyland Hotel, Anaheim, California Laser measurements were performed on pixels with 3T read-out architecture. Six columns of pixels were implemented. Movement of laser across pixels results in corresponding pixel response. References [1] G. F. Knoll, Radiation Detection and Measurement, 3rd ed. John Wiley & Sons, Inc., 2000. [3] SOIPIX Collaboration. http://rd.kek.jp/project/soi/ [2] D.Flandre, et al., “Fully depleted SOI CMOS technology for heterogeneous micropower, high-temperature or RF microsystems,” Solid-State Electronics, vol. 45, no. 4, pp. 541-549, 2001.