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CERN EDMS NO. CH-1211 Geneva 23 Switzerland REV. VALIDITY DRAFT REFERENCE Date: 04.05.2017 Radiation Hardness Assurance Protocol Document Active Penning and Pirani front-end Radiation to electronics includes new front-end of vacuum gauges installed in the ARCs and the DS of LHC. Vacuum gauges in the ARCs are active (i.e. integrating their own conditioning circuits with their sensor). They provide 0-10V signal along ND100 cables, over long distances (max 1km) to the alcoves where PLCs are installed. EQUIPMENT CONCERNED: DRAWINGS CONCERNED: DOCUMENTS CONCERNED: PE IN CHARGE OF THE ITEM: PROJECT LEADER: Pawel Krakowski Nikolaos Chatzigeorgiou Gregory Pigny DECISION OF THE PROJECT ENGINEER: DECISION OF THE PROJECT LEADER: Rejected. Rejected. Accepted by the Project Engineer, Accepted by the Project Leader. no impact on other items. Actions identified by the Project Engineer. Accepted by the Project Engineer, but impact on other items. Comments from other Project Engineers required. Final decision and actions by the Project Management. DATE OF APPROVAL: DATE OF APPROVAL: ACTIONS TO BE UNDERTAKEN: DATE OF IMPLEMENTATION: Note: When approved, an Engineering Change Request becomes an Engineering Change Order. This document is uncontrolled when printed. Check the EDMS to verify that this is the correct version before use. REFERENCE EDMS NO. REV. VALIDITY DRAFT Page 2 of 27 Contents Active Penning and Pirani front-end ................................................................................. 1 1. Project description ................................................................................................. 4 1.1 Purpose ............................................................................................................ 4 1.2 SUMMARY TABLE ............................................................................................... 5 1.3 pROJECT DESCRIPTION ...................................................................................... 6 1.3.1 MAIN FEATURES ................................................................................................ 6 2. rADIATION ENVIRONMENT...................................................................................... 7 3. Gauges Charactericstics.......................................................................................... 9 3.1 Piezo gauge ...................................................................................................... 9 3.1 Pirani/Penning Gauge ......................................................................................... 9 3.2 Electrical Characteristics of the Design Active components .................................... 10 3.2.1 3.2.2 3.2.3 3.2.4 3.3 4-20MA CURRENT LOOP TRANSMITTER .............................................................. PIEZO CONDITIONING CIRCUIT DESING ............................................................ FURTHER PIRANI CONDITIONING STAGES DESCRIPTION ..................................... PENNING DESIGN ......................................................................................... Power Supply .................................................................................................. 10 14 18 19 22 4. Radiation tests of components ............................................................................... 23 5. SysteM radiation test ........................................................................................... 23 6. Project SCHEDULE ............................................................................................... 24 7. Costs Estimation .................................................................................................. 24 8. comments (compulsory) ....................................................................................... 25 9. comments (if required)......................................................................................... 25 10. comments (If any) ............................................................................................... 25 CERN CH-1211 Geneva 23 Switzerland EDMS NO. REV. VALIDITY DRAFT REFERENCE Date: 04.05.2017 This document is uncontrolled when printed. Check the EDMS to verify that this is the correct version before use. REFERENCE EDMS NO. REV. VALIDITY DRAFT Page 4 of 27 1. PROJECT DESCRIPTION 1.1 Purpose The purpose of this document is to provide technical specification for the design of radiation tolerant conditioning electronics for all three types of gauges (Piezo, Pirani and Penning) installed in the ARCs of the LHC, able to stand cumulated dose beyond year 2035. The new radiation tolerant circuits must be ready to be installed during LS2 in the DS areas and during LS3 in the ARCs. Table 1 shows the number of concerned gauges in the DS and ARCs. Table 1 – Total number of gauges conditioning electronic in DS and ARC. Active gauges DS ARC Penning # 16 324 Pirani # 16 324 Piezo # 48 120 The new design gives the opportunity to solve other issues not related to R2E, although important in the point of view of LHC operation, such as: The signal transmission, 0-10V over long distances must be replaced by 4-20 mA signal transmission. Calibration of the Pirani circuit has to be improved; the existing circuit is very difficult and time consuming. Each design is strongly dependent on the gauge type and reference, the strategy for the next 10-20 years concerning vacuum instrumentation in the DS and ARCs needs to be clearly defined. REFERENCE EDMS NO. REV. VALIDITY DRAFT Page 5 of 27 1.2 SUMMARY TABLE Equipment Responsible TE-VSC-ICM Person Responsible G.Pigny; N. Chatzigeorgiou; P.Krakowski Project Name Radiation tolerant design of Penning, Pirani and Piezzo front-end Short Description Deployment Plan LS2 – 2019 (DS), LS3-2022(ARCs) Criticality (See EDMS document x.z) Installation Location LHC DS and ARCs Expected Life time 10 years Number of units to be 848 installed EDMS Project folder Tested version Schematic EDA (Versions in different rows) XXX REFERENCE EDMS NO. REV. VALIDITY DRAFT Page 6 of 27 1.3 PROJECT DESCRIPTION Following project is the consequence of radiation test performed by TE-VSC-ICM section. The impact of the ionizing radiation on the DS and ARCs pressure gauges electronics can be critical for machine operation, as they generate alarms to vacuum and cryogenic systems. In order to minimise potential effects of radiation, currently installed gauges front-ends have been offset by ~15 m from the gauges heads installed directly on the MQ, to the MB surroundings, where the annual dose is ~10 times lower. Neither shielding nor any other specific prevention has been deployed. All three gauges conditioning circuits, critical for LHC operation, are installed directly in the accelerator tunnel and are constantly exposed to ionising radiation. At these sites main dose contribution comes from beam interaction with residual gas, and currently in average is << 10 Gy.y-1. FLUKA simulations dedicated for ARCs for the next 10 year of operation predict that the annual dose exceed 10 Gy.y-1 in some locations. The signal conditioning circuit for the Pirani sensor is CERN designed, with maximum measurement range reaching 10-4 mbar, while the ones for the Penning sensor are COTS capable to measure pressure down to ~10-11 mbar. In order to survive RUN-2 (2015-2018), RUN-3 (2020-2022), and challenging High Luminosity LHC (2035+) ~10 years (Table 1) of operation these electronics must withstand at least a Total Ionising Dose TID| of 250-300 Gy 1.3.1 DESIGN MAIN FEATURES In this sub-section the main features and performances should be listed in form of bullet points. Example: Feature 1 Feature 2 Feature 3 Feature 4 Certification of components and design for 500 Gy (x8 safety factor) or 250 Gy (x4 safety factor); Change from 0-10V to 4-20mA signal readout; Design modularity with exchangeable Penning, Pirani, Piezo and PS cards Improvement of Pirani calibration circuit Table 2 REFERENCE EDMS NO. REV. VALIDITY DRAFT Page 7 of 27 2. RADIATION ENVIRONMENT by the originator and/or PE The RADWG and the MCWG will provide the radiation levels and the spectra for the exposed areas, based on the information given by the equipment responsible. The information has to be reported in Table 4. The value of Dose, High Energy Hadrons (HEH) and 1MeV equivalent neutron fluences have to be normalized per year and the assumption on the integrated luminosity or the beam losses have to mention in the table. Location DCUM Dose [Gy/y] HEH [pp/cm2] LHC tunnel Table 3 1MeV [n/cm2] REFERENCE EDMS NO. REV. VALIDITY DRAFT Page 8 of 27 In order to take into account the radiation spectra, the Normalized Reverse Integral (NRI) is used to quantify the hardness of an environment and is defined as the proportion of HEH (hadrons above 20 MeV) above an energy E (MeV). Some examples can be found in the Table 6. Environment LHC tunnel Table 4 REFERENCE EDMS NO. REV. VALIDITY DRAFT Page 9 of 27 3. GAUGES CHARACTERICSTICS 3.1 PIEZO GAUGE Active piezo resistive gauge installed in the ARCs of the LHC (Huba 680.99713) is the modified version of the standard reference (Huba 680.7061101) in which voltage regulators have been removed leaving only differential amplifier in order to withstand higher radiation doses (up to 200Gy). It has the following characteristics: Pressure range: 0-1.6 bar Overload: max 8 bar Output: 0-10 VDC Power supply: +/13.5 VDC Linearity: <+/- 0.25% Temperature range: 0-70°C Electrical connector: DIN 43650 Flange: KF 16 DIN 28403 The output has no voltage limitation and it is directly influenced by the fluctuation of the power supply. What is more it has no protection against short circuit. The power supply input has neither EMC protection, nor against polarity swapping. 3.1 PIRANI/PENNING GAUGE Combined Pirani-Penning gauges installed in the ARCs of the LHC, are modified versions of the standard reference active gauges PKR 251 or 261. The sensor part is removed from its electronics. Aluminium block adapter with connectors and temperature compensation for the Pirani are assembled together with the sensors. They can be oredered throught the following reference at the CERN store: 18.20.50.011.5 PKR 251 on KF25 for Arc Insulation vacuum 18.20.50.015.1 PKR 261 on CF40 for Arc Beam Vacuum Characteristics: Measuring range (air, N2): 2x10-9…1x10-2 mbar Penning operating voltage: <3.3kV Penning operating current: <500uA Temperature compensation (Pirani): PTC = 1.5kΩ, α = 3.10-3 Ω/°C Filament resistance (Pirani): ~ 65 Ω at room temperature REFERENCE EDMS NO. REV. VALIDITY DRAFT Page 10 of 27 3.2 ELECTRICAL CHARACTERISTICS OF THE DESIGN ACTIVE COMPONENTS 3.2.1 4-20MA CURRENT LOOP TRANSMITTER 3.2.1.1 DESCRIPTION Current loop transmitters will be used as final stage between the sensor and the acquisition system (PLC). Use of 4-mA to 20-mA (4−20 mA) current loops has become the standard in the process-control industry due to their increased resistance to noise compared to voltagemodulated signals. Current loops are a method of transmitting information. The information is carried as a current of varying levels of intensity, representing a continuum of values similar to the voltage output of an analog-to-digital (A/D) converter, but without the noise and line-length concerns. For the 4−20-mA current loop, 4 mA normally represents the zero-value output of the sensor, and 20 mA represents the full-scale output. Figure 1 Current loop example. A typical current loop includes a sensor, transmitter, receiver, and current source (or power supply). The sensor measures a physical parameter (e.g., pressure) and provides an output voltage. The transmitter converts the sensor’s output to a proportional 4−20-mA dc current. The receiver converts the 4−20-mA current into a voltage for additional processing and/or display. The current source supplies the power for the entire system. The power supply can be provided from the transmitter or the receiver. Wire-break detection is simple due to the 4-mA offset of the zero value. (If the receiver reads 0 mA, there is a break in the circuit.) REFERENCE EDMS NO. REV. VALIDITY DRAFT Page 11 of 27 In the ARCs of LHC the maximum cable length can exceed 800 meters. Next table summarizes the lengths and linear resistances of cables in the ARCs of LHC. The cable reference is ND100 with 50 twisted pairs, and wires of 0.25 mm2 cross section each. The linear resistance is 75 Ω/km (for each one of the 100 wires). Table 5. Cable lengths in the ARCs of LHC ARC Max. Cable Length [m] Wire Linear Resistance [Ω] 12 ~750 57 23 ~860 65 34 ~750 57 45 ~730 55 56 ~830 62 67 ~720 54 78 ~720 54 81 ~720 54 3.2.1.2 MINIMUM LOOP VOLTAGE Following the information of table 4, concerning the cable lengths in the ARCs of LHC, a maximum required power for the loop can be calculated. For the calculation, a cable of 1km length is assumed. Irrespective of the position of the power (either from transmitter or from receiver), the loop consumes max. 20mA full scale. Transducer Side + PLC Side - + 75Ω 20mA + Wiring Resistance DC 25Ω - 75Ω + GND1 1km Figure 2. Simplified schematic of current loop system. REFERENCE EDMS NO. REV. VALIDITY DRAFT Page 12 of 27 In a current loop, the power supply must emit voltage equal to or greater than all the voltage drops in the system combined. The PLC input impedance is 25 Ohms for current measurements, thus the full-scale voltage induced is 0.5 VDC. Then, the resistance of the wire, assuming 1km length of ND100 cable, is 75 Ohm per wire. Each wire will drop the voltage by 1.5 VDC. Any excess loop voltage is dropped across the current transmitter. Due to the relative low current, this is only a small amount of power, which creates little heat. The “transducer side” representation of XXXX, is assumed to be a current loop transmitter (XTR series). These transmitters require a power supply typically of 24 VDC (from 7V to 40V). Thus, the total voltage required for the loop is the sum of all the above, which is at least 27.5 VDC (from 10.5V to 43.5V). 3.2.1.3 POWER SOURCE AT RECEIVER SIDE One solution is to power the loop from the receiver side, or “PLC side”. The analog input module of the PLC can be configured for this operation (see table 3), namely the 2-wire transducer option. The power supply voltage for the loop is provided from the PLC and it is in the order of 16.4 VDC (20mA*820Ω). Voltage drops across the wires and the termination resistance of the PLC are in total 3.5 VDC. Thus, the loop-powered transmitter will operate with 12.9 VDC, which is sufficient for most of the available transmitters in the marker. Table 6. Loop- powered transmitters. Part Supply Range [V] Max Nonlinearity [%] Input Range [V] Ref. Voltage [V] / [ppm/°C] Price [€] XTR115/116 XTR117 7.5 to 36 7.5 to 40 0.003 0.003 0-5 / 0-10 0-5 / 0-10 2.5, 4.096 / ±35 Not included 3 2 Transducer Side + PLC Side - + 75Ω 20mA DC Wiring Resistance + 25Ω - 75Ω + - GND1 1km Figure 3. Loop-powered transmitters. Ad. Info REFERENCE EDMS NO. REV. VALIDITY DRAFT Page 13 of 27 3.2.1.4 POWER SOURCE AR THE TRANSMITTER SIDE Powering the loop from the transmitter side or the transducer side is similar to the representation of figure 10. On this setup, the designer can easily adapt power requirements of the loop by adding extra power sources on his design. Especially for very long cable lengths, a power supply with at least 27.5 VDC is required. At the other hand, it increases the complexity of the system and the cost. A trade off which needs to be well understood. Next table illustrates some of these type of transmitters. Table 7. 4-20mA transmitter. Part XTR110 XTR111 Supply Range [V] Max Nonlinearity [%] Input Range [V] Ref. Voltage [V] / [ppm/°C] Price [€] 13.5 to 40 7 to 44 0.005 0.002 0-5 / 0-10 0-5 / 0-10 10 / 35 3 / 30 12 1.5 Ad. Info 3.2.1.5 EXTERNAL TRANSISTOR FOR POWER DISSIPATION An external transistor, Q1, conducts the majority of the full-scale output current. Power dissipation in this transistor can approach 0.8W with high loop voltage (40V) and 20mA output current. The transmitters are designed to use an external transistor to avoid on-chip thermalinduced errors. Heat produced by Q1 will still cause ambient temperature changes that can affect the transmitter. To minimize these effects, locate Q1 away from sensitive analog circuitry. Table 8. External transistors for current loop transmitters Part TIP29C TIP31B TIP41C MJE3440 IRF9510 Transmitter Package Price [€] XTR115/116 TO-220 0.5 TO-220 SOT-32 TO-220 0.5 0.5 0.4 XTR117 XTR110 Ad. Info REFERENCE EDMS NO. REV. VALIDITY DRAFT Page 14 of 27 3.2.2 PIEZO CONDITIONING CIRCUIT DESING 3.2.2.1 DESCRIPTION The main features of this design are: The piezo card must provide the power supply of +/-13.5VDC Output voltage readout the 0-10V into 4-20 mA to the PLC. The +/-13.5 VDC power supply must be independent of the other internal power supplies used of the Pirani and Penning cards. As the voltage measurement is directly proportional to the excitation voltage of the bridge, the precision of the power supply +/-13.5V will be determined by: the precision of the 0-10V to 4-20mA converter the resolution of the ADC used in the PLC to convert the 4-20mA (12 bits) REFERENCE EDMS NO. REV. VALIDITY DRAFT Page 15 of 27 3.2.2.2 PIRANI BRIDGE OPERATIONAL AMPLIFIERS – 1ST STAGE The first stage of the pirani design consists of a bridge supplied in retroaction by an operational amplifier associated with a current booster transistor (BJT). Concerning the operational amplifier, they are 4 major concerns in the bridge circuit: 1. Bridge excitation The filament of the bridge is the only active element on the Piezo gauge side. The bridge is continuously supplied in order to maintain constant temperature of the filament (i.e constant resistance of the filament) from the range of the atmospheric pressure (ATM) to the high vacuum (HVAC). This corresponds to the output voltage excursion of the operational amplifiers from 6V (ATM) to 0.7V (HVAC), this implies that the first operational amplifier must be able to deliver rated output voltage >±6V at ±15VDC supplies. 2. Input CMV of the bridge amplifier In a steady state, if the excitation voltage of the bridge (Ve) can change by 1%, the common mode voltage at the output of the bridge will change by 1/n % (n>1) of Ve, depending on the values of each element of the bridge. If the effect of this variation is allowed to ¼ of the LSB of an ADC of k bits with a voltage reference Vref, then the differential amplifier must have a common-mode gain (Acm) less than: Acm < (100.n.Vref)/(4.2k.Ve) Considering a differential amplifier with a differential gain Ad: CMR > 20.log(Ad/Acm) 1. Table 9, CMR budget analysis Differential Gain [V/V] 1 1000 Ref. Voltage [V] 15V 15V n 2 2 Excitation Voltage [V] 6V 6V Num. Bits 12 bits 12 bits CMR [dB] 30.3 90.3 2. Differential gain still has to be defined, but since the circuit will operate at low frequency (< 1kHz), most of the op-amps offer CMR higher than 80dB in this frequency range. In order to meet worst-case defined condition the amplifier needs to have a CMR greater than 90dB. 3. Offset voltage and offset drift Offset voltage adds constant error to the circuit. For a simpler circuit design, external potentiometers should be avoided (except the ones for pressure calibration). Thus, an opamp with very low or ultra-low offset must be foreseen. In addition, the first stage and each stage in chain will contribute to the final offset. The range of the total offset should not affect more than ½ LSB. Assuming 12 bits of resolution and 10V full scale, the offsets ≤ 10V/(2.212)=1.2 mV in total could be accepted. For three complete stages, each stage must show the offset ≤ 1.2mV/3 = 400 uV. Moreover, the offset drift must be kept low. For the same analysis, an op-amp with less than 400uV/°C must be considered. The supply of the op-amp must be bipolar (±15V or equivalent) for better zeroing. REFERENCE EDMS NO. REV. VALIDITY DRAFT Page 16 of 27 4. Noise External noise sources can dominate in many cases, so we need to consider the effect of source resistance on overall operational amplifier noise performance. At low source impedance, the lower voltage noise of a bipolar operational amplifier is supeerior. Above about 15KOhm source resistances (rule of thumb) low-noise FET op-amps are recommended by literature, for lower total noise. Our bridge is low source resistance; thus we can consider a bipolar input operational amplifier. In addition, the noise of the first stage will dominate the noise contribution of the rest of the stages. It is therefore important the selection of an op-amp with very low noise figure. From all above specs, an online search gives the following results in the table below. Table 10. Candidates for Pirani 1-st stage. Part Output Swing [V] CMVR [dB] Offset [V] Offset drift [V/°C] Supply [V] Input Noise [V/√Hz] Price [€] Ad. Info OP-77* OPA27/37 ±14 120 55u 0.3u ±22 10n ±13.8 100 100u 0.4u ±22 4.5n 9 3 TPG300 RadHard ±14 110 100u 1.5u ±15 22n AD706 5 REFERENCE EDMS NO. REV. VALIDITY DRAFT Page 17 of 27 3.2.2.3 BIPOLAR JUNCTION TRANSISTOR (BJT) FOR THE BRIDGE 1ST STAGE The BJT transistor is controlled by the bridge operational amplifier and drives the bridge with current. This BJT must meet following specifications (NPN for this study): 1. Assuming collector excitation voltage of +15V (worst case 0-Ohm collector resistor) and emitter directly to GND, a VCE max ≥ +15V is required. 2. The continuous collector current must be ≥ 100 mA (40mA ±15% is the nominal Pirani current within the calibration limits and 10mA more for the current for the other side of the bridge – in total 50mA ±15%.) 3. Maximum dissipated power is calculated for the worst-case scenario. For this topology the worst case occurs when one side of the bridge is shorted, then the emitter would be directly connected to ground. Assuming the collector resistance of approx. of 200 Ohms, and transistor ON-resistance negligible, the total power would be of <1.25 W. 4. Nominal dissipated power, calculated for normal operation, in which the full-scale output is 6V and the nominal current of the bridge is 50mA. Thus, the transistor will dissipate power (15V-6V)*50mA=0.45 watts. 5. The junction-to-case thermal resistance value of the transistor is the main thermal criteria for heatsink. For normal operation (from point 4) the dissipated power is P normal=0.45W. Thus, the temperature of a case with Rthermal=x °C/W will go above ambient temperature by Tcase=Rthermal*Pnormal. For example, a transistor with Rthermal=50 °C/W, which dissipates 0.5 watts of power will increase its case temperature by Tcase=50*0.5 °C=25 °C above ambient. 6. The current gain of the transistor, hFE, must be minimum in the order of 100-±20% for the collector current in the range of 1mA to 50mA. Low hFE performance transistors will force the bridge operational amplifier to swing close to the supply rails, which might saturate the opamp at the extremities. Table 11. BJT candidates for bridge current booster Part VCE [V] VCB [V] VBE [V] IC [A] Power [W] Thermal Resistance [°C/W] Price [€] Ad. Info 2N1711 2N4401 2N3019 50 40 80 75 60 140 7 6 7 0.5 0.6 1 0.8 0.625 0.8 58 83.3 30 1 0.014 1 TPG300 REFERENCE EDMS NO. REV. VALIDITY DRAFT Page 18 of 27 3.2.3 FURTHER PIRANI CONDITIONING STAGES DESCRIPTION 1. The most important requirement of further stages is very high input impedance of the amplifier, as the source resistance of previous stage will be much higher than 15kOhm. A DiFET/JFET input precision OP-AMP would maintain noise levels in very low magnitude. 2. Low offset and drift offset as this accumulates from the all the stages for calculations. 3. Bipolar power supply and output voltage swing more than ±12V. Table 12. Candidates for conditioning stages operational op-amps. Part LF441* OPA121 OPA124 AD711 Output Swing [V] Input Offset [V] Offset drift [V/°C] Supply [V] Input Noise [V/√Hz] Price [€] Ad. Info ±13 ±12 ±12 ±13 jFET DiFET DiFET BiFET 0.5m 2m 250u 250u 10u 3u 2u 3u ±18 ±15 ±15 ±15 35n 6n 6n 45n obsolete 12 9 3 TPG300 Rad-Hard The original TPG300 design has several BJT transistors on the feedback of the 3-rd stage. This stage is a piece-wise linear amplifier that switches gains according to the input voltage. Table 13. Feedback BJT NPN candidates Part BC850C* BC547B VCE [V] VCB [V] VBE [V] IC [A] Power [W] Price [€] Ad. Info 45 45 50 50 5 6 0.1 0.1 0.25 0.5 0.016 0.07 TPG300 REFERENCE EDMS NO. REV. VALIDITY DRAFT Page 19 of 27 3.2.4 PENNING DESIGN 3.2.4.1 LOGARITMIC STAGE OR EQUIVALENT The input stage of the Penning measuring chain has to convert input current to voltage. Input currents of this stage vary from 1pA to 100uA according to pressure. A Log amplifier may be considered for the study of components. The current is performed at the low side of a High Voltage potential thus no significant CMV is introduced; but the sign of the current is negative (conventional flow of current). In general, Log circuits take advantage of the voltage-current relationship of a trans-diode configuration of the form: 𝑉𝑜 = − 𝑘𝑇 𝐼𝑖𝑛 ln 𝑞 𝐼𝑠 Where k is the Boltzmann’s constant (1.38062x10-23J/K), q is the electron charge (1.60219x10-19C), T is the absolute temperature and Is the reverse saturation current of the junction. One shortcoming of a Log circuit is the quantity of Is and kT/q are highly temperature dependent. The quantity of Is can be negligible if we use a matched pair transistor. While we eliminate the effect of Is, the scale factor kT/q is proportional to absolute temperature. One solution is to compensate by using a thermistance (PTC or NTC?) with a value inversely proportional to absolute temperature as the smaller of the two resistors in a voltage divider configuration. This voltage divider configuration will set the final gain of the Log circuitry. 1. A1 and A2 must be fully compensated FET input OP-AMPS 2. The input bias current ≤ 100fA over a well specified temperature range 3. Low offset and offset drift (>500uV max, 1uV/°C) 4. Bipolar supply Figure 4. Temp Compensated Log circuit. REFERENCE EDMS NO. REV. VALIDITY DRAFT Page 20 of 27 Table 14, Electrometer grade op-amp candidates Part Input Bias [A] Output [V] Input Offset [V] Offset drift [V/°C] Supply [V] Input Noise [V/√Hz] Price [€] Ad. Info AD549K/J OPA128 100f/250f 75f ±12 jFET 500u 15u ±15 90n ±13 DiFET 500u 5u ±15 92n 44/30 70 TPG300 RadHard ADA4530 LMC6001 LMP7721 OPA129 ±20f 25f 40f 100f +5 +5 ±13 DiFET 100u 350u 50u 2m 0.5u 2.5u 1.5u 10u ±8 +16 +5.5 ±15 14n 22n 6.5n 15n 20 14 9 10 Volotek In addition to the OP-AMPS, a matched pair bipolar transistor (PNP) is required to eliminate the temperature dependency of Is. Table 15, PNP matched pair transistor candidates for logarithmic stage Part VCE [V] VCB [V] VBE [V] IC [A] Power [W] hFE1/hFE2 VCE=5V, IC=100u VBE1-VBE2 [V] Price [€] Ad. Info 2N3811 MAT03 NST45010MW6T1G BCM62B 60 36 45 45 60 36 50 50 5 5 5 5 50m 20m 100m 100m 0.5 0.5 0.38 0.39 90% 97% 90% 5m 100u 2m obsolete 15€ 0.2 0.3 TPG300 TO-78 SMD SMD 3.2.4.2 FURTHER STAGES Any further stage for the Penning circuitry can be of the same type as of chapter 4.2.3 which is for the further stages of the Pirani circuit. 3.2.4.3 HIGH VOLTAGE GENERATION High Voltage is generated by means of High-Frequency transformation. Therefore, the active components of such technology are: - DC adjustable voltage regulator Table 16, Adjustable Regulator candidates Part LM317 Vmin [V] Vmax [V] Imax [A] Regulation Price [€] Ad. Info 1.25 37 1.5 0.01% 0.9 TPG300 REFERENCE EDMS NO. REV. VALIDITY DRAFT Page 21 of 27 - Royer oscillator with 2 low power general purpose NPN transistors. Table 17, NPN Transistor candidates for Royer oscillator. Part 2N3019 BCP56-16 VCE [V] VCB [V] VBE [V] IC [A] Power [W] Price [€] Ad. Info 80 80 140 100 7 5 1 1 1 1.6 1.2 0.3 TPG300 SMD 3.2.4.4 HIGH FREQUENCY TRANSFORMER Technical specifications?? Saturable core transformer Input voltage? Output voltage? Isolation voltage between primary/secondary? Leakage current between primary/secondary? Secondary/ground?... Size? Frequency? 3.2.4.5 SIGNAL ISOLATION Signal isolation is required to avoid any ground loops between the gauges, the front-end electronics and the acquisition system. The isolation amplifier needs to have an input range of 0-10V and the same output range with a fixed unity gain. It is also required to have double bipolar power supplies (isolated). Some candidates of isolation amplifiers. Part Vin [V] Vout [V] ISO124 ISO122 ±12.5 ±12.5 ±12.5 ±12.5 Power Supply [V] ±18 ±18 ±18 ±18 Gain Nonlinearity [%] Isolation Volatge [VRMS] Price [€] 0.01 0.02 1500 1500 15 18 Ad. Info REFERENCE EDMS NO. REV. VALIDITY DRAFT Page 22 of 27 3.3 POWER SUPPLY Power is required to supply all the electronics of active gauges. The power supply module would be housed in one modular card and will serve all the electronics within the crate. Total required power is still to be defined… The system requirements are: ±15 VDC1 for all the operational amplifiers of the conditioning stages. +20 VDC1 for powering the penning high frequency transformer. ±15 VDC2 isolated from 1. For isolation amplifiers and signal transmitters. REFERENCE EDMS NO. REV. VALIDITY DRAFT Page 23 of 27 4. RADIATION TESTS OF COMPONENTS To be discussed in details with Salvatore 5. SYSTEM RADIATION TEST REFERENCE EDMS NO. REV. VALIDITY DRAFT Page 24 of 27 6. PROJECT SCHEDULE The following project is a part of Vacuum R2E Work Package, described in details in SUB-WORK PACKAGE: R2E (RADIATION TO ELECTRONICS). Schedule foreseen for this project is given below (Figure 5). The duration of the main phases, such as prototyping, design, installation, testing and commissioning is avilable for the different tasks. Schedule Activity 2016 2017 2018 2019 2020 2021 2022 Study Design & Proto Proto rad test • Task 1: Active gauges in the arc DS series DS rad test DS installation DS commissioning ARC series ARC rad test ARC installation ARC commissioning Study Figure 5. Schedule for the SUB-WORK PACKAGE: R2E. Task 2: Active gauges in LSSctronics LSS Design & Proto Series Installation Commissioning Study 7. COSTS ESTIMATION Design & Proto • Task 3: 24 VDC local power Modification IT supply for fixed pumping Commissioning IT groups Modification LSS Commissioning LSS To be included from R2E WP 2023 2024 2025 REFERENCE EDMS NO. REV. VALIDITY DRAFT Page 25 of 27 8. COMMENTS (COMPULSORY) 9. COMMENTS (IF REQUIRED) 10. COMMENTS (IF ANY) by the Project Engineer by other Project Engineers by the Project Leader REFERENCE EDMS NO. REV. VALIDITY DRAFT Page 26 of 27 ENGINEERING CHANGE ORDER (ECO) FOLLOW-UP OF ACTIONS COMMENTS ADDITIONAL INFORMATION SITE ACTIVITIES COMPLETED LAYOUT DRAWINGS UPDATED IN CDD TESTS COMPLETED FINAL STATUS IMPLEMENTATED ABANDONED REFERENCE EDMS NO. REV. VALIDITY DRAFT Page 27 of 27