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IEP on Synthesis of Digital Design 2007
Combinational Circuits
Combinational Circuits
S. Sundar Kumar Iyer
1
IEP on Synthesis of Digital Design 2007
Combinational Circuits
Acknowledgement

Slides taken from
http://bwrc.eecs.berkeley.edu/IcBook/index.htm
which is the web-site of “Digital Integrated Circuit – A Design
Perspective” by Rabaey, Chandrakasan, Nicolic
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IEP on Synthesis of Digital Design 2007
Combinational Circuits
Outline

Static Circuits

Complementary CMOS

Pseudo NMOS

Pass Transistor

Dynamic Circuits

Domino Logic
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Combinational Circuits
IEP on Synthesis of Digital Design 2007
Combinational vs. Sequential Logic
In
Combinational
Logic
Circuit
In
Out
Out
Combinational
Logic
Circuit
State
Combinational
Output = f(In)
Sequential
Output = f(In, Previous In)
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IEP on Synthesis of Digital Design 2007
Combinational Circuits
Static CMOS Circuit
•At every point in time (except during the switching
transients) each gate output is connected to either
VDD or Vss via a low-resistive path.
•The outputs of the gates assume at all times the value
of the Boolean function, implemented by the circuit
(ignoring, once again, the transient effects during
switching periods).
•This is in contrast to the dynamic circuit class, which
relies on temporary storage of signal values on the
capacitance of high impedance circuit nodes.
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IEP on Synthesis of Digital Design 2007
Combinational Circuits
Complementary CMOS
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Combinational Circuits
IEP on Synthesis of Digital Design 2007
Static Complementary CMOS
VDD
In1
In2
PUN
InN
In1
In2
InN
PMOS only
F(In1,In2,…InN)
PDN
NMOS only
PUN and PDN are dual logic networks
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NMOS Transistors
in Series/Parallel Connection
IEP on Synthesis of Digital Design 2007
Combinational Circuits
Transistors can be thought as a switch controlled by its gate signal
NMOS switch closes when switch control input is high
A
B
X
Y
Y = X if A and B
A
X
B
Y
Y = X if A OR B
NMOS Transistors pass a “strong” 0 but a “weak” 1
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IEP on Synthesis of Digital Design 2007
PMOS Transistors
in Series/Parallel Connection
Combinational Circuits
PMOS switch closes when switch control input is low
A
B
X
Y
Y = X if A AND B = A + B
A
X
B
Y
Y = X if A OR B = AB
PMOS Transistors pass a “strong” 1 but a “weak” 0
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Combinational Circuits
IEP on Synthesis of Digital Design 2007
Threshold Drops
VDD
PUN
VDD
S
D
VDD
D
0  VDD
VGS
S
CL
VDD  0
PDN
D
VDD
S
CL
0  VDD - VTn
CL
VGS
VDD  |VTp|
S
CL
D
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IEP on Synthesis of Digital Design 2007
Combinational Circuits
Complementary CMOS Logic Style
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IEP on Synthesis of Digital Design 2007
Combinational Circuits
Example Gate: NAND
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IEP on Synthesis of Digital Design 2007
Combinational Circuits
Example Gate: NOR
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Combinational Circuits
IEP on Synthesis of Digital Design 2007
Complex CMOS Gate
B
A
C
D
OUT = D + A • (B + C)
A
D
B
C
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Combinational Circuits
Properties of Complementary CMOS Gates
Snapshot
IEP on Synthesis of Digital Design 2007
•High noise margins:
VOH and VOL are at VDD and GND, respectively.
•No static power consumption:
There never exists a direct path between VDD and
VSS (GND) in steady-state mode.
•Comparable rise and fall times:
(under appropriate sizing conditions)
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IEP on Synthesis of Digital Design 2007
Combinational Circuits
CMOS Properties
Full rail-to-rail swing; high noise margins
 Logic levels not dependent upon the relative
device sizes; ratioless
 Always a path to Vdd or Gnd in steady state;
low output impedance
 Extremely high input resistance; nearly zero
steady-state input current
 No direct path steady state between power
and ground; no static power dissipation
 Propagation delay function of load
capacitance and resistance of transistors

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Combinational Circuits
IEP on Synthesis of Digital Design 2007
Switch Delay Model
Req
A
A
Rp
A
Rp
Rp
B
Rn
Rp
CL
Cint
A
Rn
A
Cint
A
NAND2
Rp
A
B
Rn
B
INV
CL
Rn
Rn
A
B
CL
NOR2
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Combinational Circuits
IEP on Synthesis of Digital Design 2007
Input Pattern Effects on Delay
Delay is dependent on the
pattern of inputs
 Low to high transition

Rp
A
Rp
 both inputs go low
B
Rn
– delay is 0.69 Rp/2 CL
CL
B
Rn
A
 one input goes low
– delay is 0.69 Rp CL

High to low transition
 both inputs go high
Cint
– delay is 0.69 2Rn CL
 one input goes high
– delay is 0.69 2Rn CL+ Rn Cint
or 0.69 2RnCL
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Combinational Circuits
IEP on Synthesis of Digital Design 2007
Delay Dependence on Input Patterns
3
Input Data
Pattern
Delay
(psec)
A=B=01
67
A=1, B=01
64
A= 01, B=1
61
0.5
A=B=10
45
0
A=1, B=10
80
A= 10, B=1
81
A=B=10
2.5
Voltage [V]
2
A=1 0, B=1
1.5
A=1, B=10
1
-0.5
0
100
200
time [ps]
300
400
NMOS = 0.5m/0.25 m
PMOS = 0.75m/0.25 m
CL = 100 fF
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Combinational Circuits
IEP on Synthesis of Digital Design 2007
Transistor Sizing
Rp
2 A
Rp
B
Rn
2
B
2
Rn
A
Rp
4 B
2
CL
Cint
Rp
4
Cint
A
1
Rn
Rn
A
B
CL
1
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IEP on Synthesis of Digital Design 2007
Transistor Sizing a Complex
CMOS Gate
A
B
8 6
C
8 6
Combinational Circuits
4 3
D
4 6
OUT = D + A • (B + C)
A
D
2
1
B
2C
2
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Combinational Circuits
IEP on Synthesis of Digital Design 2007
Fan-In Considerations
A
B
C
D
A
CL
B
C3
C
C2
D
C1
Distributed RC model
(Elmore delay)
tpHL = 0.69 Reqn(C1+2C2+3C3+4CL)
Propagation delay deteriorates
rapidly as a function of fan-in –
quadratically in the worst case.
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Combinational Circuits
IEP on Synthesis of Digital Design 2007
tp as a Function of Fan-In
1250
quadratic
tp (psec)
1000
Gates with a
fan-in
greater than
4 should be
avoided.
750
tpH
500
tp
L
250
tpL
linear
H
0
2
4
6
8
10
12
14
16
fan-in
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Combinational Circuits
IEP on Synthesis of Digital Design 2007
tp as a Function of Fan-Out
tpNOR2
tpNAND2
tpINV
tp (psec)
2
All gates
have the
same drive
current.
Slope is a
function of
“driving
strength”
4
6
8
10
12
14
16
eff. fan-out
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IEP on Synthesis of Digital Design 2007
Combinational Circuits
tp as a Function of Fan-In and Fan-Out
 Fan-in:
quadratic due to increasing
resistance and capacitance
 Fan-out: each additional fan-out gate
adds two gate capacitances to CL
tp = a1FI + a2FI2 + a3FO
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Fast Complex Gates:
Design Technique 1
IEP on Synthesis of Digital Design 2007
 Transistor
Combinational Circuits
sizing
 as long as fan-out capacitance dominates
 Progressive
InN
sizing
CL
MN
In3
M3
C3
In2
M2
C2
In1
M1
C1
Distributed RC line
M1 > M2 > M3 > … > MN
(the fet closest to the
output is the smallest)
Can reduce delay by more than
20%; decreasing gains as
technology shrinks
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Combinational Circuits
Fast Complex Gates:
Design Technique 2
IEP on Synthesis of Digital Design 2007
 Transistor
ordering
critical path
In3 1 M3
charged
CL
In2 1 M2
C2 charged
In1
M1
01
C1 charged
delay determined by time to
discharge CL, C1 and C2
critical path
01
In1
M3
CLcharged
In2 1 M2
C2 discharged
In3 1 M1
C1 discharged
delay determined by time to
discharge CL
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Fast Complex Gates:
Design Technique 3
IEP on Synthesis of Digital Design 2007
 Alternative
Combinational Circuits
logic structures
F = ABCDEFGH
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Fast Complex Gates:
Design Technique 4
IEP on Synthesis of Digital Design 2007
 Isolating
Combinational Circuits
fan-in from fan-out using buffer
insertion
CL
CL
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Fast Complex Gates:
Design Technique 5
IEP on Synthesis of Digital Design 2007

Combinational Circuits
Reducing the voltage swing
tpHL = 0.69 (3/4 (CL VDD)/ IDSATn )
= 0.69 (3/4 (CL Vswing)/ IDSATn )
 linear reduction in delay
 also reduces power consumption
But the following gate is much slower!
 Or requires use of “sense amplifiers” on the
receiving end to restore the signal level
(memory design)

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IEP on Synthesis of Digital Design 2007
Combinational Circuits
Sizing Logic Paths for Speed
Frequently, input capacitance of a logic path
is constrained
 Logic also has to drive some capacitance
 Example: ALU load in an Intel’s
microprocessor is 0.5pF
 How do we size the ALU datapath to achieve
maximum speed?
 We have already solved this for the inverter
chain – can we generalize it for any type of
logic?

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Combinational Circuits
IEP on Synthesis of Digital Design 2007
Buffer Example
In
Out
1
2
N
CL
N
Delay    pi  g i  f i 
i 1
(in units of tinv)
For given N: Ci+1/Ci = Ci/Ci-1
To find N: Ci+1/Ci ~ 4
How to generalize this to any logic path?
Reference: Sutherland, Sproull, Harris, “Logical Effort, Morgan-Kaufmann 1999.
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IEP on Synthesis of Digital Design 2007
Combinational Circuits
Summary
Sutherland,
Sproull
Harris
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IEP on Synthesis of Digital Design 2007
Combinational Circuits
Pseudo NMOS
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Combinational Circuits
IEP on Synthesis of Digital Design 2007
Ratioed Logic
VDD
Resistive
Load
VDD
Depletion
Load
RL
PDN
VSS
(a) resistive load
PMOS
Load
VSS
VT < 0
F
In1
In2
In3
VDD
F
In1
In2
In3
PDN
VSS
(b) depletion load NMOS
F
In1
In2
In3
PDN
VSS
(c) pseudo-NMOS
Goal: to reduce the number of devices over complementary CMOS
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Combinational Circuits
IEP on Synthesis of Digital Design 2007
Ratioed Logic
VDD
• N transistors + Load
Resistive
Load
• VOH = V DD
RL
• VOL =
F
In1
In2
In3
RPN
RPN + RL
• Assymetrical response
PDN
• Static power consumption
VSS
• tpL= 0.69 RLCL
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Combinational Circuits
IEP on Synthesis of Digital Design 2007
Active Loads
VDD
Depletion
Load
VDD
PMOS
Load
VT < 0
VSS
F
In1
In2
In3
PDN
VSS
depletion load NMOS
F
In1
In2
In3
PDN
VSS
pseudo-NMOS
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Combinational Circuits
IEP on Synthesis of Digital Design 2007
Pseudo-NMOS
VDD
A
B
C
D
F
CL
VOH = VDD (similar to complementary CMOS)
2
V OL
kp


2
k n  VDD – V Tn  V OL – -------------  = ------  V DD – VTp 
2 
2

kp
V OL =  VDD – V T  1 – 1 – -----(assuming that V T = V Tn = VTp )
kn
SMALLER AREA & LOAD BUT STATIC POWER DISSIPATION!!!
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Combinational Circuits
IEP on Synthesis of Digital Design 2007
Pseudo-NMOS VTC
3.0
2.5
W/Lp = 4
Vout [V]
2.0
1.5
W/Lp = 2
1.0
0.5
W/Lp = 0.5
W/Lp = 1
W/Lp = 0.25
0.0
0.0
0.5
1.0
1.5
2.0
2.5
Vin [V]
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Combinational Circuits
IEP on Synthesis of Digital Design 2007
Improved Loads (2)
VDD
M1
VDD
M2
Out
A
A
B
B
Out
PDN1
PDN2
VSS
VSS
Differential Cascode Voltage Switch Logic (DCVSL)
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Combinational Circuits
IEP on Synthesis of Digital Design 2007
DCVSL Example
Out
Out
B
B
A
B
B
A
XOR-NXOR gate
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IEP on Synthesis of Digital Design 2007
Combinational Circuits
Pass-Transistor Logic
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Combinational Circuits
IEP on Synthesis of Digital Design 2007
Pass-Transistor Logic
Inputs
B
Switch
Out
A
Out
Network
B
B
• N transistors
• No static consumption
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Combinational Circuits
IEP on Synthesis of Digital Design 2007
Example: AND Gate
B
A
B
F = AB
0
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Combinational Circuits
IEP on Synthesis of Digital Design 2007
NMOS-Only Logic
3.0
In
1.5m/0.25m
VDD
x
0.5m/0.25m
Out
0.5m/0.25m
Voltage [V]
In
Out
2.0
x
1.0
0.0
0
0.5
1
1.5
2
Time [ns]
45
Combinational Circuits
IEP on Synthesis of Digital Design 2007
NMOS-only Switch
C = 2.5V
C = 2.5 V
M2
A = 2.5 V
A = 2.5 V
B
B
Mn
CL
M1
VB does not pull up to 2.5V, but 2.5V - VTN
Threshold voltage loss causes
static power consumption
NMOS has higher threshold than PMOS (body effect)
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Combinational Circuits
NMOS Only Logic:
Level Restoring Transistor
IEP on Synthesis of Digital Design 2007
VDD
VDD
Level Restorer
Mr
B
A
Mn
M2
X
Out
M1
• Advantage: Full Swing
• Restorer adds capacitance, takes away pull down current at X
• Ratio problem
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Combinational Circuits
IEP on Synthesis of Digital Design 2007
Restorer Sizing
Voltage [V]
3.0
2.0
•Upper limit on restorer size
•Pass-transistor pull-down
can have several transistors in
stack
W/Lr =1.75/0.25
W/L r =1.50/0.25
1.0
W/Lr =1.0/0.25
0.0
0
100
200
W/L r =1.25/0.25
300
Time [ps]
400
500
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Combinational Circuits
Solution 2: Single Transistor Pass Gate with
VT=0
IEP on Synthesis of Digital Design 2007
VDD
VDD
0V
2.5V
VDD
0V
Out
2.5V
WATCH OUT FOR LEAKAGE CURRENTS
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Combinational Circuits
IEP on Synthesis of Digital Design 2007
Complementary Pass Transistor Logic
A
A
B
B
Pass-Transistor
F
Network
(a)
A
A
B
B
B
Inverse
Pass-Transistor
Network
B
B
A
F
B
B
A
A
B
F=AB
A
B
F=A+B
F=AB
AND/NAND
A
F=AÝ
(b)
A
A
B
B
F=A+B
B
OR/NOR
A
F=AÝ
EXOR/NEXOR
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Combinational Circuits
IEP on Synthesis of Digital Design 2007
Solution 3: Transmission Gate
C
A
C
A
B
B
C
C
C = 2.5 V
A = 2.5 V
B
CL
C=0V
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Combinational Circuits
IEP on Synthesis of Digital Design 2007
Resistance of Transmission Gate
30
2.5 V
Resistance, ohms
Rn
20
Rp
2.5 V
Rn
Vou t
Rp
10
0
0.0
0V
Rn || Rp
1.0
Vou t , V
2.0
52
Combinational Circuits
IEP on Synthesis of Digital Design 2007
Pass-Transistor Based Multiplexer
S
S
S
S
VDD
S
A
VDD
M2
F
S
M1
B
S
GND
In1
In2
53
Combinational Circuits
IEP on Synthesis of Digital Design 2007
Transmission Gate XOR
B
B
M2
A
A
F
M1
M3/M4
B
B
54
Combinational Circuits
IEP on Synthesis of Digital Design 2007
Delay in Transmission Gate Networks
2.5
2.5
V1
In
2.5
Vi
Vi-1
C
0
2.5
C
0
Vn-1
Vi+1
C
0
Vn
C
C
0
(a)
Req
Req
V1
In
Req
Vi
C
Vn-1
Vi+1
C
C
Req
Vn
C
C
(b)
m
Req
Req
Req
Req
Req
Req
In
C
CC
C
C
CC
C
(c)
55
IEP on Synthesis of Digital Design 2007
Combinational Circuits
Delay Optimization
56
Combinational Circuits
IEP on Synthesis of Digital Design 2007
Transmission Gate Full Adder
P
VDD
Ci
A
P
A
A
P
B
VDD
Ci
A
P
Ci
VDD
S Sum Generation
Ci
P
B
VDD
A
P
Co Carry Generation
Ci
A
Setup
P
Similar delays for sum and carry
57
IEP on Synthesis of Digital Design 2007
Combinational Circuits
Dynamic Logic
58
IEP on Synthesis of Digital Design 2007
Combinational Circuits
Dynamic CMOS

In static circuits at every point in time (except
when switching) the output is connected to
either GND or VDD via a low resistance path.
 fan-in of n requires 2n (n N-type + n P-type)
devices

Dynamic circuits rely on the temporary
storage of signal values on the capacitance of
high impedance nodes.
 requires on n + 2 (n+1 N-type + 1 P-type)
transistors
59
Combinational Circuits
IEP on Synthesis of Digital Design 2007
Dynamic Gate
Clk
Clk
Mp
off
Mp on
Out
In1
In2
In3
Clk
CL
PDN
1
Out
((AB)+C)
A
C
B
Me
Clk
off
Me on
Two phase operation
Precharge (Clk = 0)
Evaluate (Clk = 1)
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IEP on Synthesis of Digital Design 2007
Combinational Circuits
Conditions on Output
Once the output of a dynamic gate is
discharged, it cannot be charged again until
the next precharge operation.
 Inputs to the gate can make at most one
transition during evaluation.


Output can be in the high impedance state
during and after evaluation (PDN off), state is
stored on CL
61
IEP on Synthesis of Digital Design 2007
Combinational Circuits
Properties of Dynamic Gates

Logic function is implemented by the PDN only
 number of transistors is N + 2 (versus 2N for static complementary
CMOS)
Full swing outputs (VOL = GND and VOH = VDD)
 Non-ratioed - sizing of the devices does not affect
the logic levels
 Faster switching speeds

 reduced load capacitance due to lower input capacitance (Cin)
 reduced load capacitance due to smaller output loading (Cout)
 no Isc, so all the current provided by PDN goes into discharging CL
62
IEP on Synthesis of Digital Design 2007
Combinational Circuits
Properties of Dynamic Gates

Overall power dissipation usually higher than static
CMOS
 no static current path ever exists between VDD and GND
(including Psc)
 no glitching
 higher transition probabilities
 extra load on Clk

PDN starts to work as soon as the input signals
exceed VTn, so VM, VIH and VIL equal to VTn
 low noise margin (NML)

Needs a precharge/evaluate clock
63
Issues in Dynamic Design 1:
Charge Leakage
IEP on Synthesis of Digital Design 2007
Combinational Circuits
CLK
Clk
Mp
Out
CL
A
Clk
Me
Evaluate
VOut
Precharge
Leakage sources
Dominant component is subthreshold current
64
Combinational Circuits
IEP on Synthesis of Digital Design 2007
Solution to Charge Leakage
Keeper
Clk
Mp
A
Mkp
CL
Out
B
Clk
Me
Same approach as level restorer for pass-transistor logic
65
Issues in Dynamic Design 2:
Charge Sharing
IEP on Synthesis of Digital Design 2007
Clk
Mp
Out
A
CL
B=0
Clk
Combinational Circuits
Charge stored originally on CL is
redistributed (shared) over CL
and CA during evaluation,
leading to reduced robustness
CA
Me
CB
66
Combinational Circuits
IEP on Synthesis of Digital Design 2007
Solution to Charge Redistribution
Clk
Mp
Mkp
Clk
Out
A
B
Clk
Me
Precharge internal nodes using a clock-driven transistor
(at the cost of increased area and power)
67
IEP on Synthesis of Digital Design 2007
Issues in Dynamic Design 3:
Backgate Coupling
Clk
Mp
A=0
Out1 =1
CL1
Combinational Circuits
Out2 =0
CL2
In
B=0
Clk
Me
Dynamic NAND
Static NAND
68
Combinational Circuits
Issues in Dynamic Design 4: Clock
Feedthrough
IEP on Synthesis of Digital Design 2007
Clk
Mp
A
CL
B
Clk
Out
Me
Coupling between Out and
Clk input of the precharge
device due to the gate to
drain capacitance. So
voltage of Out can rise
above VDD. The fast rising
(and falling edges) of the
clock couple to Out.
69
IEP on Synthesis of Digital Design 2007
Combinational Circuits
Other Effects
 Capacitive
coupling
 Substrate coupling
 Minority charge injection
 Supply noise (ground bounce)
70
Combinational Circuits
IEP on Synthesis of Digital Design 2007
Cascading Dynamic Gates
V
Clk
Mp
Clk
Mp
Out1
Me
Clk
Out2
In
In
Clk
Clk
Me
Out1
VTn
V
Out2
t
Only 0  1 transitions allowed at inputs!
71
IEP on Synthesis of Digital Design 2007
Combinational Circuits
Domino Logic
72
Combinational Circuits
IEP on Synthesis of Digital Design 2007
Domino Logic
Clk
In1
In2
In3
Clk
Mp
11
10
PDN
Me
Out1
Clk
Mp Mkp
Out2
00
01
In4
In5
Clk
PDN
Me
73
Combinational Circuits
IEP on Synthesis of Digital Design 2007
Why Domino?
Clk
Ini
Inj
Clk
PDN
Ini
Inj
PDN
Ini
Inj
PDN
Ini
Inj
PDN
Like falling dominos!
74
IEP on Synthesis of Digital Design 2007
Combinational Circuits
Properties of Domino Logic
Only non-inverting logic can be implemented
 Very high speed

 static inverter can be skewed, only L-H transition
 Input capacitance reduced – smaller logical effort
75
Combinational Circuits
IEP on Synthesis of Digital Design 2007
Designing with Domino Logic
VDD
VDD
VDD
Clk
Mp
Clk
Mp
Out1
Mr
Out2
In1
In2
In3
PDN
PDN
In4
Can be eliminated!
Clk
Me
Clk
Me
Inputs = 0
during precharge
76
Combinational Circuits
IEP on Synthesis of Digital Design 2007
Footless Domino
VDD
Clk
VDD
Mp
Clk
Mp
Out1
0
0
Clk
Mp
Out2
1
0
In1
1
VDD
Outn
1
0
In2
1
0
In3
1
0
1
Inn
1
0
The first gate in the chain needs a foot switch
Precharge is rippling – short-circuit current
A solution is to delay the clock for each stage
77
Combinational Circuits
IEP on Synthesis of Digital Design 2007
Differential (Dual Rail) Domino
off
Mp Mkp
Clk
Out = AB
1
on
Mkp
0
Clk
Mp
1
A
!A
0
Out = AB
!B
B
Clk
Me
Solves the problem of non-inverting logic
78
Combinational Circuits
IEP on Synthesis of Digital Design 2007
np-CMOS
Clk
In1
In2
In3
Clk
Mp
11
10
PDN
Me
Out1
Clk
Me
In4
In5
PUN
00
01
Clk
Mp
Out2
(to PDN)
Only 0  1 transitions allowed at inputs of PDN
Only 1  0 transitions allowed at inputs of PUN
79
Combinational Circuits
IEP on Synthesis of Digital Design 2007
NORA Logic
Clk
In1
In2
In3
Clk
Mp
11
10
Out1
PDN
Clk
Me
In4
In5
PUN
00
01
Clk
Me
to other
PDN’s
WARNING: Very sensitive to noise!
Mp
Out2
(to PDN)
to other
PUN’s
80