Download M/s CMR Design

King Saud University
Electrical Engineering Department
EE315: Analog and Digital Electronic Circuits
First Mid Term Exam.: Second Semester 1431-1432 H,
Name:
Time allowed:1½ Hrs.
Number:
Question 1: Encircle the most correct answer.
(10 pts.)
1. The voltage between the input terminals of an ideal Op-Amp, when connected with feedback is:
(a) infinite
2.
4.
5.
6
7.
(d) none of them
(b) high gain current
(c) direct coupled
(d) d. c. current
The common mode rejection ratio of an ideal Op Amp should be:
(a) zero
(b) infinite
(c) more than 10
(d) less than 100
In a typical general purpose Op-Amp, the gain is quite ------------ at dc and ------------ frequencies, it
starts to ------------------- at a rather low frequency.
(a) low, high, fall off
(b) low, low, rise
(c) high, low, fall off
(d) high, high, go up
Select he correct statement:
(a) the output impedance of Op-Amp is large.
(b) the input impedance of an inverting Op-Amp is very large.
(c) the input impedance of a non-inverting Op-Amp is very small.
(d) the input impedance of an ideal non-inverting Op-Amp is infinite.
In a BJT current source, the two performance parameters which need improvement are:
(a) dependence of IO on β and output resistance of the current source.
(b) dependence of IO on β and input resistance of the current source.
(c) dependence of IO on VBE and output resistance of the current source.
(d) nonlinear distortion and the bandwidth.
Biasing in IC design is based on the use of ------------------ sources
(a) constant-voltage
8.
(c) milli volts
An Op-Amp is a --------------------- amplifier.
(a) d. c. power
3.
(b) zero
(b) constant-current
(c) linear voltage
(d) logarithmic
In a BJT differential amplifier:
(a) the two collectors should be shorted.
(b) the two emitters should be complementary.
(c) the two bases should be shorted.
(d) the two emitters should be shorted.
9. In a BJT differential amplifier, a difference voltage of about ------------- is sufficient to switch the
current almost entirely to one side of the pair.
(a) 4VT
(b) 100VT
(c) VT/2
(d) 1 V
10. In the basic BJT Differential-Pair, it is ---------------- that the collector circuits be such that Q1 and
Q2 ------------ saturation.
(a) essential; never enter
(b) not necessary; never enter
(c) essential; are always in
(d) required; are always in
Question 2:
(20 pts.)
1. An ideal non-inverting Op-Amp. has a gain of 50. What is
value of the voltage between the two input terminals of the
Op Amp?
(2 pts.)
1
2. Write the expression for CMRR of a BJT differentail amplifier
circuit assuming that the output is taken single- endedly.
(2 pts.)
3. Calculate the output of the circuit shown:
10 KΩ
Vi
15 KΩ
+
VO
–
4. Write the expression for the closed loop gain
of a non-inverting Op-Amp., Assuming the
open loop gain to be finite.
(2 pts.)
5. In a BJT differential amplifier, the two transistors are matched and have
β = 150 and equal collector resistances of 1 KΩ each. What is the
common mode rejection ratio, if the output is taken differentially?
(2 pts.)
6. A BJT differential pair is to be used as a linear small-signal amplifier.
What is the maximum value of the input differential voltage?
(2 pts.)
7. A differential amplifier uses matched
transistors with β =100 and the output is
taken differentially. Calculate the worstcase common mode gain, if the two
collector resistances are accurate to
within ±1%.
(2 pts.)
8. Draw the equivalent circuit model of the
differential half – circuit.
(2 pts.)
9. Draw the circuit diagram for a diode
connected npn transistor.
(2 pts.)
10. Draw the circuit daigram of a simple
BJT current source.
(2 pts.)
Question 3:
(10 pts.)
Assume that the Op-Amp shown in the figure below is ideal.
(a) Determine the values of I1, I2, I3 and I4.
(b) Calculate the voltage VA.
(c) Find the maximum allowable value of RL for VO to remain greater than –12 V.
VA
20 KΩ
I2
+2V
I3
20 KΩ
I1
RL
200Ω
IL
VO
–
I4
+
2
King Saud University
Electrical Engineering Department
EE315: Analog and Digital Electronic Circuits
Second Mid Term Exam.: Second Semester 1431-1432 H,
Name:
Time allowed:1½ Hrs.
Number:
Question 1: Encircle the most correct answer.
1.
In MOSFET differential amplifier, the value of input differential voltage (vid) at which full swing occurs is:
(a) √2 (𝑉𝑮𝑺 − 𝑉𝒕 )
2.
(10 pts.)
(b) √2 (𝑉𝑮𝑺 + 𝑉𝒕 )
(c) √2(𝑉𝑮𝑺 − 𝑉𝒕 )
In a basic MOSFET current mirror, the output transistor should be:
(a) in cut off condition.
(c) in active region
3.
(d) None of them
(b) in triode region.
(d) in saturation region
An NMOSFET is in saturation region, if :
(a) vDS < vGS – Vt
(c) vGS < vDS – Vt
(b) vDS > vGS – Vt
(d) vGS > vDS – Vt
4.
Two types of load devices are used in NMOS. One of them is ---------------- MOSFET with the drain
connected to the gate, and the other is -------------- MOSFET with the gate connected to the source.
(a) depletion, enhancement
(b) enhancement, depletion
(c) enhancement, enhancement
(d) depletion, depletion
5.
In an inverter with enhancement mode load, the load transistor -------------- operates in -------------.
(a) never; saturation
(b) all the time; saturation
(c) all the time; triode region
(d) sometimes ; saturation
6.
The inverting Op Amp configuration is an example of -------------------- feedback.
7.
(a) shunt - shunt
(b) shunt - series
(c) series - shunt
The output impedance of a feedback amplifier depends upon:
(a) the method of sampling only.
(c) the method of mixing only.
(d) series - series
(b) the method of sampling as well as of mixing.
(d) none of them
8.
In a practical series-shunt feedback amplifier, the feedback network ------------------ an ideal voltagecontrolled -------------------- source.
(a) will not be, voltage
(b) will be, current
(c) will be, voltage
(d) has to be, current
9.
The negative feedback in amplifiers:
(a) reduces nonlinear distortion.
(c) increases the effect of noise.
(b) increases nonlinear distortion.
(d) reduces the bandwidth.
10. An amplifier without feedback has a gain of 2000 and bandwidth of 5 KHz. A negative feedback
with β = 0.01 is applied. The Gain – Bandwidth product with feedback is:
(a) 1000 KHz
(b) 500 Hz
(c) 2 MHz
3
(d) None of them
Question 2:
(14 pts.)
1.
Draw the circuit diagram of a noninverting amplifier.
(2pts.)
2.
In an NMOS amplifier with enhancement load, the two transistors are perfectly matched and are of same size.
Calculate the large signal voltage gain.
(2pts.)
3.
An amplifier has a bandwidth of 2 KHz. A feedback is applied to reduce the gain by a factor of 80. Calculate
the bandwidth.
(2pt.)
4.
The figure shows a differential amplifier with
active load. One connection is missing. Draw the
missing connection in the figure.
(2pts.)
5.
(2
R2
Under what conditions, the circuit shown acts as a
difference amplifier? Write the expression for output
of this circuit.
(2pts.)
R1
v1
–
vo
R3
v2
+
R4
6.
Calculate the output of the circuit shown.
(2pts.)
v1
R1
–
R3
vo
+
7.
For the circuit shown, write the name of the feed back
configuration. Also indicate whether it is a voltage
amplifier, current amplifier, trans-resistance amplifier
or trans-conductance amplifier?
(2pts.)
Question 3:
(16 pts.)
For the circuit shown, assume that the Op-Amp has infinite input resistance and zero output resistance.
1. Determine expression for feedback factor
4
2. If the gain of the Op-Amp (A) is 105, find R2/R1 to obtain a feedback gain Af = 500.
3. If Vs = 2 mV, calculate Vf.
4. If A decreases by 25%, what is the corresponding decrease in Af ?
Rs
+
Vs
A
+
–
–
RL
R2
R1
5
King Saud University
College of Engineering
Electrical Engineering Department
EE 315: Analog and Digital Electronic Circuits
Final Exam: Closed book and notes
Time: 3 Hrs
Second Semester 1431-32
Monday 11/7/1432 (13/6/11)
Note: Do the work neatly and show all your work clearly (except for Question 1).
Question 1: Encircle the most correct answer.
1.
(1 X 20 = 20 Pts.)
For successful operation of BJT differential amplifier, it is ------------- that Q1 and Q2 never enter -------------.
(a) not necessary; triode region.
(c) essential; active region
2.
3.
4.
5.
6.
7.
8.
(b) not necessary; saturation
(d) essential; saturation
In BJT differential amplifiers, the ------------- are usually used in place of the load resistances.
(a) capacitors
(b) diodes
(c) current sources
(d) voltage sources
One of the ------------- of negative feedback in an amplifier is that the gain is -----------------.
(a) advantages; desensitized
(b) disadvantages; desensitized
(c) advantages; doubled
(d) advantages; increased
Negative feedback is applied to a trans-conductance amplifier. The input impedance will:
(a) become zero
(b) increase
(c) decrease
(d) remain constant
An ideal Op Amp has -------------- input impedance and ------------- output impedance.
(a) infinite; infinite
(b) zero; zero
(c) zero; infinite
(d) infinite; zero
A weighted ------------- may be made by using ------------- and an Op Amp.
(a) summer; resistors
(b) summer; capacitors
(c) integrator; resistors
(d) summer; inductors
In an ideal BJT differential amplifier, the common mode rejection ratio (CMRR) is infinite if the output is:
(a) taken single endedly. (b) shorted.
(c) taken differentially.
(d) open circuited.
Which of the following conditions should be satisfied to minimize the effect of open loop gain over the
closed loop gain in an inverting Op Amp.?
(a) (1 + R2/R1) >> A
(b) (1 + R2/R1) << A
(c) (1 + R2/R1) << 1/A
(d) (1 + R2/R1) = A
9.
In BJT current mirror, one of the sources of error is the linear dependence of the ------------ on the collector
voltage of Q2.
(a) output current
(b) output voltage
(c) input current
(d) voltage gain
10. The availability of both n- and p-channel transistors in CMOS technology makes it more convenient to
design MOS steering circuits in -------------- than in a pure ------------ technology.
(a) hybrid; CMOS
(b) PMOS; CMOS
(c) CMOS; NMOS
(d) NMOS; CMOS
11. BiCMOS allows for the implementation of both ------------ and ------------ circuits on the same chip.
(a) inductor; capacitor
(b) linear; hybrid
(c) saturated; unsaturated
(d) analog; digital
12. The robustness of a logic family is determined by its ability to ------------- noise, and thus by the --------------.
(a) inject; noise margins
(c) reject; noise margins
(b) inject; current level
(d) reject; integration level
13. The Pseudo-NMOS pull down network (PDN) is identical to the ------------- of the ---------- logic gate.
(a) PDN; TTL
(b) PDN; ECL
(c) PUN; CMOS
(d) PDN; CMOS
14. In a Pseudo-NMOS logic gate, r determines all the breakpoints of the VTC; the ---------------- the value of r,
the ------------ VOL is and the ---------- the noise margins are.
(a) smaller; lower; wider
(b) larger; lower; wider
(c) larger; larger; wider
(d) larger; lower; smaller
15. One of the main disadvantages of CMOS is that it has increased -------------- when the fan-in and fan-out
are ------------, affecting both ------------- and propagation delay.
(a) circuit complexity; increased; chip area
(b) power dissipation; increased; chip area
(c) noise margins; increased; chip area
(d) circuit complexity; increased; static power
6
16. The closed loop gain of an inverting Op-Amp rolls off at a uniform slope of ------------ with a corner
frequency given by -------------------.
(a) – 10dB/decade;
𝜔𝑡
(b) – 20dB/decade;
1+𝑅2 /𝑅1
𝜔𝑡
1+𝑅2 /𝑅1
(c) – 10dB/decade; 𝜔𝑡 (1+R2 /R1)
(d) – 20dB/decade; 𝜔𝑡 (1+R2 /R1)
17. For the BJT differential amplifier with resistances in the emitter leads, the differential gain, when the output
is taken differentially is approximately equal to:
(d) none of them
(a) – RC/(re+RE)
(b) – RE /(re+RC)
(c) – RC //(re+RE)
18. In actual TTL circuits, the input transistor, Q1 is designed to have a very ------------- β.
(a) high reverse
(b) low forward
(c) low reverse
(d) low transfer
19. Select the most correct statement.
(a) One of the approaches to speed up the operation of TTL is to ensure transistor saturation.
(b) In Schottky TTL circuits, the transistors are not allowed to go into saturation.
(c) A TTL gate has a passive pull up.
(d) The input transistor in a TTL gate operates in inverse active mode when input is low.
20. Select the wrong statement (s).
(a) A Pseudo-NMOS AND gate contains only one pull up transistor.
(b) The Pull down transistor of a TTL is always ON.
(c) A CMOS gate contains even number of transistors.
(d) The ECL 100K series provides the shortest available gate delay.
Question 2:
(2 X 15 =30 Pts.)
1. Draw the circuit diagram of a Miller integrator.
2. An ideal op-Amp. is used as an inverting amplifier. The two resistances used are 2KΩ and 20 KΩ. Determine
the gain and input resistance of the circuit.
3. A BJT differential amplifier uses collector resistances of 10 K each. The two emitters are directly connected
to a current source of 2 mA. Calculate the input differential resistance of the amplifier if the transistors have β
=200.
4. A typical BJT multi-stage differential amplifier consists of four basic stages. Write the purpose of the third
stage.
5. A basic current mirror uses a matched pair of BJTs having β =50. Calculate the value of output current if the
reference current is 15 mA.
6. Draw the circuit diagram of a basic MOSFET
current mirror.
7. Draw the circuit diagram and i-v characteristics
of a diode connected depletion mode MOSFET.
(Circuit Diagram)
(i-v characteristics)
8. Write the expression for the input differential voltage of a MOS differential amplifier at which full swing
occurs.
7
9. In a matched CMOS inverter, (W/L)n = 1.8 and μn/μp = 2.5. Calculate the area factor.
10. Write the name of the type of feedback used in transconductance amplifier.
11. Draw the circuit diagram of a practical series-shunt amplifier with the feedback network represented by its hparameters and neglecting h21.
12. For the pull up circuit shown in the figure, draw the
pull down circuit and indicate the transistor ratios to
guarantee a worst-case gate delay equal to that of
the basic inverter.
A
C
E
B
D
13. Draw the circuit diagram of the
conceptual form of the TTL logic
gate.
14. For the circuit given in figure, calculate I2 and I3 ,
assuming (W/L)1 = 2, (W/L)2 = 3 and (W/L)3 = 4.
5V
1 mA
I2
I3
Q2
Q1
Q3
15. Draw the circuit diagram for the PseudoNMOS circuit to realize the following
function:
𝑌 = 𝑃(𝑄 + 𝑅) + 𝐾. 𝐸
Question 3:
(6Pts.= 1+0.5+0.5+0.5+0.5+0.5+0.5+0.5+0.5+0.5+0.5)
For the circuit shown in the figure assume that he Op. Amp. is ideal,
v1 = 2V and v2 = 0.5V.
(i) Determine the value of R so that the circuit acts as a difference
amplifier.
(ii) Calculate the value of the input impedance of the circuit.
(iii) Calculate Vx, Vy and vO.
(iv) Calculate output current of the Op. Amp., the load current and
currents through all the resistors. Show the direction of each
current in the figure.
8
20 K
v1
v2
5 K
Vx
R
Vy
40 K
–
+
vO
RL =2 K
Question 4:
(6Pts.= 2+1+1+1+0.5+0.5)
An ideal series-series feedback amplifier operates with the following:
Input voltage = 76 mV; Output current = 8 mA; Feedback voltage = 72 mV; Input and output resistances
with feedback = 190 KΩ and 114 KΩ respectively.
Draw the block diagram of the circuit and calculate the values of gain with and without feedback, the
feedback factor and the input and output resistances of the basic amplifier (without feedback). Clearly
indicate the units in each case.
Question 5:
(6 Pts.)
An MOS differential pair uses transistors with a W/L ratio of 125 and operates at a total bias current of 1 mA. It
has kn/ =0.2 mA/V2, VA = 20 V and RD = 5 KΩ. Calculate VOV, gm, ro and Ad.
(2+1+1+2)
Question 6:
(6 Pts.)
Vcc = +12 V
The transistors used in the circuit shown in the figure
have β = 120 and VA = 50 V.
(b) Calculate Ad, Acm and CMRR.
Q3
Q4
(a) Calculate the dc values of IC1, IC2 and VE. (1+1+1)
(1+1+1)
VO
IC1
IC2
v2
Q1
Q2
v1
VE
Q5
Q6
R = 6.3 K
-VEE = - 12 V
Question 7:
(6 Pts.)
(A) A CMOS inverter is fabricated with 1.2 µm technology with equal channel lengths of 1.2 µm for all
the transistors. The inverter has VDD = 5 V, Vtn = |Vtp| = 1 V, µnCox =100 µA/V2, µn/µp = 2.8,
(W/L)n =1.5 and the load is C = 0.2 pF.
(i) Determine the value of Wp to make Qn and Qp matched.
(1)
(ii) Draw the CMOS inverter and its voltage transfer characteristics. Label the various regions and
the state of the transistors in each region.
(3)
(iii) Calculate the propagation delay
(1)
(iv) Calculate the power dissipation if the inverter is switched at 5 MHz.
(1)
OR
9
(B) A BJT gate is shown in the figure below. The transistors have βF = 100 and βR = 0.02. The forward
bias junction voltages are 0.65 V and VCE(sat) = 0.2 V. An input of 3.7 V is connected to the gate.
(i) Indicate the status of all transistors and the diode.
(1)
(ii) Determine the output voltage.
(2)
(iii) Determine the currents through all the resistors.
(2)
(iv) Calculate the power dissipated by the gate.
(1)
+5 V
50 Ω
900 Ω
2 KΩ
Q4
D
Q1
Q2
Out
In
Q3
500 Ω
10