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Trap densities in amorphous- In Ga Zn O 4 thin-film transistors Mutsumi Kimura, Takashi Nakanishi, Kenji Nomura, Toshio Kamiya, and Hideo Hosono Citation: Applied Physics Letters 92, 133512 (2008); doi: 10.1063/1.2904704 View online: http://dx.doi.org/10.1063/1.2904704 View Table of Contents: http://scitation.aip.org/content/aip/journal/apl/92/13?ver=pdfcov Published by the AIP Publishing This article is copyrighted as indicated in the article. Reuse of AIP content is subject to the terms at: http://scitation.aip.org/termsconditions. Downloaded to IP: 140.120.12.186 On: Mon, 23 Dec 2013 06:50:15 APPLIED PHYSICS LETTERS 92, 133512 共2008兲 Trap densities in amorphous-InGaZnO4 thin-film transistors Mutsumi Kimura,1,a兲 Takashi Nakanishi,1 Kenji Nomura,2 Toshio Kamiya,2 and Hideo Hosono2 1 Department of Electronics and Informatics, Ryukoku University, Seta, Otsu 520-2194, Japan Materials and Structures Laboratory, Tokyo Institute of Technology, Nagatsuta, Midori, Yokohama 226-8503, Japan 2 共Received 30 December 2007; accepted 12 March 2008; published online 3 April 2008兲 Trap densities in amorphous-InGaZnO4 共␣-IGZO兲 are extracted directly from the capacitance-voltage characteristics of thin-film transistors at low frequencies. It is found that the trap densities are flat in the energy gap, and are 1.7⫻ 1016 cm−3 eV−1 in the deep energy far from the conduction band edge 共Ec兲, but become larger near Ec. Moreover, postannealing reduces the trap density near Ec, which is associated with the reduction of the hysteresis in the current-voltage characteristics. The annealed ␣-IGZO does not have a Gaussian-type state and has fewer tail states than amorphous Si. © 2008 American Institute of Physics. 关DOI: 10.1063/1.2904704兴 Oxide conductors and semiconductors are promising as transparent electronic components in various applications such as flat-panel displays, optical sensors, and solar cells.1–4 In particular, because amorphous-InGaZnO4 共␣-IGZO兲 thinfilm transistors 共TFTs兲 exhibit high performances even when fabricated on plastic substrates at low temperatures, they have been extensively studied.5–11 However, the electrical properties of ␣-IGZO, which are important for designing device structures and circuit configurations, are not thoroughly understood. Although the fundamental carrier-transport properties and electronic structures of ␣-IGZO have been studied using Hall measurements5,12,13 and ab initio calculations,14,15 the trap densities in ␣-IGZO, which determine the transistor characteristics especially when fabricated on large substrates at low temperatures, are not yet reported. Several methods have been developed to experimentally detect the trap densities, including electron paramagnetic resonance, deep-level transient spectroscopy, isothermal capacitance transient spectroscopy,16 constant photocurrent methods,17 device simulation fitting,18 field-effect 共FE兲 methods,19,20 and capacitance-voltage 共C-V兲 methods.21,22 However, these methods often give different results because each method has a different detectability for different types of trap states. Moreover, because some of these methods require varying the measurement temperature over a wide range, it is difficult to evaluate temperature-sensitive materials. Furthermore, because device simulation fitting and FE methods require a mobility model in order to fit the currentvoltage 共I–V兲 characteristics, the results depend on the mobility model. On the other hand, C-V methods do not have these drawbacks because they do not require varying the measurement temperature and the mobility model. Therefore, C-V methods are useful for ␣-IGZO because it is known that the transistor characteristics are changed by thermal annealing and that the carrier mobility depends on the carrier density.5,12 In the case of the usual metal-oxide-semiconductor FE transistors 共MOSFETs兲, actual devices have a vertical “metal/insulator/semiconductor” 共MIS兲 structure. Because the semiconductor is connected to the bulk terminal at a a兲 Electronic mail: [email protected]. certain fixed voltage, the boundary condition at the back side is the fixed potential. Because the charging current is quickly supplied from the bulk terminal, the frequency dependence is consequently determined by the trap and detrap rates of the trap states. Accordingly, some conventional C-V methods for the usual MOSFETs can extract the trap densities by evaluating the frequency dependence.21,22 The other C-V methods are also based on these structure and boundary condition and formularized. In the case of TFTs, actual devices have a “metal/insulator/semiconductor/insulator” structure. It is preferable to extract the trap densities from the actual structure because the fabrication and existence of the bulk terminal may influence electrical properties of the semiconductor. Because the semiconductor is connected to the source and drain regions far from the center of the semiconductor, the boundary condition is the floating potential. Because the charging current is slowly supplied through the source and drain regions, the frequency dependence is mainly influenced by the supplying speed of the charging current. Accordingly, the conventional C-V methods cannot extract the trap densities. Therefore, we have developed a novel method to extract the trap densities directly from the C-V characteristics of TFTs at low frequencies.23–25 This method numerically calculates the Poisson equation and the charge density and extract the trap densities by fitting the measured and calculated C-V characteristics. The applied frequency must be extremely low in order to maintain the equilibrium condition due to the above explanation. An outstanding advantage of this method is that the trap densities extracted from the C-V characteristics can be directly related to the I-V characteristics of the TFTs. Figure 1 shows the cross-sectional structure of an ␣-IGZO TFT. A heavily doped n+-Si substrate was used as the gate terminal. An SiO2 film, which was used as the gate insulator, was grown by thermal oxidation. After the necessary areas were patterned by photolithography, an ␣-IGZO FIG. 1. Cross-sectional structure of an ␣-IGZO TFT. This article is copyrighted as indicated in the article. Reuse of AIP content is subject to the terms at: http://scitation.aip.org/termsconditions. Downloaded to IP: 0003-6951/2008/92共13兲/133512/3/$23.00 92, 133512-1 © 2008 American Institute of Physics 140.120.12.186 On: Mon, 23 Dec 2013 06:50:15 133512-2 Appl. Phys. Lett. 92, 133512 共2008兲 Kimura et al. FIG. 2. Measurement system for the C-V characteristics. film, which was used as the channel layer, was deposited by pulsed laser deposition 共PLD兲 at room temperature in oxygen gas at 6.2 Pa and was patterned by a lift-off technique. Select samples were annealed at 300 ° C in air for 1 h 共postannealing兲. It was confirmed that the annealed ␣-IGZO remained amorphous.13 After the necessary areas were patterned by photolithography, indium tin oxide and Au films, which were used as the source and drain terminals, were sequentially deposited by PLD, and were patterned by a lift-off technique. The channel width 共W兲 and length 共L兲 were 300 and 50 m, respectively. It was confirmed that the electron concentration in ␣-IGZO without an applied voltage was about 1016 cm−3 using Hall measurements.13 Figure 2 shows the measurement system for the C-V characteristics.24 A small ac voltage generated by a lock-in amplifier was superimposed on the dc offset voltage 共Vgs兲 generated by a voltage source, and it was applied to the gate terminal of the TFT on a probe station in a shield box. The charging and discharging currents through the source and drain terminals were amplified by a current amplifier. The signal amplitude and the phase shift were measured by the lock-in amplifier, and the capacitance 关Cg共s+d兲兴 and conductance components were separated. Figure 3 shows the measured results of the C-V and I-V characteristics of the unannealed and annealed TFTs. Here, the C-V characteristics at applied frequencies of 0.1 and 0.5 Hz are plotted. Because these C-V characteristics completely overlap, it is guaranteed that the applied frequencies are sufficiently low in order to maintain the equilibrium condition. It is observed that Cg共s+d兲 becomes small at a negative Vgs because the electrons are depleted in the ␣-IGZO film. Cg共s+d兲 becomes larger as Vgs increases because the electrons are accumulated at the surface of the ␣-IGZO film. Cg共s+d兲 is saturated at the geometrical capacitance of the gate insulator at a positive Vg共s+d兲 because a parallel-plate capacitor is formed across the gate insulator. The energy profile of the trap density is extracted from the transition curve from the depletion region to the accumulation region. Moreover, the FIG. 4. Calculated results of the potential profiles of the annealed ␣-IGZO TFT. I-V characteristics for the forward and reverse scans are also plotted. The swing parameter 共S兲 is 0.26 V decade−1, the field effect mobility 共兲 is 9.0 cm2 V−1 s−1, and the hysteresis is large for the unannealed TFT. On the other hand, S is 0.15 V decade−1, is 12.3 cm2 V−1 s−1, and the hysteresis disappears for the annealed TFT, which imply that postannealing dramatically improves transistor performances. The trap densities were extracted using the following algorithm. First, the surface potential 共s兲 is calculated from the C-V characteristic. By applying Q = CV to the gate insulator, differentiating it by Vgs, and transforming it, Eqs. 共1兲 and 共2兲 are acquired. Moreover, by integrating Eq. 共2兲 by Vgs, Eq. 共3兲 is acquired. Here, Ci is the geometrical capacitance of the gate insulator, Cg共s+d兲 is the measured capacitance in the C-V characteristic, and Vfb is the flatband voltage, which corresponds to Vgs where Cg共s+d兲 begins to increase, Q = Ci共Vgs − s兲, s Q =1− Vgs Vgs s = 冕 Vgs 冒 共1兲 Ci = 1 − Cg共s+d兲/Ci , 共1 − Cg共s+d兲/Ci兲dVgs . 共2兲 共3兲 Vfb By substituting Cg共s+d兲 into Eq. 共3兲, s is calculated as a function of Vgs. Figure 4 shows the calculated results of the surface potentials of the annealed TFT. It is found that s is saturated for high Vgs − Vfb, which indicates that the electrons are accumulated at the surface of the ␣-IGZO film and that the conduction band edge approaches the Fermi level. Furthermore, by applying Gauss’s law to the surface of the channel layer, Eq. 共4兲 is acquired. Here, 共 / x兲s is the surface potential gradient in the channel layer, i is the dielectric constant of the gate insulator, s is that of the channel layer, and ti is the thickness of the gate insulator, 冉 冊 x = 共i/s兲共Vgs − s兲/ti . 共4兲 s By substituting s into Eq. 共4兲, 共 / x兲s is also calculated as a function of Vgs. Next, so that s and 共 / x兲s calculated from Eqs. 共3兲 and 共4兲 are consistent, the potential profile in the channel FIG. 3. Measured results of the C-V and I-V characteristics of the 共a兲 unanThis article is copyrighted as indicated in the article. Reuse of AIP content is subject to the terms at: http://scitation.aip.org/termsconditions. Downloaded to IP: layer 共兲 is calculated for each Vgs. By applying the Poisson nealed and 共b兲 annealed ␣-IGZO TFTs. 140.120.12.186 On: Mon, 23 Dec 2013 06:50:15 133512-3 Appl. Phys. Lett. 92, 133512 共2008兲 Kimura et al. trap density near Ec. The annealed ␣-IGZO does not have a Gaussian-type state, which is often observed in the ␣-Si TFTs, and has fewer tail states than ␣-Si. The hysteresis is large in the I-V characteristic for the unannealed TFT, while the hysteresis disappears for the annealed TFT, as shown in Fig. 3. This change can be qualitatively explained using the change in the trap densities of the unannealed and annealed TFTs. However, it cannot be quantitatively explained. The voltage shift of the hysterisis is as large as 4 V, but the voltage shift estimated from the change in the trap densities is as small as 1 V. Moreover, such shallow states at 0.1– 0.3 eV from Ec are usually fast states and do not cause a hysteresis in these slow measurements. Therefore, it is suggested that other reasons cause the hysteresis. FIG. 5. Extracted results of the trap densities of the unannealed and annealed ␣-IGZO TFTs and ␣-Si TFT 共Ref. 26兲. equation to the channel layer and supposing that the charge density in the channel layer 共兲 is caused by the density of states, Eqs. 共5兲 and 共6兲 are acquired. Here, x is the axis along the depth, and N is the density of state, 2 = − /S , x2 The authors would like to thank Dr. Simon W.-B Tam of Cambridge Research Laboratory of Epson. This research is partially supported by a Grant for Industrial Technology Research from the New Energy and Industrial Technology Development Organization 共NEDO兲, and a Research Project of the Joint Research Center for Science and Technology at Ryukoku University. 1 M. W. J. Prins, K.-O. Grosse-Holz, G. Müller, J. F. M. Cillessen, J. B. Giesbers, R. P. Weening, and R. M. Wolf, Appl. Phys. Lett. 68, 3650 共1996兲. 2 H. Kawazoe, M. Yasukawa, H. Hyodo, M. Kurita, H. Yanagi, and H. Hosono, Nature 共London兲 389, 939 共1997兲. 3 K. Nomura, H. Ohta, K. Ueda, T. Kamiya, M. Hirano, and H. Hosono, Science 300, 1269 共2003兲. =−q Nd . 共6兲 4 R. L. Hoffman, B. J. Norris, and J. F. Wager, Appl. Phys. Lett. 82, 733 0 共2003兲. 5 By dividing the channel layer into the multimeshed layers, K. Nomura, H. Ohta, A. Takagi, T. Kamiya, M. Hirano, and H. Hosono, Nature 共London兲 432, 488 共2004兲. assuming the back surface potential 共b兲 and N, correlating 6 H. Q. Chiang, J. F. Wager, R. L. Hoffman, J. Jeong, and D. A. Keszler, boundary conditions between each adjacent meshed layers, Appl. Phys. Lett. 86, 013503 共2005兲. 7 approximating that is constant in each meshed layer, and B. Yaglioglu, H. Y. Yeom, R. Beresford, and D. C. Paine, Appl. Phys. Lett. numerically integrating Eq. 共5兲 through all the meshed lay89, 062103 共2006兲. 8 D. Kang, H. Lim, C. Kim, I. Song, J. Park, Y. Park, and J. G. Chung, Appl. ers, is calculated for the entire channel layer. Moreover, by Phys. Lett. 90, 192101 共2007兲. fitting s and 共 / x兲s calculated from Eqs. 共5兲 and 共6兲 to 9 G. Goncalves, P. Barquinha, L. Raniero, R. Martins, and E. Fortunato, those calculated from Eqs. 共3兲 and 共4兲, b and N are optiThin Solid Films 516, 1374 共2008兲. 10 mized for each Vgs. Figure 4 also shows the calculated results P. Gorrn, M. Sander, J. Meyer, M. Kroer, E. Becker, H.-H. Johannes, W. of the potential profiles of the annealed TFT. It should be Kowalsky, and T. Riedl, Adv. Mater. 共Weinheim, Ger.兲 18, 738 共2006兲. 11 M. Ito, M. Kon, C. Miyazaki, N. Ikeda, M. Ishizaki, Y. Ugajin, and N. noted that a voltage less than 50% of Vgs − Vfb is applied to Sekine, IEICE Trans. Electron. E90-C, 2105 共2007兲. the channel layer and the gate insulator when Vgs − Vfb is less 12 A. Takagi, K. Nomura, H. Ohta, H. Yanagi, T. Kamiya, M. Hirano, and H. than 2 V because the back surface is electrically floating, Hosono, Thin Solid Films 486, 38 共2005兲. 13 which drastically differs from the conventional theory of K. Nomura, A. Takagi, T. Kamiya, H. Ohta, M. Hirano, and H. Hosono, Jpn. J. Appl. Phys., Part 1 45, 4303 共2006兲. MIS capacitance. It should also be noted that an increase of 14 J. Robertson, K. Xionga, and S. J. Clark, Thin Solid Films 496, 1 共2006兲. s less than 0.1 V, which corresponds to band bending in the 15 K. Nomura, T. Kamiya, H. Ohta, T. Uruga, M. Hirano, and H. Hosono, channel layer, induces an increase in the drain current 共Ids兲 Phys. Rev. B 75, 035212 共2007兲. 16 more than five orders of magnitude when Vgs − Vfb increases D. K. Schroder, Semiconductor Material and Device Characterization, 3rd to more than 2 V, as observed in Fig. 3. ed. 共Wiley, New Jersey, 2006兲. 17 J. Kocka, M. Vanecek, and A. Triska, Amorphous Silicon and Related Finally, the energy profile of N is extracted. Although N Materials, edited by H. Fritzshe 共World Scientific, Singapore, 1988兲, p. theoretically includes not only the trap density but also the 297. conductive-state density, N realistically corresponds to the 18 T.-K. A. Chou and J. Kanicki, Jpn. J. Appl. Phys., Part 1 38, 2251 共1999兲. 19 trap density because s is within the energy gap. Figure 5 M. Shur and M. Hack, J. Appl. Phys. 55, 3831 共1984兲. 20 shows the extracted results of the trap densities of the unanM. J. Powell, IEEE Trans. Electron Devices 36, 2753 共1989兲. 21 L. M. Terman, Solid-State Electron. 12, 689 共1969兲. nealed and annealed TFTs. The trap density of an 22 26 S. M. Sze, Physics of semiconductor Devices, 2nd ed. 共Wiley, New York, amorphous-Si 共␣-Si兲 TFT is also shown in Fig. 5. Here, the 1981兲. 23 origin of the horizontal axis corresponds to s for the flatM. Kimura, R. Nozawa, S. Inoue, T. Shimoda, B. O.-K. Lui, S. W.-B. band condition. The conduction band edge 共Ec兲 of the Tam, and P. Migliorato, Jpn. J. Appl. Phys., Part 1 40, 5227 共2001兲. 24 M. Kimura, S. W.-B. Tam, S. Inoue, and T. Shimoda, Jpn. J. Appl. Phys., ␣-IGZO TFTs is about 1.5 eV, while that of the ␣-Si TFT Part 1 43, 71 共2004兲. is about 0.7 eV. It is found that the trap densities of the 25 S. W.-B. Tam, P. Migliorato, O. K. B. Lui, and M. J. Quinn, IEEE Trans. ␣-IGZO TFTs are flat in the energy gap, and are 1.7 Electron Devices 46, 134 共1999兲. 16 −3 −1 26 ⫻ 10 cm eV in the deep energy far from Ec, but beR. A. Street, Technology and Applications of Amorphous Silicon 共Springer, This article is copyrighted as indicated in the article. Reuse of AIP content is subject to the terms at: http://scitation.aip.org/termsconditions. Downloaded to IP: come larger near Ec. Moreover, postannealing reduces the Berlin, 2000兲. 140.120.12.186 On: Mon, 23 Dec 2013 06:50:15 冕 共5兲