Download Matching High-Speed Amplifiers and Data Converters

So Many Amplifiers To Choose From;
Matching Amplifiers To Applications
•Transfer Functions and Loop Gain
–Voltage Feedback, Current Feedback, FDA’s
•Loop Gain and other contributors to linearity
•Differential circuits and why.
•MFB Filter Design
–Transfer function with an ideal op amp
–Design choices and recommendations
–Loop gain analysis and implications
–Example Designs
Michael Steffes
Market Development Manager
High Speed Signal Conditioning
1
Loop Gain is Everything in Op Amps
• Op Amp suppliers are essentially selling a device that does impedance
transformation (high input Z to low output Z) and a whole lot of open loop
gain.
• The customer then closes the loop to get a more controlled voltage gain,
but also gets a huge improvement in precision (both DC and AC) due to
the high open loop gain.
• For high frequency parts, the DC open loop gain is a secondary issue and
it is really the one pole rolloff curve that is of interest and where the
magnitude of the open loop gain equals the inverse of the feedback ratio.
(Loop Gain x-over).
2
Simplified VFB Analysis
R2
Vo
R1

R
Vi
1 2
R1
1
As 

Z+
V1
R2
+
Zo
A(s)
R1
Vo
Vi
V2
Z-
-
VFB
Assumption s :
Z  
Vo
+
Z  
Zo  0
Vo  As V1  V2 
3
Simplified VFB Loop Gain Analysis
Loop Gain
Log Gains
20 Log (A(S))
 R
20 log1  f
 Rg




Loop Gain x-over
Loop
Bandwidth
Log(f)
0°
LG
Phase
Margin
-180°
4
Simplified CFB Analysis
Z+
R1
+
R2
Vi
V1
x1 Z(s)
Vo
V2
ZV2
CFB
Assumptions:
ierr
R2
Vo
R1

R
Vi
1 2
Z s

Zo
Z  
Z  0
Zo  0
Vo  Z sierr
V1
Vo
+
ierr is the error current
5
Simplified CFB Loop Gain Analysis
Loop Gain
Log Impedances
20 Log (ZS)
Loop Gain x-over
20logR f 
Loop
Bandwidth
Log(f)
0°
LG
Phase
Margin
-180°
6
Simplified FDA Analysis
R2
R1
Vn
VIN-
-
VOUT+
+
a(f)
Vp
-
R3
VIN+
VOUT-
+
VOCM
With the feedback ratios
matched, this reduces to the
same equation as an
inverting VFB amplifier. Will
have the same Loop gain
Bode Plots.
R4
VOUT   VOUT   1  a f   1  
VIN    VIN   1 a f    1


With 
Rg
R1
R3


R1  R2 R3  R4 Rg  R f
VOUT   VOUT   Rf
VIN   VIN  R
g

1
  Rf  
 1   
  Rg  
1 

As  





1
1 

a f  
Considerable complexity in
the analysis will result with
imbalanced feedback ratios.
Refer to TI app. Note
SLOA054 for details.
For this discussion, the FDA
will be a subset of the VFB
class of devices.
7
Comparing Voltage and Current
Feedback Op Amps
• Two parts on the same process, at the same quiescent power,
will have pretty similar open loop gain curves for VFB and
CFB devices – Compare the OPA690 (VFB) and the
OPA691(CFB) below.
OPA690 Voltage Feedback (VFB)
Dominant Pole at 80kHz
OPA691 Current Feedback (CFB)
Dominant Pole at 200kHz
Gain of 2 (6dB) Loop Gain at 20Mhz is 14dB
Gain of 2, Rf = 402ohms, Loop gain at 20Mhz is 16dB
The loop gain profile is just slightly higher over frequency for the CFB version due to the higher dominant pole location
8
Theoretical Determinants of Harmonic Distortion
• An Ideal amplifier would take an input spectrum and pass it on to the
output with the same gain for each Fourier component and no added
power in the spectrum.
– We have not quite achieved that ideal, hence new amplifiers and
techniques moving closer to this are still being introduced.
• Output spectral purity has many levels of consideration – the better
you aspire to, the more of these levels you will have to consider.
• The first level is that, for a high open loop gain type of part, the output
linearity will be the linearity intrinsic to the output stage corrected by
the loop gain at the fundamental frequency.
– Low loop gain devices, like most RF amplifiers, achieve high
linearity by making the signal power a very small part of the
quiescent power. Hence you will see >80dBc SFDR type devices
9
to very high frequencies using > 1.5W quiescent power
Distortion Analysis using Negative Feedback
with Distortion modeled only as an Output Stage Distortion
Vo  A  Verr  Vd
Verr  Vi  f  Vo
Differencing
Stage
Vi
Vo  A  Vi  A  f  Vo  Vd
1 A  f Vo  A  Vi  Vd
Vd
Vi
Vo  A

1  A  f  1  A  f 
Distortion
Signal
+
Verr
-
+ Vd
A
Forward Gain
Vo
+
f
Feedback
Ratio
where Af ≡ Loop Gain. Output stage non-linearities are corrected by loop gain.
10
Paths to Improved Distortion Suggested by
the Control Theory Model.
• At a first level, output linearity is the open loop distortion of the output stage,
corrected by the loop gain. So, improving either of these will improve
distortion.
• One key conclusion from the Loop Gain comparison between VFB and CFB
is that the CFB holds a more constant loop gain over signal gain (Gain
Bandwidth Independence). This should hold more constant distortion to
higher gains than VFB.Comparing those plots for the VFB OPA690
and CFB OPA691 -
OPA690, VFB, HD linear with log gain
OPA691,CFB, HD more constant over gain
11
Continued Improvement in SFDR??
•
The 2nd Harmonic typically does not follow this theory exactly. There are other, external,
effects that typically come into play on the even order terms for a single ended amplifier.
•
Even order distortion can be visualized as ½ cycle imbalance on a sine wave. Odd order
distortion can be visualized as curvature through zero on a sine wave.
•
Anything that will take a purely balanced output sine wave and introduce perturbation on
one ½ cycle but not the other, will be generating even order distortion terms.
•
Suspects include –
– Mutual coupling in the negative supply pin to the non-inverting input
– Slightly imbalanced ground return currents getting into the input signal paths.
– Imbalanced supply decoupling impedance.
•
One of the best ways to eliminate this issue is to run the signal path differentially – but
exactly why does that work??
12
Why is it that a Differential Configuration
Suppresses the 2nd harmonic??
Differential even order harmonic cancellation
X1
+
A
y1
A
y2
V/2
Vcm
+
V/2
X2
Let both gain elements A have the same polynomial
approximation to a transfer function
13
Why is it that Differential configuration
suppress the 2nd harmonic??
y  Ao  A1 X  A2 X
X1  V
2
 A3 X 3
2
&
X 2  V
 2  2
 A V   A V 
2
2
y1  Ao  A1 V
y 2  Ao
2
 A2 V
2
1
2
then
 y1 
 2
 A V 
2
 A3 V
3
3
3

y 2   0  A1V  2 A3 V
 A1V 
•
2

2
3
A3
V3
4
Substituting in the two halves of differential input signal, getting to each output
signal, then taking the difference - shows we are theoretically only left with the
desired linear signal and the 3rd order term. Even if the A2 coefficient is not exactly
matched between the two amplifiers, it is their difference that ends up being the gain
for this 2nd order non-linearity at the output. We also see a reduction in the 3rd
order coefficient - arising from only applying 1/2 of the input through each channel.14
Single Ended Even order Terms become Odds
in the Differential Configuration
• In the time domain, this effect can be seen by producing a clipped waveform
for the two outputs, then taking the difference. The individual outputs would
have a very high even order harmonic content, while the differential signal
will still be distorted, but will give rise to only odd harmonics since the
clipping is now symmetric on each 1/2 cycle of the sinusoid.
Single ended to Differential Distortion
20
Differential Output
15
Output Voltages
10
5
0
-5
-10
-15
-20
0
1E-08
2E-08
3E-08
4E-08
5E-08
6E-08
7E-08
8E-08
9E-08
1E-07
Time (sec)
15
Single Ended vs. Differential SFDR
•
To illustrate the power of differential designs in suppressing HD2, the plots below show t
HD2 and HD3 for a low noise, low distortion VFB dual amplifier in both single ended and
differential configurations. The test conditions give the same loop gain, but the differentia
test had a 35ohm load to each output while the single ended was a 100ohm – which
raised the HD3 quite a bit.
16
Key Elements to Understanding and Improving Distortion
•
External conditions that will influence distortion
– Required Output Voltage and Current as a portion of the quiescent power and design
of the output stage
• This is including loading and supply voltage effects as well.
• Adding a higher standing current in the output stage will often lower distortion
with no effect on noise. This Class A current can pick up about 10dB on the 3rd.
– Loop gain – use a VFB designed for the desired gain setting or, at higher gains use a
CFB device.
– Frequency – since loop gain changes with frequency, a fixed output stage nonlinearity will give a changing distortion over frequency.
– Layout and Supply Decoupling
• This is covered in detail in TI – app. Note SBAA113
17
Applying these Concepts to the MFB Filter
• MFB Filter Design
– Transfer function with ideal Op amp
– Design choices and recommendations
– Loop gain analysis and implications
– Example Design with unity gain and non-unity gain
VFB Devices
– Example Design with FDA Device
18
Starting point for the MFB Filter Design
•
MFB (Multiple FeedBack) Low Pass Filter
R1
C2
R2
R3
Vi
C1
VO
+
•
•
•
Can also call this an “Integrator Based Filter” because imbedded inside the filter is
an integrator circuit (R2 and C2) which is of critical interest to the op amp for
stability.
Since it is an integrator op amp application, a couple of constraints come in
– Should be a unity gain stable voltage feedback op amp.
• We will overcome the unity gain stability constraint later but you cannot
(easily) use a current feedback device in this filter.
At DC, the signal gain is –R1/R3. Later, we will see that R3 only impacts the Q of the
filter shape (not the wo). Tuning R3 for Q will, however, also be changing the DC
Gain.
19
What advantages does an MFB filter provide.
1.
2.
3.
The MFB filter provides much better stopband rejection than
an equivalent Sallen-Key filter (also called VCVS filter)
The MFB filter is also much more forgiving of lower
bandwidth op amps in terms of the close loop pole
sensitivity to amplifier gain bandwidth product. At least for
low Q designs, it gets much more sensitivity at higher Q
In theory, it is impossible to make this circuit oscillate (at
least with really slow op amps put into the circuit)
20
Stop Band Rejection Comparison
The plot below compares two designs for a Butterworth low pass design using
an MFB and then a Sallen Key design using the same low speed
amplifier
Note the improved stopband rejection achieved for the MFB
The Sallen Key filter eventually shows signal feedthrough to the output
through the feedback capacitor that gives the rising portion of the output
curve.
(from sboa049b, Active Low Pass Filter Design, Jim Karki)
21
Ideal Transfer Function for the MFB Low Pass Filter
• The equations below show the transfer function – and the
key design elements resulting from this.
D.C .gain s  0 
AvD.C .  
Vo
1


Vi
C1C2 R2 R3
R1
R3
1
s2  s
1
C1C 2 R1 R2
wo 
 R3  
1 
1



R

R
1


3
2

C1 R2 R3 
 R1   C1C2 R1 R2
R1
C1
C2
Q
R1

R2
R2

R1
R1 R2
R3
C2
R2
R3
Vi
R
Or , with  1
R2
C1
VO
R2
+
C1
C2
R3
Q
-

  R3   

1 

 
22
MFB Filter Design Methodology
As is normally the case in active filter design, we have more
components to resolve than filter design parameters.
Here, there are 5 external elements to resolve from which we
need to set
– 1. DC Gain (this will be just -R1/R3). Call this Av and only use
the magnitude in the filter design (but we will get an inverting
gain through the filter)
– 2. Filter wo (characteristic frequency in radians)
– 3. Filter Q (quality factor, unitless)
We need to come up with 2 more constraints to uniquely resolve
all 5 component values to get a nominal design for the filter.
Another way to say this is that there is an infinite number of
external component combinations that will give the desired filter
shape. But the internal details of the filter performance vary
significantly as different component combinations are selected.
23
MFB Filter Design Methodology
– In active filter design the other issues that can be used to
constrain component values are noise and distortion. At low
frequencies, before the capacitors come into play for this low
pass filter, the noise of R2 adds directly to the voltage noise of
the op amp to set the apparent input noise voltage for
calculation purposes.
– It might not be too unreasonable to constrain R2 to add the
same (or lower) output noise power as the op amp’s input
noise voltage.
The full expression for output noise at low frequencies is relatively
complicated.
But first, let’s look at the DC part of this circuit and set up for DC
bias current cancellation using a resistor on the non-inverting
input - Rp
24
MFB DC Analysis Circuit
R1
Vi
R3
R2
+
RP
To improve the output DC precision, for bipolar input Op amps,
set R p  R  R || R
2 1 3
25
MFB Noise Analysis Circuit and Total Output Noise Equation
en
RP
*
*
*
+
in
en is the op amp voltage noise
in is the current noise – assumed equal
for VFB op amps on each input
eO
-
4kTRP
R2
*
in
*
4kTR2
R1
*
4kTR1
R3
*
4kTR3
eo 
4kTR
p
 e  in R p 
2
n
2
  R 

 R1 
 R 
 R 
1    4kTR2 1  1   4kTR1 1  1   in 2  R2 1  1   R1 
 R3 
 R3 
 R3 
  R3 


Non-inverting input terms
2
2
2
R1 and R3 noise
R2 terms
This is not attempting to include any bandlimiting effects of the filter caps.
Inverting current
noise term
26
Output Noise Analysis
•
This complete equation includes a couple of terms that we can safely
ignore.
– The Rp resistor is in place if bias current cancellation is part of the
intended design. However, in the final circuit a large capacitor should
be placed across this resistor to attenuate the noise contributions due
to Rp. Recall that CMOS or FET input stages (or current feedback
amplifiers in general) will not benefit from adding this Rp towards
improving output DC accuracy.
•
The en will come from the amplifier selected – so that is a fixed portion of
the total output noise equation.
R2 adds several terms that can, if you are not careful, dominate over the
en term. So if a low noise amplifier was selected for its noise, setting R2
consistent with that will retain the original intent.
R3 will also add noise in a similar fashion to R2 – it will turn out that setting
R3 ≈ R2 is good for other reasons – so we will use that as a working
assumption in setting an upper limit for R2 in this noise analysis
•
•
27
Approximate Target for a Maximum R2
• Pulling the en term out and setting equal (in power) to the terms
due to R2 and R3 – (neglecting the R1 terms as they will be set by
R3 and the target gain)
2

 R1  2
1   en  4kTR2  in R2 2
 R3 

 R1 
 R 
1    in 2  2 R2 R1 1  1  


 R3 
 R3  


2
Solving for R2
2
 4kT
  en 
2

R2  R2  2  2R1 || R3      0
 in
  in 
R1
As an approximation, let R3 = R2, then
using
R3
 Av
2
 1  Av  4kT  1  Av  en 
R22  R2 
 2 
   0
1

3
Av
1

3
Av

 in

 in 
Solving this
2


1  3 Av   enin 
 1  Av  2kT 
R2  

  1
 2  1
1  Av  2kT  
 1  3 Av  in 
28
Setting the Integrator Pole
•
•
With R2 selected from a noise control
perspective, we can then proceed to
picking C2 to put the integrator pole over a
wide range of locations. Then, with 2 of
the 5 passive elements selected, the
target filter shape can be set with the
remaining 3.
It is best to look at the (1/R2C2) issue from
a noise gain control standpoint. The
following circuit is the feedback analysis
circuit for the MFB filter where an added
capacitor (CT) is included at the inverting
node – this will be either a parasitic that
needs to be included or a tuning capacitor
for phase margin control. It has no direct
impact on the desired filter transfer
function but can impact loop gain & phase
margin significantly.
R1
V-
VO
R2
C2
CT
C1
R3
Source input, assumed
low impedance
29
Noise Gain Transfer Function
• The following equation is the gain from Vo to V-. This is often called
β in the control theory literature. The “noise gain” (1/β) is also
given below.
 1

1
1
2
s

s


 C R C R || R  C C R R
V
C2
1
1
2 
1 2 1 2
 1 3



VO CT  C2 2  1

1
1
1
s  s




 C1 R3 C1 R1 || R2  R2 CT  C2  R2 R1 || R3 C1 CT  C2 
 1

1
1
1
s2  s




1  CT 
 C1 R3 C1 R1 || R2  R2 CT  C2  R2 R1 || R3 C1 CT  C2 
 
 1 
  C2 
 1

1
1
s2  s



 C1 R3 C1 R1 || R2  C1C2 R1 R2
As is always the case, the poles of the noise gain are the same as the desired filter poles. It
is useful to re-write this 1/β in terms of the target filter elements (letting CT = 0 to simplify)
30
Noise Gain Transfer Function
•
Re-writing the Noise Gain (1/β) in terms of the desired filter design terms gives
(where that equation is simplified by letting CT=0, for now)

1 
2
s2  s O 
 1  AV O

R2C2 
1
 Q


 
2
s 2  s  O   O
 Q 
•
•
•
•
The poles are again the desired filter ωo and Q while the zeroes are also set by
these terms plus an added (1/R2C2) in the linear term.
Important points
– At DC (s=0), the noise gain is 1 + Av
– At s ∞, the noise gain becomes 1 + CT/C2 (from the previous full eq.)
– The 2 – zeroes and 2 poles control the transition between these two gains.
– The only added degree of freedom in setting the zeroes is the integrator pole
location – everything else is already determined by the desired filter shape.
It can be proven that the zeroes are always real – it is not possible to get complex
zeroes in this equation.
31
Setting the 1/R2C2 becomes the focus of the design from here.
MFB Filter Design Methodology
Stepping through some algebra to get an isolated solution for C1, the following
expression results that only leaves us to select C2 (if R2 is already chosen)
Q
C1 
wo R2 1  Qwo R2C2 1  Av 
The wo (R2C2) term is of some interest. This is the ratio of the target ωo to the
embedded integrator pole. The equation above will only solve for a nonnegative C1 if the term in the denominator is positive.
wo R2C2 
1
Q1  Av 
C1  0
This sets a limit to the maximum ratio of wo to the integrator pole. Moving the
R2C2 term around (always satisfying the constraint implied by the above
equation), will be changing the noise gain zeroes as shown on the previous
slide which will then be changing the loop gain
32
Setting the Range on the Integrator Pole
It is a bit simpler to work with this ωo (R2C2) term inverted. That then becomes the ratio of
the integrator pole to the desired filter characteristic frequency and normally will be a
ratio >1. Doing that gives a minimum limit on this ratio of
1
Integrator Pole

 Q1  Av

0
0 R2C2
This shows that the integrator pole must be set at least this Q*(1+AV) greater than the
target ωo to get a valid solution for C1. In the limit, where we do solve for C1=∞, we
also get R3 = 0Ω. As we move the target 1/R2C2 term up, the noise gain zeroes will
spread apart with one going up with 1/R2C2 and the other coming down. Also R3 will
increase from 0Ω and C1 will come down from ∞. One interesting point on this
continuum is where R3 = R2. That will result when the following relationship is set to
equality.
1
Integrator Pole 
 Q1  2 Av 

0
0 R2C2
This is showing Q(1+2*Av) as a maximum limit to the ratio of the integrator pole to ωo –
that is only if R3 ≤R2 is desired from a total output noise perspective. Valid solutions
will result moving the integrator pole further out (R3>R2), but will give higher noise
(due to the higher R3 value) and reduced SFDR as the noise gain will start to peak at
frequencies below ωo when the lower noise gain zero drops below ωo
33
Summary of MFB Design Methodology
1.
2.
3.
4.
5.
6.
7.
8.
9.
Set your filter design targets
Select a possible amplifier and get its noise numbers
The higher the Gain Bandwidth Product, the higher the loop gain will be at a
particular frequency. Also, some GBW margin is needed to hit the desired
pole locations. FilterPro suggests the gain bandwidth product be
100*Q*AV*Fo The AV term is correct for Sallen Key using VFB amplifiers –
but for MFB, we go unity gain at high frequencies and this is too restrictive
Compute an initial value for R2 to not be a dominate noise source at the output
Select the ratio of 1/R2C2 to ωo to give an R3≤R2
Compute C1 using the equation shown earlier
Compute R3 using the following expressions
Set R1 to get the gain
Check loop gain and phase margin in the design
Add CT if phase margin too low
This is all set up in a design spreadsheet available with an application note – “Design
Methodology for MFB Filters in ADC Interface Applications” SBOA114 on the TI web
site.
34
Example Designs using Spreadsheet
Target a 3rd order Butterworth with F-3dB = 1.2Mhz with a gain of -4V/V
– Go into Filter Pro to get the pole locations –
– Real pole at 1.2Mhz, Complex poles at 1.2Mhz = Fo and Q = 1.
3. Select the amplifier – Consider amplifier with a GBW > 100*Fo*Q to get accurate
filter results – this would be >120Mhz gain bandwidth product
4. Assume we are driving a 16bit converter with a 4Vpp input range and do not want
the integrated noise to exceed ½ LSB in an RMS sense. Estimate Noise Power
Bandwidth as 1.2*F-3dB = 1.44Mhz.
Then eo < (4Vpp/(217))/(√1.44Mhz) = 25.2nV/√Hz
Then input referred en should be < 25.2/4 = 6.3nV/ √Hz
(analysis from “Noise Analysis for High Speed Op Amps” SBOA066)
So we need GBW > 120Mhz and en <6.3nV/√Hz total including resistor noise –
Allow the amplifier to be up to ½ of this total giving an allowed input of 3.15nV/√Hz
for just the amplifier en.
35
Example Designs using Spreadsheet
Going into the selection table, we find this is a pretty tough
requirement, The only single channel amplifiers with low enough
noise and high enough GBW are listed below. The OPA2613 dual
and THS4131 FDA would also meet this if differential I/O was an
eventual target for the design
From this, let’s first try the OPA820 and then the OPA846
The amplifier will be used to get the complex poles with Q = 1 and
Fo = 1.2Mhz. The real pole at 1.2Mhz will be added as a post RC filter
36
Initial Design Example using OPA820
37
Design Example using OPA820 – Loop Gain
38
First Example Circuit
1.2kW
49pF
+5V
300W
300W
-
Vi
995pF
250W
3pF
OPA820
530pF
+
1uF
540W
-5V
Real 1.2Mhz pole at output designed by targeting the noise of voltage of
the series resistor to be 1/10 the noise at the OPA820 output. The
540Ω on the V+ input gets bias current cancellation.
39
Summary Details on the OPA820 Design
1.
2.
3.
4.
5.
6.
7.
This design set R2=300Ω and R3 = 300Ω by setting the ratio of the
integrator pole/Fo at the suggested value of 9x.
This gave the desired filter design with a total input referred en =
4.95nV/√Hz (lower than the target 6.3nV/√Hz)
Only parasitic CT on the inverting node was used (3pF) since the
OPA820 is unity gain stable. We estimate 53deg. phase margin.
C2 = 49.1pF and C1 = 995pF gave the desired filter shape.
Noise gain zeroes at 633kHz and 10.7Mhz
Loop gain at Fmax = 1Mhz was 29dB
Simulated distortion for 4Vpp output at RC filter output
At 200kHz input HD3 = -95dBc
At 1Mhz input HD3 = -89dBc (3rd falling at 3Mhz, getting rolled off.)
40
Impact of Higher Integrator Pole
Now take this design and intentionally increase the integrator pole
location beyond the point that an R3 =R2 design would
result. (> than the 9 ratio shown in the spreadsheet)
This will have the effect of splitting the zero frequencies wider
apart, moving one much lower in frequency and the other
higher. It will also then solve for an R3>R2 which is good for
increasing the input impedance but will increase output noise.
The original OPA820 design set the 1/R2C2 at 9X the target Wo as
computed in the spreadsheet to get R3 = R2.
Overriding this and setting that Ratio to 20X puts the integrator
pole at 20*1.2Mhz = 24Mhz. This puts the noise gain zeroes
at 288kHz and 22Mhz causing added noise gain peaking
below the 1.2Mhz cutoff.
41
Modified OPA820 Design with Lower Noise Gain
Zero Peaking < F-3dB
42
Modified OPA820 Circuit With Noise Gain
Peaking
4.5kW
22pF
+5V
300W
1.12kW
Vi
589pF
250W
3pF
OPA820
530pF
+
1uF
1.19kW
-5V
Real 1.2Mhz pole at output designed by targeting the noise of voltage of
the series resistor to be 1/10 the noise at the OPA820 output. The
1.19kΩ on the V+ input gets bias current cancellation.
43
Summary Details on Modified OPA820
Design
1.
2.
3.
4.
5.
6.
7.
This design set R2=300Ω and R3 = 1.12kΩ by targeting the integrator
pole/Fo ratio at 20X.
This gave the desired filter design with a total input referred en =
6.8nV/√Hz (> than the 4.95nV before and> target max. of 6.3nV/√Hz)
Only parasitic CT on the inverting node was used (3pF) since the
OPA820 is unity gain stable. We estimate an improved 58deg. phase
margin.
C2 = 22pF and C1 = 589pF gave the desired filter shape.
Noise gain zeroes at 288kHz and 22Mhz
Loop gain at Fmax = 1Mhz was 23.5dB (5.5dB less than before)
Simulated distortion for 4Vpp output at output of the RC stage
At 200kHz input HD3 = -91.5dBc (vs. -95dBc previously)
At 1Mhz input HD3 = -84dBc (vs. -89dBc previously)
44
Filter Design Using Higher Gain Bandwidth
Op Amp
Now repeat this same filter design using a much higher gain bandwidth
amplifier than the OPA820
In this case, the OPA846 will be used – this gives the following benefits.
1. Lower input noise voltage (1.2nV vs. 2.5nV)
2. Higher Gain Bandwidth (1750MHz vs. 280Mhz)
3. Higher Slew Rate (645V/µsec vs. 240V/µsec)
However, the OPA846 is non-unity gain stable – so, once the C2 capacitor is
chosen to get the desired filter shape, an added CT on the inverting
node must be added to get a high frequency noise gain that is close to
the stated minimum stable gain (7V/V). This can be done just by trial
and error observing the reported phase margin as CT is updated. I
targeted about 45deg. Minimum level here. Increasing CT further does
hurt output noise and loop gain at band edge.
To take advantage of the lower input noise voltage of the OPA846, lower R2
and R3 resistor values are needed. Here a design using R3 < R2 will be
done initially – remember R3 will be in the input impedance to the filter.
45
Higher Loop gain Design Using the OPA846
46
2nd Design Example using OPA846
47
Higher Loop Gain Example Design
400W
95pF
+5V
100W
200W
2300pF
102W
450pF
OPA846
1300pF
+
1uF
280W
-5V
Real 1.2Mhz pole at output designed by targeting the noise voltage
of the series resistor to be 1/10 the noise at the OPA846 output. The
280Ω on the V+ input gets bias current cancellation.
48
Summary Details on the OPA846 Design
1.
2.
3.
4.
5.
6.
7.
This design set R2=200Ω and R3 = 100 Ω. Noise analysis suggested R2 =
81Ω but I wanted to set R3 < R2 here so I increased R2 to 200Ω and
reduced the target ratio of the integrator pole/Fo from the 9X (shown to get
to R3=R2) to a 7X target which gave the R3 = 100Ω
This gave the desired filter design with a total input referred en = 3.2nV/√Hz
Added 450pF on the inverting node since the OPA846 is not unity gain
stable. Estimating 46deg. phase margin with this tuning element in place.
C2 = 95pF and C1 = 2300pF gave the desired filter shape.
Noise gain zeroes at 611kHz and 20.5Mhz
Loop gain at Fmax = 1Mhz was 42dB
Simulated distortion for 4Vpp output at the RC filter output was At 200kHz input HD3 = -138dBc
At 1Mhz input HD3 = -128dBc (3rd falling at 3Mhz, getting rolled off.)
49
Design Using the OPA846 with lower noise gain
zero reducing in band loop gain.
50
OPA846 design with lower noise gain zero
51
OPA846 with Lower Noise Gain Zeroes
3kW
33pF
+5V
750W
200W
884pF
102W
150pF
OPA846
1300pF
+
1uF
800W
-5V
Real 1.2Mhz pole at output designed by targeting the noise voltage
of the series resistor to be 1/10 the noise at the OPA846 output. The
800Ω on the V+ input gets bias current cancellation.
52
Summary Details on the OPA846 Design
having lower noise gain Zero
1.
2.
3.
4.
5.
6.
7.
This design set R2=200Ω and R3 = 750 Ω. This results from setting the target
integrator pole/Fo = 20X.
This gave the desired filter design with a total input referred en = 5.5nV/√Hz
Added 150pF on the inverting node since the OPA846 is not unity gain
stable. Estimating 43deg. phase margin with this tuning element in place.
C2 = 33pF and C1 = 884pF gave the desired filter shape.
Noise gain zeroes at 246kHz and 5.3Mhz
Loop gain at Fmax = 1Mhz was 36dB (6dB lower than previous OPA846 ckt)
Simulated distortion for 4Vpp output at the RC filter output was At 200kHz input HD3 = -127.3dBc (vs. -138dBc previously)
At 1Mhz input HD3 = -120.4dBc (vs. -128dBc previously)
53
Filter Design Using a Low Noise FDA
Now repeat this same filter design using an FDA to implement a
differential in to differential out design.
In this case, the THS4130 will be used –
Low noise (1.3nV/√Hz)
Good Gain Bandwidth (180Mhz)
Relatively Low Slew Rate (52V/usec)
4Vpp output at 1.2Mhz requires 15V/usec slew rate.
Extremely low distortion cannot be expected at 1.2MHz
with such a low design margin.
FDA’s that are quoted as unity gain stable, are really operating at a
noise gain of 6dB. The FDA topology presents a true unity noise
gain at high frequencies due to the feedback cap. Hence, lower
phase margin than might be expected results. Here an added
cap. across the inputs was used to improve the phase margin.
54
Design Using the THS4130 FDA to get a
Differential I/O MFB Filter.
55
THS4130 Loop Gain Plot
56
THS4130 Differential I/O MFB Filter Design
for a 3rd order 1.2Mhz Butterworth
800W
74pF
+15V
200W
200W
119W
+
1490pF
VI
10pF
THS4130
557pF VO
1490pF
200W
119W
200W
-15V
74pF
800W
Real 1.2Mhz pole at output designed by targeting the noise voltage
of the series resistor to be 1/10 the noise voltage at the THS4130
output.
57
Summary Details on the THS4130 FDA
Design for a 1.2Mhz 3rd Order Butterwoth
1.
2.
3.
4.
5.
6.
The spreadsheet recommended R2 = 104Ω but I used 200Ω to increase
the resistors somewhat to limit loading related distortion degradation.
Total input referred noise estimated to be 3.44nV/√Hz for single side –
need to take √2 * 3.44nV = 4.85nV √Hz to get total differential input
referred noise.
Selected R3 = R2 by setting the integrator pole at 9*Fo.
Since the THS4130 is compensated for 0dB signal gain (6dB noise gain)
and, the C2 feedback cap takes this circuit a true 0dB noise gain at high
frequencies – we saw < 40deg nominal phase margin with no CT in place.
With C2 set to 74pF, I added 20pF CT and increased phase margin to
54deg.
Loop gain at Fmax = 21.4dB.
Collapsed CT and output real pole capacitor into 1 differential value by
connecting across the two circuit halves with ½ the value. Kept C1’s
separate to get common mode filtering in the forward path.
Distortion performance unknown but should give great HD2. Still need to
test and/or simulate this circuit.
58
Summary MFB Filter Design Suggestions
1.
2.
3.
4.
5.
6.
Set targets – Use the MFB for relatively low Q requirements
Pick an amplifier from noise, Gain Bandwidth requirements
Start design by picking R2 close to spreadsheet suggested value
Set 1/R2C2 by picking a ratio of this to ω0 ≤ value required to get R3 =
R2. This will control noise contribution due to R3 and keep the noise
gain zeroes placed relatively high to avoid in band noise gain peaking
and loop gain loss.
Complete design, check phase margin and loop gain at max.
operating frequency. Check that prior stage can drive R3 without too
much loss in distortion performance.
Check design in Pspice or Tina – check for filter shape as desired –
compare to spreadsheet plot for ideal filter shape and if way off, use a
faster amplifier or adjust R3 up. Slow amplifiers mainly reduce the Q
but do not change the ω0 very much in the MFB topology. Increasing
R3 will increase Q but will not move the ω0 while also reducing gain.
59