Download controlo de um dirigível

PROJECTO I
EM ENGª
ELECTRÓNICA
E COMPUTADORES
CONTROLO DE UM
DIRIGÍVEL
JOÃO ALEXANDRE Nº 3408
SÉRGIO ALMEIDA Nº 3594
24 DE OUTUBRO DE 2003
Escola Superior de Tecnologia de Setúbal
Projecto Final de Curso
ESCOLA SUPERIOR DE TECNOLOGIA DE
SETÚBAL
INSTITUTO POLITÉCNICO DE SETÚBAL
DEPARTAMENTO DE ENGENHARIA
ELECTROTÉCNICA
CONTROLO DE UM
DIRIGÍVEL
João Alexandre
Sérgio Almeida
Projecto para obtenção do Bacharelato em
Engª Electrónica e Computadores
Outubro de 2003
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Projecto realizado sob a orientação
do
Prof. António Abreu
Departamento de Engenharia Electrotécnica
Escola Superior de Tecnologia de Setúbal
Instituto Politécnico de Setúbal
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Agradecimentos
Em primeiro lugar há que salientar a elevada importância do Prof. António Abreu que
apresentou uma “infinita” disponibilidade durante todo o decorrer do projecto,
disponibilidade esta que permitiu o esclarecimento de dúvidas que foram surgindo ao
longo do tempo.
O contributo dos seguintes colegas foi também muito importante para a realização deste
projecto.
Agradecimentos aos colegas Marco Silva e Rui Pimenta, pelo apoio dado no que diz
respeito a fornecimento de material necessário e também pelos conhecimentos úteis.
A todos os colegas que realizaram os seus projectos, que contribuíram dando apoio e
incentivo.
Há que referir a disponibilidade mostrada por um dos funcionários da empresa Balão
Balão, no que diz respeito ao fornecimento de Hélio e ao contributo para o aumento de
conhecimentos úteis ao projecto.
Por último, há que referir o contributo do Sr. Vítor Neves pelos conhecimentos
relativamente a uma ferramenta de software que foi utilizada.
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Resumo
Este trabalho tem como objectivo o desenvolvimento de um controlador de um dirigível a
hélio, de modo a que este se possa deslocar num ambiente tridimensional.
O dirigível é composto por um balão, três motores de corrente contínua e sensores
ópticos. Dois dos motores controlam o deslocamento do Balão na horizontal, tendo o
outro motor a função de controlar o Balão na vertical. Os sensores determinam a
distância do balão aos obstáculos que estejam na direcção do eixo dos sensores.
São apresentados os pormenores relativos aos desenvolvimentos realizados (software e
hardware) e são mostrados dois exemplos de controlo sobre o balão.
O primeiro exemplo assenta num controlo da altitude e o segundo num sistema autónomo
simples, denominado Robot Minimalista.
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Abstract
The purpose of this work is to develop an autonomous system that has ability to fly on a
three-dimensional environment.
A blimp, three DC motors and optical sensors compose the system. Two motors control
the horizontal movements of the system. The third motor controls the system movement
in the vertical. The sensors determine the distance between the Blimp and obstacles that
are in the sensor axis direction.
All details regarding the development of the project (software and hardware) are shown,
as are two examples of control over the blimp.
The first example shows an altitude control of the blimp and the second is based on a
very simple autonomous system, called Robot Minimalista.
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Palavras Chave
Sensor
Controlo
Dirigível
Motor
Hélio
Estabilidade
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Keywords
Sensor
Control
Blimp
Motor
Helium
Stability
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Índice
1.
Introdução ................................................................................................................... 1
1.1
Abordagem Genérica .......................................................................................... 1
1.2
Organização do Relatório do Projecto ................................................................ 2
2. Dirigível ...................................................................................................................... 3
2.1
Aquisição do Dirigível........................................................................................ 3
2.2
Características do Dirigível................................................................................. 3
2.2.1
Motores ....................................................................................................... 4
2.2.1.1 Motores de corrente contínua.................................................................. 4
2.2.1.2 Motores do Balão.................................................................................... 5
2.2.2
Cockpit........................................................................................................ 6
2.2.3
Balão ........................................................................................................... 7
2.2.3.1 Tipos de Balões....................................................................................... 7
2.2.3.2 Calculo do peso suportado pelo Balão utilizado..................................... 7
2.2.3.3 Estabilidade do Balão ........................................................................... 10
2.2.3.3.1 Testes efectuados ............................................................................ 11
2.2.3.3.2 Resultados ....................................................................................... 11
3. Hardware Desenvolvido............................................................................................ 14
3.1.
Controlo de Motores ......................................................................................... 14
3.1.1
PWM ......................................................................................................... 14
3.1.2
Controlo do sentido de rotação ................................................................. 15
3.1.3
Ponte em H................................................................................................ 16
3.1.4
CPLD ........................................................................................................ 17
3.2
SENSORES....................................................................................................... 17
3.2.1
SENSOR DE MEDIÇÃO DE DISTÂNCIAS .......................................... 17
3.2.1.1.
Caracterização do Sensor.................................................................. 18
3.3. ADCs................................................................................................................. 19
3.4.
FOTOTRANSÍSTORES................................................................................... 22
3.5. LDRs ................................................................................................................. 24
3.6.
ALIMENTAÇÃO ............................................................................................. 26
4. Experiências.............................................................................................................. 27
4.1.
Controlo de Altitude ......................................................................................... 27
4.1.1
Controlo em malha fechada ...................................................................... 27
4.1.1.1.
Acção proporcional........................................................................... 28
4.1.1.2.
Acção Integral................................................................................... 29
4.1.1.3.
Acção Derivativa .............................................................................. 30
4.1.2
Software de Controlo ................................................................................ 31
4.1.3
Resultados ................................................................................................. 32
4.2
Robot Minimalista ............................................................................................ 39
5.1
Conclusões ........................................................................................................ 43
5.2
Futuros desenvolvimentos ................................................................................ 44
Referências Bibliográficas ................................................................................................ 45
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Lista de Figuras
Figura 2. 1 - Cockpit do Dirigível....................................................................................... 3
Figura 2. 2- Caracterização da rotação de um motor corrente contínua ............................. 5
Figura 2. 3 – Hélice de um dos motores do Dirigível......................................................... 6
Figura 2. 4 – Desenho do Balão em AutoCad .................................................................... 8
Figura 2. 5 - Calculo do volume do Balão .......................................................................... 8
Figura 2. 6 - Forças que actuam sobre o Dirigível............................................................ 10
Figura 2. 7 - Balão com fios.............................................................................................. 11
Figura 2. 8 – Gráfico da altitude do balão com fios lançado abaixo do PE...................... 12
Figura 2. 9 – Gráfico da altitude do balão com fios lançado acima do PE....................... 12
Figura 3. 1 - Circuito PWM .............................................................................................. 15
Figura 3. 2 - Circuito descodificador ............................................................................... 15
Figura 3. 3 - Ponte H......................................................................................................... 16
Figura 3. 4 - Sensor de infravermelhos............................................................................. 18
Figura 3. 5 - Caracterização do sensor relativamente a objectos de diferentes cores....... 18
Figura 3. 6 – Tipo de ADCs quanto ao Interface.............................................................. 19
Figura 3. 7 – Resposta Característica do ADC ................................................................. 20
Figura 3. 8 – Ciclo de conversão do ADC (MAX1112) ................................................... 21
Figura 3. 9 – Fototransistor............................................................................................... 22
Figura 3. 10 - Resposta do fototransistor face às diferentes cores.................................... 22
Figura 3. 11 - Circuito implementado para o Fototransistor............................................. 23
Figura 3. 12 - LDR............................................................................................................ 24
Figura 3. 13 - Ligação do LDR......................................................................................... 24
Figura 3. 14 - Circuito implementado para medir a tensão no LDR................................. 25
Figura 3. 15 - Bateria (Idêntica à utilizada) ...................................................................... 26
Figura 4. 1 - Controlo proporcional .................................................................................. 28
Figura 4. 2 - Controlo Integral .......................................................................................... 29
Figura 4. 3 - Controlo Derivativo ..................................................................................... 30
Figura 4. 4 – Janela do Software realizado ....................................................................... 31
Figura 4. 5 - Controlo proporcional com Kp = 5 .............................................................. 32
Figura 4. 6 - Controlo proporcional com Kp = 10 ............................................................ 32
Figura 4. 7 - Controlo proporcional com Kp = 15 ............................................................ 33
Figura 4. 8 - - Controlo proporcional com Kp = 20......................................................... 33
Figura 4. 9 - Controlo Pd com Kd = 5 .............................................................................. 34
Figura 4. 10 - Controlo Pd com Kd = 7 ............................................................................ 34
Figura 4. 11 - Controlo Pd com Kd = 9 ............................................................................ 35
Figura 4. 12 - Controlo Pi com Ki = 1 .............................................................................. 36
Figura 4. 13 - Controlo Pi com Ki = 2 .............................................................................. 36
Figura 4. 14 - Controlo Pi com Ki = 3 .............................................................................. 37
Figura 4. 15 – Gráfico de altitude do balão com fios........................................................ 38
Figura 4. 16 – Gráfico de altitude do balão com fios passado uma hora.......................... 38
Figura 4. 17 – Cockpit do Dirigível com os LDRs e o Fototransistor acoplados ............. 39
Figura 4. 18 – Sinal à saída do circuito do PWM para um nível de luminosidade inferior
ao valor de referencia................................................................................ 40
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Figura 4. 19 – Foco de luz a incidir sobre o LDR do lado direito do cokpit do balão...... 41
Figura 4. 20 – Foco de luz a incidir sobre o Fototransistor .............................................. 42
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Lista de Tabelas
Tabela 4. 1 – Peso de todos os componentes utilizados no Robot Minimalista ............... 42
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Lista de Abreviaturas
ADC
Conversor Analógico Digital
CPLD
Circuito de Lógica Programável
LDR
Resistência Variável com a Luz
(Light Dependent Resistor)
PWM
Modulação em Largura de Pulso
(Pulse Width Modulation)
P
Controlador Proporcional
PD
Controlador Proporcional-Derivativo
PI
Controlador Proporcional-Integral
DC
Corrente contínua
(Direct current)
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Introdução
Este capítulo encontra-se divido em duas partes. A primeira é relativa à caracterização do
projecto, que passa primeiro por uma abordagem genérica à área em que o projecto se
engloba, e por último, na particularização do sistema em questão, mostrando as possíveis
aplicações que um projecto com estas características poderá ter.
Na segunda parte é feita uma descrição da organização do relatório, nomeadamente o
conteúdo geral de cada um dos capítulos.
1.1 Abordagem Genérica
A robótica é uma área de investigação que tem despertado desde há muito tempo o
interesse de muitas empresas.
Tem-se como exemplo a empresa japonesa Honda, que desde algumas décadas tem vindo
a desenvolver vários protótipos de robots terrestres. Robots estes que têm como objectivo
parecerem-se o mais possível com um ser humano, no que diz respeito à forma e
locomoção.
No entanto, quando se fala de robótica aérea, a situação já é diferente. A investigação
nesta vertente da robótica não se encontra tão desenvolvida.
Como robots aéreos podem-se ter aviões, helicópteros e balões. As diferenças entre estes
residem na sua constituição, o que requer tipos de controlo diferente.
No caso dos aviões existe a necessidade de se atingir uma determinada velocidade, de
modo a que o efeito aerodinâmico de sustentação funcione e o avião permaneça no ar.
Com efeito, quando isso não acontece, o avião perde sustentação, podendo despenhar-se.
Por seu turno, no helicóptero existe a possibilidade de o poder estabilizar num dado
ponto, i.e., ter-se velocidade de deslocamento nula. Isto é possível devido à disposição
dos motores. Por ultimo têm-se os balões. A sustentação de um balão no ar é garantida
pelo composto químico que é utilizado para encher o mesmo.
O balão é considerado o robot aéreo mais estável por não necessitar da actuação de
motores para se sustentar no ar.
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De referir duas das principais aplicações que os robots aéreos podem ter. A primeira
aplicação refere-se a uma possível utilização em funções de entretenimento. A outra
aplicação diz respeito à utilização em sistemas de vigilância (incêndios e aplicações
militares).
Neste documento relata-se o projecto do controlo de um balão a hélio com
aproximadamente 120 litros de capacidade, adquirido recentemente pelo Departamento
de Engenharia Electrotécnica da Escola Superior de Tecnologia de Setúbal do Instituto
Politécnico de Setúbal. É descrito o projecto do controlo dos motores, baseado em
microcontrolador, e são descritos os sensores utilizados. São ainda relatadas duas
experiências de controlo com objectivos diferentes. Numa faz-se o controlo da posição
em altitude, recorrendo a controladores P, PI e PD. Na outra descreve-se um sistema
simples em que os sensores são ligados directamente aos motores. Em ambas as situações
são realizadas experiências e discutidos os resultados. O balão revelou-se um sistema
difícil de controlar, dado ser muito leve, ou seja, é muito sensível a interferências
externas e praticamente não ser influenciado pelo atrito, ou seja, pequenos movimentos
demoram muito tempo a desaparecer.
1.2
Organização do Relatório do Projecto
Este projecto encontra-se organizado em cinco capítulos:
•
No capítulo 2 caracteriza-se o Dirigível utilizado.
•
No capítulo 3 descreve-se o hardware desenvolvido.
•
No capítulo 4 vão ser descritas as experiências e discutidos os resultados
obtidos.
•
Por fim, no capítulo 5 apresentam-se as conclusões do trabalho
desenvolvido e as perspectivas de trabalho futuro.
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Dirigível
Este capítulo irá assentar inicialmente numa introdução relativamente à obtenção do
dirigível, sendo posteriormente descritos todos os elementos que o constituem.
2.1
Aquisição do Dirigível
De modo a realizar o projecto, foi necessário primeiro que tudo obter um balão e
motores. Como tal foram realizadas inúmeras pesquisas na Internet com vista a este fim.
Em Portugal os resultados da pesquisa foram praticamente nulos. Como tal optou-se por
adquirir um dirigível a uma empresa sediada no estrangeiro, mais propriamente no
Canadá.
2.2
Características do Dirigível
A opção da compra de um dirigível foi uma mais valia em relação a uma possível compra
de um balão e dos motores à parte. A mais valia reside no facto de o dirigível já trazer
uma estrutura que suporta os motores e um cockpit que permite colocar uma possível
electrónica e alimentação.
Na Figura 2.1 pode ver-se a estrutura que suporta os motores e o cockpit do dirigível.
Figura 2. 1 - Cockpit do Dirigível
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O dirigível adquirido é constituído por um pacote que engloba um balão, um cockpit que
suporta os três motores, uma placa PCB com a electrónica de controlo dos motores e um
comando de radio frequência para comandar o dirigível.
Deste pacote foi aproveitado apenas o balão, o cockpit e respectivos motores. A possível
utilização do modulo de RF que o balão trazia foi posta de lado devido a este ser
Unidireccional.
2.2.1 Motores
Nesta secção irá ser realizada uma introdução relativamente aos motores de corrente
contínua, para depois ser feita uma caracterização dos motores utilizados no Dirigível.
2.2.1.1
Motores de corrente contínua
Todos os motores eléctricos valem-se dos princípios do electromagnetismo, mediante os
quais condutores situados num campo magnético e atravessados por correntes eléctricas
sofrem a acção de uma força mecânica, por exemplo, electroímans exercem forças de
atracção ou repulsão sobre outros materiais magnéticos. Na verdade, um campo
magnético pode exercer força sobre cargas eléctricas em movimento. Como uma corrente
eléctrica é um fluxo de cargas eléctricas em movimento num condutor, conclui-se que
todo condutor percorrido por uma corrente eléctrica, imerso num campo magnético, pode
sofrer a acção de uma força.
Num motor há dois electroímans em que um impulsiona o outro. O electroíman tem
algumas vantagens sobre um íman permanente:
•
Podemos torná-lo mais forte.
•
O seu magnetismo pode ser criado ou suprimido.
•
Os seus pólos podem ser invertidos.
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Figura 2. 2- Caracterização da rotação de um motor corrente contínua
Um íman permanente tem os pólos norte e sul definidos. Um electroíman também os tem
mas a característica de cada pólo (norte ou sul) depende do sentido da corrente eléctrica.
Quando se altera o sentido da corrente, a posição dos pólos também se altera, do norte
para o sul e de sul para norte.
Um dos electroímans de um motor tem uma posição fixa; está ligado à armação externa
do motor e é chamado rotor . O outro electroíman está colocado no eixo de rotação e tem
o nome de estator. Quando se liga o motor, a corrente chega à bobina do campo,
determinando os pólos norte e sul. Há, também, o fornecimento de corrente ao íman da
armadura, o que determina a situação norte ou sul dos seus pólos. Os pólos opostos dos
dois electroímans atraem-se, como acontece nos imanes permanentes. O íman da
armadura, tendo movimento livre, gira, a fim de que o seu pólo norte se aproxime do pólo
sul do íman do campo e o seu pólo sul do pólo norte do outro. Se nada mais acontecesse,
o motor pararia completamente. Um pouco antes de se encontrarem os pólos opostos, no
entanto, a corrente é invertida no electroíman da armadura, (com o uso de um comutador)
invertendo, assim a posição de seus pólos; o norte passa a ser o que está próximo ao norte
do campo e o sul passa a ser o que está próximo ao sul do campo (Figura 2.1). Eles então
repelem-se e o motor continua em movimento. Esse é o princípio de funcionamento do
motor de corrente contínua.
2.2.1.2
Motores do Balão
Como foi referido anteriormente, o Dirigível é constituído por 3 motores (Figura 2.1).
Os motores são de corrente contínua e apresentam um tamanho e peso reduzidos.
Na extremidade do eixo de cada um dos motores encontra-se acoplada uma hélice (Figura
2.3) que tem como função fazer deslocar o ar e assim movimentar o balão.
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Figura 2. 3 – Hélice de um dos motores do Dirigível
Têm-se as seguintes características dos motores:
•
A velocidade dos motores é máxima para um valor próximo dos 3 Volts;
•
Para a velocidade máxima tem-se que o valor da corrente consumida ronda os
200mA para cada um dos motores;
•
Os motores rodam nos dois sentidos; para mudar o sentido de rotação basta mudar
a polaridade da alimentação.
2.2.2 Cockpit
O cockpit do balão apresenta um formato aerodinâmico e tem como função suportar os
motores. Outra possível função do cokpit pode ser o sustento de alguma electrónica e
uma possível bateria.
Os dois motores laterais encontram-se suportados por uma haste que se encontra ligada
ao cockpit. O outro motor encontra-se na parte detrás do Cockpit. O cockpit é feito de
plástico, permitindo assim que seja o mais leve possível. A haste por outro lado é feita de
um metal que apresenta alguma rigidez.
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2.2.3 Balão
Nesta secção faz-se uma introdução relativamente a balões, sendo posteriormente
calculado o peso suportado pelo balão utilizado e analisada a estabilidade do mesmo.
2.2.3.1
Tipos de Balões
Como materiais mais conhecidos para a construção de balões tem-se o látex e o foil. O
látex é um material mais resistente que o foil mas que apresenta uma maior
permeabilidade ao hélio ou hidrogénio.
Por um lado, a resistência do balão é uma mais valia, pois permite que o balão aguente
uma maior pressão relativamente aos balões de foil. Todavia a permeabilidade é uma
grande desvantagem. Como tal, o dirigível utilizado é constituído por um balão de foil. O
balão utilizado apresenta uma forma aproximada de um elipsoide.
2.2.3.2
Calculo do peso suportado pelo Balão utilizado
Tendo em vista que o sistema controlador irá ser suportado pelo balão, calculou-se o peso
máximo que este é capaz de sustentar.
De salientar que só através da obtenção desse peso se poderá saber a quantidade de
electrónica a utilizar.
Para calcular o peso máximo suportado pelo balão começou-se por calcular o volume.
Puseram-se várias hipóteses para o cálculo do volume. Uma das hipóteses seria emergir o
balão dentro de um depósito com água e verificar a diferença de nível antes e após
emergir o balão. Esta hipótese foi posta de lado devido à diferença de pressões (água e
hélio) ser muito grande.
A técnica utilizada para calcular o volume do balão assentou na utilização de uma
ferramenta que permite desenhar sólidos tridimensionalmente, permitindo posteriormente
calcular o volume dos mesmos. A ferramenta utilizada foi o programa AutoCad, versão
2004.
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Figura 2. 4 – Desenho do Balão em AutoCad
Antes de se começar a utilizar o programa AutoCad, tiraram-se as medidas necessárias
para a realização do desenho do balão, de modo a ficar o mais idêntico possível ao
modelo original. Seguidamente, desenhou-se o balão (Figura 2.4) e por último cálculouse o volume, recorrendo a uma das muitas funcionalidades do programa (Figura 2.5).
Figura 2. 5 - Calculo do volume do Balão
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Como se pode observar o volume do balão anda na ordem dos 119,7 dm ³.
De notar que o cálculo do peso máximo que o balão suporta foi efectuado com base nas
características do composto químico utilizado para encher o balão. O composto químico
utilizado foi o elemento He (Hélio).
O hélio é obtido unicamente a partir de algumas explorações de gás natural, pelo que o
seu custo é elevado. As principais fontes encontram-se nos EUA, Rússia e Argélia.
O hélio é um gás nobre, incolor, inodoro, inerte e com uma densidade inferior à do ar, o
que lhe confere o poder de elevação.
Por cada metro cúbico de hélio irá obter-se um poder de elevação de aproximadamente
1Kg em condições normais, sendo de levar em conta que a variação das condições
atmosféricas implica alterações. Como variáveis atmosféricas que afectam as
propriedades do balão tem-se a humidade relativa, a temperatura e a pressão.
Condições que favoreçam um aumento do volume de Hélio no interior do Balão podem
ocasionar uma sobrepressão que pode colocar em causa a integridade dos utilizadores.
Também a situação contraria pode originar situações de risco.
Alem do hélio também se pode utilizar Hidrogénio, mas dado que se trata de um gás
inflamável, a sua utilização neste tipo de aplicações é normalmente não aconselhada,
carecendo o seu uso de um parecer especializado.
Como foi descrito, o hélio puro é muito raro, sendo o seu preço em Portugal muito
elevado. O seu uso é muito restrito. Apenas as estações meteorológicas o adquirem para
uso.
Não havendo assim a possibilidade de comprar hélio puro, a opção tomada foi adquirir
hélio a uma empresa que vende outros compostos gasosos, tais como azoto e o
hidrogénio. Como tal alugou-se uma botija de hélio de modo a poder encher o balão
sempre que necessário.
Através de informações dadas por um empregado da empresa, a botija adquirida contém
cerca de 70% de hélio, sendo os outros 30% compostos mais densos.
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Através de uma regra de três simples, cálculou-se o peso real suportado pelo balão.
119.7 g ----------- 100%
X ----------- 65%
X = 78 g
Finalmente chegou-se à conclusão que o balão suporta aproximadamente 78 gramas.
Subtraindo 40 gramas (cockpit, motores e estrutura que suporta os mesmos) fica-se com
38 gramas, para suportar o hardware a implementar.
2.2.3.3
Estabilidade do Balão
Por estabilidade do balão entende-se um determinado intervalo de tempo onde o balão se
encontra parado. Essa estabilidade vai ser garantida pela anulação de duas forças com
sentidos opostos (Figura 2.6). a força gravítica (P) e a impulsão (I). Essa força é garantida
pela quantidade de hélio que se encontra dentro do balão.
Figura 2. 6 - Forças que actuam sobre o Dirigível
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Testes efectuados
Foram feitos alguns testes referentes à estabilidade do Dirigível em duas situações
distintas; em ambas é necessário adicionar peso para que o balão fique parado. A
primeira situação diz respeito ao balão, no seu estado original e na segunda situação são
colocados fios eléctricos (que conduzirão sinais eléctricos) como se pode ver na Figura
2.7.
Outro dos testes realizados pretende avaliar a influência causada pelos fios no balão.
Figura 2. 7 - Balão com fios
2.2.3.3.2
Resultados
No primeiro teste sentiu-se uma grande dificuldade em estabilizar o balão, devido a que
este é suficientemente sensível ao acrescento de algumas miligramas. Adicionalmente o
balão tem fugas de hélio com o passar do tempo, através das zonas de junção (zonas de
soldadura do foil). Essas fugas alteram substancialmente as características do balão, o que
torna difícil o estabilizar do balão.
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Para o segundo caso a situação é diferente, pois o arco formado pelos fios vai fazer com
que haja um auto- ajuste entre o peso do balão e a sua impulsão, que vai fazer com que
haja estabilidade num determinado ponto denominado ponto de estabilidade ou PE.
1
0,9
0,8
0,7
0,6
Amostra 1
0,5
Amostra 2
Amostra 3
0,4
0,3
0,2
0,1
521
501
481
461
441
421
401
381
361
341
321
301
281
261
241
221
201
181
161
141
121
81
101
61
41
1
21
0
Figura 2. 8 – Gráfico da altitude do balão com fios lançado abaixo do PE
1,1
1
0,9
0,8
0,7
Amostra 1
Amostra 2
Amostra 3
0,6
0,5
0,4
0,3
0,2
0,1
426
409
392
375
358
341
324
307
290
273
256
239
222
205
188
171
154
137
120
103
86
69
52
35
1
18
0
Figura 2. 9 – Gráfico da altitude do balão com fios lançado acima do PE
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Como se pode analisar pelas figuras 2.8 e 2.9, o balão com fios vai andar em torno de PE.
Outra conclusão é que o balão não vai exercer a mesma força quando estiver acima do
ponto de estabilidade ou abaixo, devido à influência dos fios.
Quando o balão está acima do ponto de estabilidade o gráfico apresenta um
comportamento quase estável, ou seja, vai ter um tempo de estabelecimento rápido; já
quando o balão estiver abaixo do ponto de estabilidade, o balão vai ter um
comportamento muito mais instável e um menor tempo de estabelecimento.
As conclusões que se podem tirar é que os fios no balão vão interferir bastante com o
balão, seja devido ao seu peso ou devido à sua rigidez. O fio é assim um factor de
complexidade no balão.
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Hardware Desenvolvido
3.1. Controlo de Motores
Entende- se como controlo dos motores o controlo da velocidade e sentido de rotação dos
mesmos.
3.1.1 PWM
Para controlar a velocidade de rotação dos motores será necessário controlar a tensão que
se aplica aos terminais dos mesmos. A velocidade de rotação será imposta através da
utilização de PWMs (Modulação em largura de Pulso). Este tipo de modulação tem por
base manter a amplitude do pulso variando a sua largura, mas mantendo a frequência
permitindo assim que a velocidade de rotação dos motores varie segundo o pulso que é
transmitido aos mesmos. Basicamente o que está a ser feito é ligar e desligar a
alimentação do motor, permitindo assim que esta varie entre 0 e o seu máximo.
Na experiência referente ao Controlo da Altitude os PWMs foram implementados através
de um contador e um comparador de 4 bits (Figura 3.1). De notar que também se podia
ter implementado os PWMs recorrendo ao microcontrolador, através dos contadores. Mas
como são necessários 3 PWMs e o microcontrolador (89C51) só tem 2 contadores, foi
posta de parte esta hipótese. No caso do trabalho referente ao Robô Minimalista foi
utilizado um circuito integrado já com a função de PWM (GL494), em que as
características se encontram em anexo.
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Figura 3. 1 - Circuito PWM
3.1.2 Controlo do sentido de rotação
Para controlo do sentido de rotação dos motores do balão vai utilizar-se um
descodificador de 1 bit (Figura 3.2), cuja implementação é feita através de duas portas
AND e uma NOT.
Figura 3. 2 - Circuito descodificador
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3.1.3 Ponte em H
Uma solução para comandar os motores a partir de sinais lógicas (de baixa energia) é a
utilização de um transístor, mas esta solução não permite mudar o sentido de rotação dos
motores.
A solução encontrada foi a utilização de uma ponte H. Esta montagem permite que se
possa mudar o sentido de rotação. Outra vantagem é que permite separar a tensão de
alimentação do circuito com a tensão de alimentação dos motores. Podia-se ter
implementado o circuito da Figura 3.3 mas optou-se por utilizar um circuito integrado
com as mesmas características (L293E) cujas características podem-se ver nos anexos .
Figura 3. 3 - Ponte H
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3.1.4 CPLD
Outro dos problemas encontrados na implementação da lógica de controlo dos motores
foi o elevado número de bits necessários para o controlo dos mesmos, já que, para cada
motor seriam necessários 5 bits (4 bits de controlo de velocidade e 1 bit de controlo do
sentido de rotação), ter-se-ia um total de 15 bits. Como tal, para resolver este problema
optou-se por uma implementação de uma interface série através da utilização de um
registo de 15 bits. Tendo assim necessidade da utilização de apenas 2 bits: 1 bit para os
dados e outro bit (Clk) para o controlo dos mesmos.
Para que a implementação de todo o circuito de controlo não se tornasse muito extensa no
que diz respeito ao número de integrados, optou-se por utilizar um circuito de lógica
programável, nomeadamente uma CPLD (XC9536PC44).
3.2 SENSORES
Os sensores são os elementos chave de qualquer sistema de robótica. Estes providenciam
o único método de medida das condições envolventes do meio. Os sensores podem medir
vários tipos de informação, tal como a intensidade da luz, a temperatura, a pressão, etc.
A informação mais importante para um sistema de robótica móvel é a sua proximidade
em relação aos objectos. Esta informação é vital para o sistema cumprir as tarefas de
navegação evitando os objectos.
3.2.1 SENSOR DE MEDIÇÃO DE DISTÂNCIAS
O sensor de distância que se utilizou foi o sensor de infravermelhos. Os critérios que
levaram à escolha deste sensor foram as distâncias que este podia medir. Este mede
distancias que vão desde 20cm a 150cm. Outro dos critérios que favoreceram a escolha
do sensor foi o seu baixo consumo de corrente e a pouca influência à cor dos objectos.
O sensor utilizado para a medição de distâncias foi o sensor da marca SHARP com o
modelo GP2Y0A02YK (Figura 3.4).
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Figura 3. 4 - Sensor de infravermelhos
A técnica de medição utilizada pelo sensor GP2. é denominada por triangulação. Neste
processo, uma luz é emitida pelo sensor, sendo reflectida pelo seu alvo para por ultimo
ser recebida novamente pelo sensor. Existem três pontos envolvidos, o emissor, o ponto
de reflexão e o receptor. A disposição dos pontos formam um triângulo, daí o seu nome.
3.2.1.1. Caracterização do Sensor
Tensão (Volts)
Distância do Sensor a um objecto
3
2,75
2,5
2,25
2
1,75
1,5
1,25
1
0,75
0,5
0,25
0
Folha branca
Caderno cinzento
Caderno vermelho
Plastico preto
2
6
10
14
18
30
50
70
90
110 130 150
Distância (cm)
Figura 3. 5 - Caracterização do sensor relativamente a objectos de diferentes cores
Como se pode ver pela análise da Figura 3.5 o sensor vai ter pouca influência à cor. Um
dos problemas deste sensor é que a partir de uma determinada distância o sensor repetirá
os valores de outras distâncias, ou seja, vai ter dois valores iguais de saída para distâncias
diferentes. Logo, optou-se não utilizar o sensor para distâncias inferiores a 20 cm.
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3.3. ADCs
Hoje em dia exige-se frequentemente que os dados extraídos num sistema físico sejam
convertidos na forma digital. Normalmente estes dados aparecem sob a forma analógica
de natureza eléctrica. Surge portanto a necessidade de um dispositivo que converta a
informação analógica na forma digital. Foram inventados vários dispositivos deste tipo.
Os 4 sistemas mais conhecidos são:
1 - ADC de contagem
2 - ADC de aproximações sucessivas
3 - ADC de comparadores em paralelo ou Flash
4 - ADC de dupla rampa.
O ADC é um componente com uma entrada analógica e uma saída digital de n bits.
Em relação ao Interface pode-se ter ADCs Série ou Paralelo (Figura 3.6).
Figura 3. 6 – Tipo de ADCs quanto ao Interface
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O ADC apresenta um número binário na saída que corresponde ao valor da tensão de
entrada (Figura 3.7).
Figura 3. 7 – Resposta Característica do ADC
Tem-se que:
•
O número de bits na saída, n, denomina-se número de bits do ADC.
•
O número de intervalos de quantificação é
•
A resolução do conversor, R, é definida da seguinte forma:
R=
2n
AMax
2n
AMAX − Gama de tensão de entrada do ADC
n – Número de bits do ADC
O último parâmetro associado aos ADCs é a sua velocidade de operação. Devido a não
ser exigida uma grande velocidade de operação, nem uma resolução muito elevada, no
optou-se por utilizar o MAX1112 que tem as seguintes características:
•
ADC de Aproximações Sucessivas;
•
Número de bits = 8;
•
Interface Série;
•
Número de Canais = 8;
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Resolução do ADC utilizado:
R=
4.096
= 0,016V
28
De notar que se optou por um ADC de interface série, apenas com o intuito de se utilizar
menos linhas de dados para realizar a interface. A escolha do ADC de 8 canais assentou
em possíveis melhorias que se possam fazer ao projecto, nomeadamente um acréscimo de
sensores.
O ADC utilizado requer 4 pinos para Controlo e um pino para Dados.
Para realizar a interface entre o ADC e o microcontrolador definiram-se 5 pinos de um
dos portos do Microcontrolador para realizar o controlo. Como pinos de controlo do ADC
tem-se o CS, SCLK, DIN, SSTRB. O pino de Dados é designado por DOUT.
Na Figura 3.8 pode ver-se o diagrama temporal de um ciclo de conversão do ADC.
Figura 3. 8 – Ciclo de conversão do ADC (MAX1112)
O pino DIN é utilizado para programar o ADC.
Este pino tem as seguintes funções:
•
permite escolher se a tensão de referência é interna ou externa;
•
o canal do ADC que se pretende ler;
•
o tipo de conversão (unipolar ou bipolar);
•
o tipo de Clock (interno ou externo).
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3.4. FOTOTRANSÍSTORES
Figura 3. 9 – Fototransistor
De seguida irão ser descritas algumas das características principais dos fototransístores:
•
Resposta Espectral
A saída de um fototransistor depende do comprimento de onda da luz incidente. Estes
componentes respondem a uma luz que se encontre num intervalo de comprimento de
onda caracterizado pelos UVs (ultravioletas), passando pela luz visível, acabando nos IR
(infravermelhos).
Figura 3. 10 - Resposta do fototransistor face às diferentes cores
Como se pode observar na Figura 3.10, os fototransístores tanto respondem a luz
fluorescente como a luz incandescente, mas o seu comportamento é tanto mais perfeito
quando é estimulado por uma luz IR (infravermelha).
•
Sensibilidade
Para um dado nível de iluminação de uma fonte de luz, a saída de um fototransístor é
definida pela área da junção colector-base e pelo ganho em corrente DC do transístor.
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A junção colector-base do fototransístor funciona como um foto-díodo, que cria uma
foto-corrente que é alimentada na secção da base do transístor. Esta corrente (Ip) depois é
amplificada pelo ganho de corrente do transístor. No caso onde não é aplicada
externamente nenhuma corrente na base, tem- se:
IC = hFE (IP)
onde:
IC – Corrente no colector
hFE – Ganho em corrente dc
IP – Foto-corrente
A Figura seguinte ilustra o circuito Prático utilizado para a implementação do
Fototransistor:
Figura 3. 11 - Circuito implementado para o Fototransistor
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3.5. LDRs
Figura 3. 12 - LDR
Como o próprio nome indica, as LDRs (Light dependent resistors) são resistências
variáveis com a luz visível.
Como se pode observar na Figura 3.12, a LDR é composto por uma linha em zigzag de
cor castanha. De acordo com o nível de luz que incide nessa linha, a resistência aumenta
ou decresce. A resistência das LDRs tem o seu valor máximo para situações em que esta
se encontra no escuro e tem o seu valor mínimo para ocasiões de muita claridade. A
situação descrita caracteriza uma LDR denominada LDR de coeficiente negativo. Caso o
comportamento seja inverso a LDR denomina-se de coeficiente positivo.
De modo a usar este dispositivo num circuito simples, inicialmente começou-se por usar
um multímetro de modo a medir a corrente que circula no LDR. No entanto, a medição
de corrente não se tornou muito útil. Como tal, colocou-se uma resistência em série com
a LDR, e mediu-se a tensão na LDR. Com esta montagem realizou-se um divisor de
tensão, sendo a tensão no LDR proporcional à corrente. As figuras que se seguem
mostram o conceito descrito.
Figura 3. 13 - Ligação do LDR
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Como se pode observar na Figura 3.13, a corrente é proporcional à resistência do LDR.
Figura 3. 14 - Circuito implementado para medir a tensão no LDR
Sendo assim, tem- se que:
VLDR =
RLDR
V
RLDR + R
Tendo em conta que R utilizado anda na ordem das centenas de Ω e o valor máximo da
resistência no LDR é da ordem das dezenas de MΩ, tem-se
RLDR _ MAX
RLDR _ MAX + R
≈ 1 =>
V LDR ≈ V .
De acordo com a análise feita ao circuito da Figura 3.14, tem-se que para zonas de muita
claridade a tensão V LDR é máxima , sendo praticamente nula para zonas escuras.
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3.6. ALIMENTAÇÃO
Figura 3. 15 - Bateria (Idêntica à utilizada)
Não foram realizados testes práticos no que diz respeito a possíveis baterias que
satisfizessem as necessidades do sistema. No entanto, foi feita uma consulta que se
baseou nos vários tipos de baterias existentes no mercado e que assentou nas relações
entre os seguintes termos:
•
Energia fornecida (mAh)
•
Tensão fornecida (Volts)
•
Peso da bateria (gramas)
As baterias NiMH e as baterias NiCd apresentam algumas semelhanças. No entanto as
primeiras apresentam algumas vantagens. As vantagens são a energia fornecida e o tempo
de vida. No entanto ambas apresentam uma desvantagem que diz respeito à relação peso/
energia. Sendo a tensão mínima necessária para o sistema funcionar aproximadamente
3,8V, ir-se-ia necessitar logicamente de uma bateria com um valor maior ou igual a este.
O problema surge em adquirir uma bateria com esta tensão, com uma capacidade que
satisfaça as necessidades do sistema e com um peso máximo de 20g.
Devido ao baixo peso permitido para a alimentação recorreu-se ao uso de uma bateria de
Li-Ion que apresenta as características pretendidas e que foi fácil adquirir
A bateria utilizada é uma bateria de um telemóvel com as seguintes características:
− Tensão Nominal = 3,6V;
− Capacidade na ordem dos 820mAh;
− Peso = 18g.
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Experiências
4.1. Controlo de Altitude
A experiência consiste em estabilizar o balão a uma dada distância do tecto (PP),
utilizando um sensor de distancia colocado no topo do balão e apontando para o tecto. A
experiência reporta resultados com um controlador proporcional (P) e um controlador
proporcional-derivativo (PD). Esta experiência começa com uma apresentação teórica
deste tipo de controlo.
4.1.1 Controlo em malha fechada
Um controlador em malha fechada e um dispositivo que realiza determinados cálculos de
modo a conduzir o sistema para uma situação desejada. Uma medida do afastamento
entre a saída actual (r) do sistema e a situação desejada (d) e avaliada através de e=r-d,
que se denomina o erro da saída. O controlador avalia então o valor a aplicar ao sistema
(neste caso os motores) de modo a que este estabilize na posição desejada. A saída do
controlador denomina-se acção de controlo.
Existem três tipos de acções de controlo:
− Acção proporcional
− Acção integral
− Acção derivativa
Com a combinação destas acções podemos gerar um sinal de controlo, que se pode
chamar por controlo PID, que é genericamente representado por :
t
1
de(t )
u (t ) = Kpe(t ) + ∫ e(τ )dτ + Td
Ti 0
dt
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4.1.1.1. Acção proporcional
Na acção proporcional o sinal de controlo vai ser proporcional à amplitude do valor do
erro.
u (t ) = Kp × e(t )
e(t ) = d − r (t )
,onde,
Kp – ganho constante
e(t) – diferença entre a distância final e a distância actual
d – distância pretendida entre o sensor e a parede que se deve encontrar no final deste
controlo
Ps(t) – distância medida entre o sensor e o tecto
Esta acção consiste essencialmente num amplificador com ganho ajustável.
Sensor
Sentido do controlo u(t)<0
e(t) < 0
PE
e(t) > 0
Sentido do controlo u(t) > 0
Sensor
Figura 4. 1 - Controlo proporcional
Note-se que, quanto maior o ganho Kp menor o erro em regime permanente, isto é,
melhor a precisão do sistema em malha fechada. Este erro pode ser diminuído com o
aumento do ganho, entretanto nunca conseguiremos anular completamente o erro. Por
outro lado, quanto maior o ganho, mais oscilatório tende a ficar o comportamento
transitório do sistema em malha fechada. Na maioria dos processos físicos, o aumento
excessivo do ganho proporcional pode levar o sistema a instabilidade.
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4.1.1.2. Acção Integral
Na acção Integral o valor de controlo depende do integral do erro.
1
e(t )dt
Ti ∫
Ti (tempo integral) é o tempo necessário para que a contribuição da acção
integral iguale a da acção proporcional, onde :
u (t ) =
Ki =
1
Ti
A acção integral tem assim uma função "armazenadora de energia". A acção integral está
então directamente ligada à melhoria da precisão do sistema.
Se, por um lado, a acção integral elimina o erro estacionário, por outro, aumenta o tempo
de estabelecimento e piora a estabilidade relativa, o que usualmente é indesejável.
Como consequência, o ganho da acção proporcional deve ser reduzido, sempre que esta
esteja combinada com a acção integral.
Figura 4. 2 - Controlo Integral
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4.1.1.3. Acção Derivativa
Na acção Derivativa o sinal de controlo depende da taxa de variação do erro.
u (t ) = Td
de(t )
dt
Td (tempo derivativo) é o período de tempo antecipado pela acção relativamente à acção
proporcional.
Este tipo de controlo tem justamente a função de "antecipar" a acção de controlo a fim de
o processo reaja mais rapidamente
A adição do modo derivativo ao modo proporcional resulta num controlador altamente
sensível, uma vez que o primeiro, ao responder a uma taxa de variação do erro,
permite correcções antes deste ser elevado. Não obstante o modo derivativo não afectar
directamente o erro estacionário, adiciona amortecimento ao sistema (melhora a
estabilidade) e assim permite o uso de valores de Kp mais elevados, o que implica um
menor erro estacionário. Um inconveniente deste modo é o de acentuar o ruído de alta
frequência.
Figura 4. 3 - Controlo Derivativo
Logo a forma final do PID será dada por:
de(t ) 

u (t ) =  Kp × e(t ) + Ki × ∫ (e(t )dt ) + Kd ×

dt 

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4.1.2 Software de Controlo
De modo a realizar o controlo do dirigível, foi desenvolvida uma aplicação em Visual
Basic, cujo código é apresentado em ANEXOS (ANEXOS 1).
Esta aplicação é constituída apenas por uma janela (Figura xx) que apresenta as seguintes
funções:
•
Iniciar e terminar o processo de controlo;
•
Visualizar os valores do sensor;
•
Visualizar a velocidade do motor;
•
Ajustar os ganhos (Kp, Kd e Ki).
Figura 4. 4 – Janela do Software realizado
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4.1.3 Resultados
Os testes efectuados para cada controlador vão ter como ponto de referência o ponto de
estabilidade do balão. O primeiro teste consiste em variar o ganho da constante
proporcional anular os restantes ganhos, ou seja, implementa-se, controlo proporcional
(P).
0,9
0,8
0,7
0,6
0,5
Amostra 1
Amostra 2
0,4
0,3
0,2
0,1
507
485
463
441
419
397
375
353
331
309
287
265
243
221
199
177
155
133
89
111
67
45
1
23
0
Figura 4. 5 - Controlo proporcional com Kp = 5
0,9
0,8
0,7
0,6
0,5
Amostra 1
Amostra 2
0,4
0,3
0,2
0,1
501
481
461
441
421
401
381
361
341
321
301
281
261
241
221
201
181
161
141
121
101
81
61
41
1
21
0
Figura 4. 6 - Controlo proporcional com Kp = 10
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1
0,9
0,8
0,7
0,6
Amostra 1
Amostra 2
0,5
0,4
0,3
0,2
0,1
553
530
507
484
461
438
415
392
369
346
323
300
277
254
231
208
185
162
139
93
116
70
47
1
24
0
Figura 4. 7 - Controlo proporcional com Kp = 15
1,1
1
0,9
0,8
0,7
0,6
Amostra 1
0,5
Amostra 2
0,4
0,3
0,2
0,1
529
507
485
463
441
419
397
375
353
331
309
287
265
243
221
199
177
155
133
111
89
67
45
1
23
0
Figura 4. 8 - - Controlo proporcional com Kp = 20
Analisando os gráficos, verifica-se que com o aumento de Kp a sobreelevação e o tempo
de estabelecimento aumenta, sendo que quanto mais aumentamos Kp mais o sistema
tende a ficar instável. Por sua vez quanto menor for Kp mais suave vai ser o nosso
controlador.
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Agora analisa-se o controlador do tipo PD (controlador proporcional derivativo)
1
0,9
0,8
0,7
0,6
Amostra 1
0,5
Amostra 2
0,4
0,3
0,2
0,1
298
287
276
265
254
243
232
221
210
199
188
177
166
155
144
133
122
111
89
100
78
67
56
45
34
23
1
12
0
Figura 4. 9 - Controlo Pd com Kd = 5
1
0 ,9
0 ,8
0 ,7
0 ,6
A m o s tr a 1
A m o s tr a 2
0 ,5
0 ,4
0 ,3
0 ,2
0 ,1
301
291
281
271
261
251
241
231
221
211
201
191
181
171
161
151
141
131
121
111
101
91
81
71
61
51
41
31
21
1
11
0
Figura 4. 10 - Controlo Pd com Kd = 7
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1
0,9
0,8
0,7
0,6
Amostra 1
0,5
Amostra 2
0,4
0,3
0,2
0,1
298
287
276
265
254
243
232
221
210
199
188
177
166
155
144
133
122
111
89
100
78
67
56
45
34
23
1
12
0
Figura 4. 11 - Controlo Pd com Kd = 9
Analisando os gráficos ,verifica-se que com o aumento de Kd a sobreelevação e o tempo
de estabelecimento vai aumentar.
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Por último, testa-se o controlador do tipo Pi (controlador proporcional integral).
1
0,9
0,8
0,7
0,6
Amostra 1
0,5
Amostra 2
0,4
0,3
0,2
0,1
276
265
254
243
232
221
210
199
188
177
166
155
144
133
122
111
89
100
78
67
56
45
34
23
12
1
0
Figura 4. 12 - Controlo Pi com Ki = 1
1
0,9
0,8
0,7
0,6
Amostra 1
0,5
Amostra 2
0,4
0,3
0,2
0,1
276
265
254
243
232
221
210
199
188
177
166
155
144
133
122
111
100
89
78
67
56
45
34
23
1
12
0
Figura 4. 13 - Controlo Pi com Ki = 2
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1 ,2
1
0 ,8
A m o s tr a 1
A m o s tr a 2
0 ,6
0 ,4
0 ,2
281
271
261
251
241
231
221
211
201
191
181
171
161
151
141
131
121
111
91
101
81
71
61
51
41
31
21
1
11
0
Figura 4. 14 - Controlo Pi com Ki = 3
Como se pode observar pelas Figuras 4.12, 4.13, 4.14, este controlador aumenta a
instabilidade do nosso sistema, pois quando se aumenta o ganho o sistema tende a ficar
instável.
Fazendo agora a comparação do controlador P com o PI e PD o que se verifica é que para
o controlador PI em relação ao P é que o PI vai ter uma sobreelevação maior e uma
frequência de oscilação também superior mas um tempo de estabelecimento inferior, em
relação aos P com o PD não se conseguiu concluir muito devida as várias interferências
que surgiram, onde um dos problemas é a variação do teste do ponto de estabilidade,
devido a fugas de hélio do balão, pois no final de uma hora a referencia variava bastante,
como se pode ver nas figuras 4.15 e Figura 4.16, onde na Figura 4.15 o valor médio da
referencia vai ser de ±0.72V e em 4.16 é de 0.53V
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1
0 ,9
0 ,8
0 ,7
0 ,6
A m o s tra 1
A m o s tra 2
0 ,5
0 ,4
0 ,3
0 ,2
0 ,1
323
309
295
281
267
253
239
225
211
197
183
169
155
141
127
99
113
85
71
57
43
29
15
1
0
Figura 4. 15 – Gráfico de altitude do balão com fios
0,7
0,6
0,5
0,4
Amostra 1
Amostra 2
0,3
0,2
0,1
313
300
287
274
261
248
235
222
209
196
183
170
157
144
131
118
105
92
79
66
53
40
27
14
1
0
Figura 4. 16 – Gráfico de altitude do balão com fios passado uma hora
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4.2
Projecto Final de Curso
Robot Minimalista
O Robot Minimalista é caracterizado por ter ligações directas dos sensores aos motores.
A atribuição do nome ao Robot assentou precisamente na sua simplicidade.
A experiência consiste em projectar um Robot que tem a capacidade de se deslocar de
zonas de maior claridade para zonas de menor claridade (escuro). Para detectar a variação
do nível de luz foram utilizados duas LDRs. As LDRs encontram-se acopladas na parte
da frente do Cockpit do Dirigível. De notar que as LDRs foram dispostas no cockpit do
dirigível formando um ângulo de 45º em relação a um eixo longitudinal, como se pode
observar na Figura 4.17. A disposição escolhida para as LDRs foi implementada deste
modo com o intuito de apresentar um campo de visão o mais alargado possível,
relativamente ao seu sentido de deslocamento.
Figura 4. 17 – Cockpit do Dirigível com os LDRs e o Fototransistor acoplados
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O LDR do lado direito do cockpit do Dirigível encontra-se ligado ao motor do lado
direito do dirigível e vice versa. No caso da ligação dos motores às LDRs fosse cruzada
(o motor do lado direito fosse ligado ao LDR do lado esquerdo e vice-versa) o dirigível
em vez de se afastar das zonas de claridade, iria dirigir-se para as zonas de maior
claridade.
O PWM utilizado para o controlo da velocidade dos motores é gerado por um circuito
integrado (referido anteriormente) que tem capacidade de controlar o duty cycle (largura
do pulso) dos 50% (Figura 4.18) aos 100%. Sendo assim considerou-se que quando as
LDRs estão a detectar um nível de luminosidade inferior ao nível de referencia, ambos os
motores se encontram a funcionar a uma dada velocidade. Sendo assim, tem-se que o
balão está sempre em movimento.
Figura 4. 18 – Sinal à saída do circuito do PWM para um nível de luminosidade inferior ao valor de
referencia
No caso da LDR do lado direito (*), ao detectar um nível de luminosidade superior ao
valor de luminosidade de referência, a tensão à entrada do PWM aumentará, o que
provocará um aumento da largura do pulso à saída, incrementando assim a velocidade do
motor do lado direito (Figura 4.19).
(* )Nota : Quando se fala do lado direito do cokpit do Dirigível, está a ser referido o lado esquerdo das
Figuras 4.17 e 4.19, visto a imagem ser de uma perspectiva da vista de baixo do cokpit.
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Ao aumentar a velocidade do motor do lado direito o dirigível irá começar a virar para o
lado esquerdo afastando-se assim da zona de maior luminosidade (Figura 4.19).
Pelo mesmo processo, um aumento do nível de luminosidade na outra LDR faz com que
o balão curve para a direita.
Figura 4. 19 – Foco de luz a incidir sobre o LDR do lado direito do cokpit do balão
Para além das LDRs foi também utilizado um fototransístor que tem como função
controlar o motor que controla a altitude do dirigível.
Como o balão é um sistema estável por não necessitar da actuação de motores para se
manter no ar a uma dada altitude, implica que o motor de controlo de altitude, ao
contrário dos outros motores não se encontra sempre a funcionar.
Não se encontrando sempre a funcionar, a utilização do motor de altitude é necessária
quando se pretende que o dirigível aumente a sua altitude ou no caso de este se encontrar
a voar à muito tempo, é necessário compensar a perda de altitude que ocorre devido às
fugas de hélio. De modo a colocar o motor a funcionar incide-se uma luz sobre o
fototransístor através de uma lanterna vulgar (Figura 4.20). A intensidade da luz no
fototransístor vai determinar se a polarização da base é suficiente para o fototransistor
entrar em condução provocando o funcionamento do motor.
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Figura 4. 20 – Foco de luz a incidir sobre o Fototransistor
Na tabela seguinte (Tabela 4.1) é possível observar o peso de todos os componentes que
foram utilizados para implementar o Robot Minimalista. Como se pode observar, a
electrónica constituinte e a alimentação fazem um total de aproximadamente 34 gramas.
Que somado ao peso do balão com cockpit é inferior a 78 gramas.
Material
Ics
Resistências
Potenciómetros
LDRs
Fototransístores
Díodos
Condensadores
Conectores
Placa PCB
TOTAL1 = Electrónica + Placa PCB
Alimentação (Bateria)
TOTAL2 = TOTAL1 + Alimentação
Cockpit
TOTAL
Quantidade
3X
5X
2X
2X
1X
1X
2X
12X
1X
1X
1X
Peso (Unidade)
0.99 g
0,16 g
0,39 g
0.17 g
0.19 g
0,20 g
0,14 g
0,07 g
5,40 g
20 g
40 g
Peso
3,97 g
0,80 g
0,78 g
0,34 g
0,19 g
0,20 g
0,28 g
0,84 g
7,00 g
14,50 g
19 g
33,5 g
42 g
75,5 g
Tabela 4. 1 – Peso de todos os componentes utilizados no Robot Minimalista
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5.
Conclusões e Perspectivas de Trabalho Futuro
5.1
Conclusões
Este projecto contribuiu para a aquisição de conhecimentos relativos ao funcionamento
de diversos sensores ópticos que existem no mercado. O conhecimento alargou-se aos
sensores que foram utilizados nos trabalhos, nomeadamente as LDRs, os fototransístores
e os sensores de infravermelhos de medição de distâncias.
Tomou-se também um conhecimento mais alargado do funcionamento dos motores de
corrente contínua no que diz respeito ao seu controlo e interface com um controlador.
De referir o importante desenvolvimento de conhecimentos relativos à área de controlo
de sistemas, mais especificamente a implementação de controladores P, PD e PI que
foram vocacionados no nosso caso para o controlo de um balão a hélio.
De salientar algumas semelhanças entre o nosso projecto e um projecto de licenciatura de
um aluno Suíço, denominado “Evolutionary Blimp”. O seu objectivo assentou na
construção de um dirigível autónomo que tivesse a capacidade de circular livremente
num local fechado. O dirigível é constituído por 3 motores, 6 detectores de obstáculos e 2
câmaras de imagem. Este trabalho teve como resultados a obtenção de um Dirigível que
tem a capacidade de se deslocar num local fechado desviando-se de objectos.
Como se observou, em termos genéricos, o objectivo do trabalho do aluno Suíço é
idêntico ao nosso. As diferenças assentam no controlador implementado.
Há que referir que implementar um controlador do tipo do “Evolutionary Blimp” torna-se
mais simples comparando com o controlador implementado no nosso trabalho. De notar
que a principal dificuldade encontrada na utilização de dirigíveis é o seu ponto de
estabilidade. Visto o “Evolutionary Blimp” se encontrar permanentemente em deslocação
não se coloca o problema da estabilidade do balão. Ou seja, é mais fácil controlar os
movimentos de um dirigível em movimento do que controlar a ausência de movimentos.
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Projecto Final de Curso
Futuros desenvolvimentos
O trabalho descrito neste projecto, abre, no entender dos autores, diversas perspectivas no
que diz respeito à realização do projecto, de acordo com os requisitos que eram propostos
inicialmente, tal como a introdução de possíveis módulos.
Para a realização dos requisitos iniciais do projecto, teria inicialmente que conceber-se
um balão que suportasse aproximadamente o dobro do peso suportado pelo balão
utilizado.
Um desenvolvimento futuro poderia passar pela implementação de uma câmara digital
que desempenhasse funções de vigilância. Outra das implementações passaria pela
introdução de um módulo RF ou de um módulo Bluetooth. Esses módulos iriam
favorecer o sistema na medida que se poderia utilizar electrónica fora do dirigível. Isso
permitiria que o peso total do balão não aumentasse com o aumento da complexidade do
controlador. Este seria implementado num PC, com todas as facilidades que daí adviriam.
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Referências Bibliográficas
[1] Sedra Smith, “Microelectronic Circuits”, Fourth Edition, Oxford, 1998
[2] Steven Holzner, “Visual Basic 6 Black Book”, The Coriolis Group, 1998
[3] http://users.pandora.be/educypedia/electronics/sensorsoptical.htm
[4] http://www.draganfly.com
[5] http://www.gasin.pt/index.htm
[6] http://student.dee.uc.pt/~jalmeida/index_files/5.htm
[7] http://www.delet.ufrgs.br/~jmgomes/pid/Apostila/apostila/node24.html
[8] www.wizard.org_schem_motor.html
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ANEXOS
ANEXOS
i
ANEXOS
Índice
ANEXOS 1 ........................................................................................................................ iii
Listagem da Programação do Microcontrolador............................................................ iv
Listagem Da Programação Do Software de Controlo.................................................. xiii
ANEXOS 2 ....................................................................................................................... xx
Esquemático do 1º Trabalho ....................................................................................... xxi
Esquemático do 2º Trabalho ...................................................................................... xxiii
PCB do 1º Trabalho .................................................................................................... xxv
PCB do 2º Trabalho .................................................................................................. xxvii
Esquemático da lógica implementada na CPLD........................................................ xxix
ANEXOS 3 .................................................................................................................. xxxiv
GP2Y0A02YK.......................................................................................................... xxxv
L78xx ............................................................................................................................. xl
1N4001......................................................................................................................... lxv
GL494 .......................................................................................................................lxviii
L293 .......................................................................................................................... lxxvi
MAX1112 ............................................................................................................. cxxxvii
MAX233 ............................................................................................................... cxxxvii
HEF4047 ................................................................................................................. clxxiv
AT89C51......................................................................................................................cxc
XC9536PC44 ........................................................................................................... ccviii
ANEXOS 4 ..................................................................................................................ccxvii
Lista do material implementado............................................................................. ccxviii
ii
ANEXOS 1 – Listagem do Código de Programação
ANEXOS 1
iii
ANEXOS 1 – Listagem do Código de Programação
Listagem da
Programação do
Microcontrolador
iv
$mod51 ; identificador que permite o compilador do microcontrolador
; utilizado reconhecer as instruções deste
;
;
;
;
;
;
;
;
********************************
* ATRIBUIÇAO DOS BITS DE
*
*
CONTROLO DO DAC A
*
*
PORTOS DO MICRO
*
*
*
* P1.4 = Cont_bits
*
* P1.5 = I0
*
********************************
LETRAENVIA DATA 70H
VALOR0 DATA 71H
VALOR1 DATA 74H
VALOR2 DATA 75H
sentido0 data 76h
sentido1 data 77h
sentido2 data 78h
LIXO DATA 2FH
HIGH_BITS data 73H
escolha data 69h
ValorDAC DATA 32H
MOV R2,#00h
SETB P1.7
ORG 0000H
LJMP MAIN
; Espaco de memoria de programa alocado para o inicio do programa
; O salto para a main do programa
; memoria depois da instrução ORG, logo torna-se necessario fazer um
; salto para um procedimento que vá executar o programa.
;*********************************************************************************
;************PROCEDIMENTO QUE RECEBE VALORES DA PORTA SÉRIE**************
;*********************************************************************************
ORG 0023H
jb ri,label1
; salta a a label 1 quando receber algum caracter
reti
label1:
clr ri
; rotina para receber um caracter
mov a,sbuf
MOV LETRAENVIA,a
ACALL verifi
reti
;**********************************************************************
;************PROCEDIMENTO QUE RECEBE BITS DO ADC****************
;**********************************************************************
RECEBER_ADC:
; Inicialização do ADC
SETB P1.1 ; Colocar CS a HIGH
CLR P1.0
; Colocar SCLK a LOW
CLR P1.2
; Colocar DIN a LOW
CLR P1.1
; Colocar CS a LOW
NOP
SETB P1.2
; Colocar DIN a HIGH (BIT - START)
SETB P1.0
NOP
CLR P1.0
; Colocar SCLK a HIGH
; ///// CLOCK //////
; Colocar SCLK a LOW
MOV R3,#01H ; Registo auxiliar
MOV R1,#03H ; Contador dos CANAL que se pretende ler
LERCANAL:
MOV A,R2
; R2 Contem o valor do canal que se pretende ler
ANL A,R3
JZ ENVIAZERO
SETB P1.2
; Envio dos bits do CANAL (SEL2,SEL1,SEL0)
ENVIAR:
SETB P1.0
NOP
CLR P1.0
; Colocar SCLK a HIGH
; ///// CLOCK //////
; Colocar SCLK a LOW
MOV A,R3
RL A
; Roda para a esquerda o acum. para comparar o bit seguinte do CANAL
MOV R3,A
DEC R1
; Decrementa o contador de bits do CANAL
MOV A,R1
JZ FIMCANAL ; Ja foram enviados os 3 Bits de escolha do CANAL a ler
JMP LERCANAL ; Ainda nao foram enviados todos os bits referentes ao CANAL
ENVIAZERO:
CLR P1.2
JMP ENVIAR
FIMCANAL:
SETB P1.2
; Colocar DIN a HIGH para ENVIAR bits UNI,SGL,PD1 e PD0
MOV R4,#04H
CONTINUA:
SETB P1.0
; Colocar SCLK a HIGH
NOP
CLR P1.0
DEC R4
MOV A,R4
JZ RECEBE_VALOR
CANAL
JMP CONTINUA
; ///// CLOCK //////
; Colocar SCLK a LOW
; salta para RECEBE_VALOR para receber o valor que se encontra no
RECEBE_VALOR:
CLR P1.2
MOV R7,#07H
SETB P1.0
NOP
CLR P1.0
NOP
NOP
NOP
CONTINUALER:
SETB P1.0
NOP
CLR P1.0
; LEITURA DO VALOR PARA O MICRO
JB P1.3, ValorUM
JMP ValorZERO
ValorUM:
MOV A,ValorDAC
ADD A,#01H
RL A
MOV ValorDAC,A
MOV A,R7
DEC R7
MOV A,R7
JZ FIM_ADC
JMP CONTINUALER
ValorZERO:
MOV A,ValorDAC
ADD A,#00H
RL A
MOV ValorDAC,A
DEC R7
MOV A,R7
JZ FIM_ADC
JMP CONTINUALER
FIM_ADC:
JB P1.3, ValorUM_
JMP ValorZERO_
ValorUM_:
MOV A,ValorDAC
ADD A,#01H
MOV ValorDAC,A
JMP FIM_ADC_
ValorZERO_:
MOV A,ValorDAC
ADD A,#00H
MOV ValorDAC,A
FIM_ADC_:
MOV R6,#07H
RECEBER_ZEROS:
SETB P1.0
; Colocar SCLK a HIGH
NOP
; ///// CLOCK //////
CLR P1.0
; Colocar SCLK a LOW
DEC R6
MOV A,R6
JZ FINAL_ADC
JMP RECEBER_ZEROS
FINAL_ADC:
SETB P1.1
NOP
; Coloca CS a HIGH (Termina um Ciclo do ADC)
ret
ENVIAR_PORTA_SERIE:
clr ti
MOV A,ValorDAC
MOV SBUF,A
espera:
jnb ti,espera
RET
;******************************************************************************
;*****************PROCEDIMENTO QUE ENVIA BITS PARA O CPLD****************
;******************************************************************************
CONTINUAENVIO:
MOV A,LIXO
ANL A,B
JZ ZERO
SETB P1.5
JMP ENVIAR_BIT_pal
ZERO:
CLR P1.5
; Coloca o bit I0 com o valor lógico 0
; De seguida vai-se enviar o bit que se encontra em I0 para a CPLD
ENVIAR_BIT_pal:
clr p1.4
NOP
NOP
NOP
NOP
setb P1.4
DEC R5
; Decrementa o valor de R5, pois foi enviado um bit, ou mais um bit
MOV A,R5
; Move o valor de R5 para o acumulador
JZ TERMINOU_ENVIO_ ; Se acumulador for 0 salta para a label TERMINOU_ENVIO, o que
; significa que já foram enviados os 5 bits
MOV A,B
; Estas operações efectuam um conjunto de instruções que carregam
MOV B,#02H
; o Registo B com um valor que irá permitir detectar qual o nivel lógico
div AB
; do bit seguinet que se irá enviar para a CPLD
mov B,A
JMP CONTINUAENVIO ; Salta para a label CONTINUAENVIO para efectuar as operações que
; permitem detectar o nível lógico do bit seguinte a enviar.
TERMINOU_ENVIO_:
RET
; retorna ao programa e coloca o program counter com o valor da
; posição de memoria a seguir à qual se encontrava a chamada ao
; procedimento CONTINUAENVIO para continuar o programa
;******************************************************************************
;*****************PROCEDIMENTO QUE ENVIA BITS PARA A CPLD**********************
;******************************************************************************
; Para enviar bits para a cpld são necessárias um conjunto de instruções que passam
; pelo configuração dos pinos de controlo deste.
; Instruções estas que se encontram descritas a seguir.
ENVIAMOTOR:
MOV LIXO,VALOR2
MOV R5,#05d
para a CPLD
MOV B,#16d
Acall continuaenvio
; Registo que funciona como contador do número de bits a enviar
; O Registo B funciona como um registo auxiliar para calculos
MOV LIXO,VALOR1
MOV R5,#05d
para a CPLD
MOV B,#16d
Acall continuaenvio
MOV LIXO,VALOR0
MOV R5,#05d
para a CPLD
MOV B,#16d
Acall continuaenvio
; Registo que funciona como contador do número de bits a enviar
; O Registo B funciona como um registo auxiliar para calculos
; Registo que funciona como contador do número de bits a enviar
; O Registo B funciona como um registo auxiliar para calculos
ret
;******************************************************************************
;*******PROCEDIMENTO QUE VERIFICA QUAL O CONTROLO A FAZER*************
;******************************************************************************
verifi :
mov a, letraenvia
mov b, #10000000b
anl a,b
jz motor
mov a, letraenvia
mov b, #01111111b
anl a,b
mov R2,a
jmp main_
; verifica se é para enviar para o adc
mov a, letraenvia
mov b, #01100000b
anl a,b
cjne a,#96,motor1
mov a, letraenvia
mov b, #00011111b
anl a,b
mov Valor2,a
acall enviamotor
jmp final
; verifica se é para enviar informaçao para o motor 0
motor:
motor1:
cjne a,#64,motor0
mov a, letraenvia
mov b, #00011111b
anl a,b
mov Valor1,a
acall enviamotor
jmp final
; verifica se é para enviar informaçao para o motor 1
motor0:
cjne a,#32,motor1
mov a, letraenvia ; verifica se é para enviar informaçao para o motor 2
mov b, #00011111b
anl a,b
mov Valor0,a
acall enviamotor
final:
ret
;****************************************************************
;
INICIAR A PORTA SERIE
;****************************************************************
INIC_SERIE:
mov tmod,#20h
; 00100000
; B7 a B4 - pertencem ao timer 1 GATE C/T M1 M0 (0010)
; Gate = 0 (temporizador 1 est enable quando o bit de controlo Trx = 1)
; C/T
; M1 M0 - 10 (Modo de opera‡ao - Temporizador/Contador de 8 bits c/ autoReload.
; TH1 contem o valor de reload)
; B3 a B0 - pertencem ao timer 0 (B3 a B0 = 0) (0000)
mov th1,#0fah
; 0fd(253) - para BD - 19200 b/s
; 0fa(250) - BD = 4800 b/s
mov tcon,#00h
; Limpa o Registo TCON
mov scon,#50h
; 01010000
; 01010000 = SM0 SM1 SM2 REN TB RB8 TI RI
; 01 = SMO SM1 - Modo Funcionamento 1
; TB e RB8 = 0, So sao utilizados no modo 2 e 3
; TI e RI = 0, Sao activados no decorrer do programa
; caso se esteja a enviar ou a receber dados.
setb tr1
;setb ti
; ti=1 para ENVIAR bit pela porta série
mov ie,#90h
; EA=0 Disable todas as interrup‡äes e
; ES liga ou desliga as interrup‡oes da porta serie
mov pcon,#00h
; Pcon = 0, pois nao ‚ nessec rio duplicar a Baud Rate
; Limpa o registo PCON
ret
;**********************************************************************************
;*****SUB_PROCEDIMENTO MAIN (PROCEDIMENTO SECUNDÁRIO)********************
;**********************************************************************************
MAIN_:
MOV ValorDAC,#00H
ACALL RECEBER_ADC
ACALL ENVIAR_PORTA_SERIE
RET
;**********************************************************************************
;************PROCEDIMENTO MAIN (PROCEDIMENTO PRINCIPAL)********************
;**********************************************************************************
MAIN:
setb p1.4
ACALL INIC_SERIE
MOV VALOR0,#00H
MOV VALOR1,#00H
MOV VALOR2,#00H
ma:
jmp ma
END
; Label de Fim de programa
ANEXOS 1 – Listagem do Código de Programação
Listagem Da
Programação Do
Software de Controlo
xiii
Dim recebeu As Boolean
Dim buffer() As Byte
Dim inicio As Boolean
Dim espera As Boolean
Dim fimciclo As Boolean
Dim KP As Integer
Dim KD As Integer
Dim KI As Integer
Dim Veloc3 As Integer
Dim ValorSensor As Double
Dim Valorref As Double
Dim CP As Double
Dim CD As Double
Dim CI As Double
Private Sub Command1_Click()
Dim s As String
Dim i As Integer
Dim k As Integer
Dim j As Integer
Dim h As Integer
Dim auxvel As Integer
Dim MAXSENSORES As Integer
Dim MAXAMOSENSORES As Integer
Dim MAXAMOSTRAI As Integer
Dim AUXSENSORES(2) As Double
Dim ValorSensoractual As Double
Dim ValorSensorAnterior As Double
Dim DifSensor As Double
Dim SomaI As Double
Dim erro As Double
Dim amostra(8) As Double
Dim CPID As Double
Dim auxvel3 As Byte
MAXSENSORES = 0
MAXAMOSENSORES = 15
MAXAMOSTRAI = 4
ValorSensorAnterior = Valorref
' criar um ficheiro com o nome da hora minutos e secundos
s = "C:\dados\" & Hour(Now) & Minute(Now) & Second(Now) & ".txt"
Open (s) For Output Shared As #1
fimciclo = False
Do
If fimciclo Then
Exit Do
End If
' ciclo para receber os valores do sensor
For i = 0 To MAXSENSORES
AUXSENSORES(i) = 0
For k = 0 To MAXAMOSENSORES
MSComm1.Output = Chr(128)
Do
If recebeu Then
recebeu = False
AUXSENSORES(i) = (buffer(0) * 0.01606) + AUXSENSORES(i)
Exit Do
End If
DoEvents
Loop
Next k
' faz a media do valores dos sensores
ValorSensor = Round(AUXSENSORES(i) / MAXAMOSENSORES, 2)
' mostra o valor do sensor
Text8.Text = ValorSensor
Next i
' guarda o valor do sensor no ficheiro
Write #1, ValorSensor, Minute(Now), Second(Now)
'calcula a diferença entre o valor de referencia e o valor do sensor que da o erro
erro = Valorref - ValorSensor
' calcula a contribuição proporcional do sistema
CP = Round(erro * KP, 2)
' calcula a contribuição do controlador D
ValorSensoractual = ValorSensor
DifSensor = ValorSensorAnterior - ValorSensoractual
ValorSensorAnterior = ValorSensoractual
CD = DifSensor * KD
' calcula a contribuição do controlador I
If j > MAXAMOSTRAI Then
j=0
End If
amostra(j) = erro
j=j+1
For h = 0 To MAXAMOSTRAI
SomaI = amostra(h) + SomaI
Next h
CI = SomaI * KI
' mostra as diferentes contribuições ao controlador
Text5.Text = CP
Text6.Text = CD
Text7.Text = CI
CPID = CP + CI - CD
SomaI = 0
Text10.Text = Time
Text11.Text = CPID
If CPID > 8 Then
CPID = 8
End If
If CPID < -8 Then
CPID = -8
End If
If CPID = 0 Then
Veloc3 = 0
MSComm1.Output = Chr(96)
Else
' rotina de envio da velocidade a que os motores devem andar
If CPID > 0 Then
If Veloc3 = (Round(CPID, 0) + 7) Then
Else
MSComm1.Output = Chr(127)
Timer1.Interval = 1
Timer1.Enabled = True
espera = False
Do
If espera Then
Exit Do
End If
DoEvents
Loop
auxvel3 = CByte(Round(CPID))
MSComm1.Output = Chr(auxvel3 + 119)
Timer1.Interval = 1
Timer1.Enabled = True
espera = False
Do
If espera Then
Exit Do
End If
DoEvents
Loop
Veloc3 = auxvel3 + 7
End If
Else
If Veloc3 = (Round(CPID, 0) - 7) Then
Else
MSComm1.Output = Chr(111)
Timer1.Interval = 1
Timer1.Enabled = True
espera = False
Do
If espera Then
Exit Do
End If
DoEvents
Loop
auxvel3 = CByte(Round(-CPID))
MSComm1.Output = Chr(auxvel3 + 103)
Veloc3 = CPID - 7
Timer1.Interval = 1
Timer1.Enabled = True
espera = False
Do
If espera Then
Exit Do
End If
DoEvents
Loop
End If
End If
End If
Text4.Text = Veloc3
Timer1.Interval = 500
Timer1.Enabled = True
espera = False
Do
If espera Then
Exit Do
End If
DoEvents
Loop
DoEvents
Loop
MSComm1.Output = Chr(96)
Timer1.Interval = 5
Timer1.Enabled = True
espera = False
Do
If espera Then
Exit Do
End If
DoEvents
Loop
Text4.Text = 0
Close #1
End Sub
Private Sub Command2_Click()
' final do programa
End
End Sub
Private Sub Command3_Click()
fimciclo = True
End Sub
Private Sub Form_Load()
MSComm1.PortOpen = True
Text1.Text = KP
VScroll1.Value = KP
Text2.Text = KD
VScroll2.Value = KD
Text3.Text = KI
VScroll3.Value = KI
Text4.Text = Veloc3
HScroll1.Value = Veloc3
End Sub
Private Sub HScroll1_Change()
Veloc3 = HScroll1.Value
Text4.Text = Veloc3
End Sub
Private Sub MSComm1_OnComm()
Dim sMessage As String
' rotina da porta serie
Select Case MSComm1.CommEvent
' mensagens dos eventos
Case comEvReceive
buffer() = MSComm1.Input
recebeu = True
Case comEvSend
Case comEvCTS
sMessage = "Detectada alteração em CTS"
Case comEvDSR
sMessage = "Detectada alteração em DSR"
Case comEvCD
sMessage = "Detectada alteração em CD"
Case comEvRing
sMessage = "O fone esta tocando"
Case comEvEOF
sMessage = "Fim de arquivo encontrado"
' Error messages.
Case comBreak
sMessage = "Break recebido"
Case comCDTO
sMessage = "Carrier Detect Timeout"
Case comCTSTO
sMessage = "CTS Timeout"
Case comDCB
sMessage = "Error retrieving DCB"
Case comDSRTO
sMessage = "DSR Timeout"
Case comFrame
sMessage = "Erro - Framing"
Case comOverrun
sMessage = "Erro - Overrun "
Case comRxOver
sMessage = "Receive Buffer Overflow"
Case comRxParity
sMessage = "Erro de Paridade"
Case comTxFull
sMessage = "Transmite Buffer Cheio"
Case Else
sMessage = "Erro ou evento desconhecido"
End Select
'SetStatus (sMessage), False
End Sub
Private Sub Text1_Change()
KP = Text1.Text
VScroll1.Value = KP
End Sub
Private Sub Text2_Change()
KD = Text2.Text
VScroll2.Value = KD
End Sub
Private Sub Text3_Change()
KI = Text3.Text
VScroll3.Value = KI
End Sub
Private Sub Text4_Change()
Veloc3 = Text4.Text
HScroll1.Value = Veloc3
End Sub
Private Sub Text9_Change()
Valorref = Text9.Text
End Sub
Private Sub Timer1_Timer()
espera = True
End Sub
Private Sub VScroll1_Change()
KP = VScroll1.Value
Text1.Text = KP
End Sub
Private Sub VScroll2_Change()
KD = VScroll2.Value
Text2.Text = KD
End Sub
Private Sub VScroll3_Change()
KI = VScroll3.Value
Text3.Text = KI
End Sub
ANEXOS 2 – Esquemáticos e PCBs
ANEXOS 2
xx
ANEXOS 2 – Esquemáticos e PCBs
Esquemático do 1º
Trabalho
xxi
ANEXOS 2 – Esquemáticos e PCBs
Esquemático do 2º
Trabalho
xxiii
ANEXOS 2 – Esquemáticos e PCBs
PCB do 1º Trabalho
xxv
ANEXOS 2 – Esquemáticos e PCBs
PCB do 2º Trabalho
xxvii
ANEXOS 2 – Esquemáticos e PCBs
Esquemático da
lógica implementada
na CPLD
xxix
Circuito Final da CPLD
Bloco da comp_shifd
Bloco Comparador
Bloco Contador
ANEXOS 3 - Fichas Técnicas do Hardware desenvolvido
ANEXOS 3
xxxiv
ANEXOS 3 - Fichas Técnicas do Hardware desenvolvido
GP2Y0A02YK
xxxv
GP2Y0A02YK
GP2Y0A02YK
Long Distance Measuring
Sensor
■ Features
■ Outline Dimensions
37
29.5
4-R1.75
★
*1 Open collector output
PWB
10.45
14.4
8.95
+0.5
18.9−0.3
Connector
10.1
1 3
3.3
1.2
2-1.5
21.6
(Ta=25°C)
Symbol
Rating
Unit
V
−0.3 to +7
VCC
VO
−0.3 to VCC +0.3 V
−10 to +60
Topr
°C
Tstg
−40 to +70
°C
Lens case
R3.75
φ3.2
14.4
■ Absolute Maximum Ratings
19.8±0.1
φ3.2
1. For detection of human body and various types of objects in
home appliances, OA equipment, etc
Parameter
Supply voltage
*1
Output terminal voltage
Operating temperature
Storage temperature
★
Light emitter
side
■ Applications
Light detector
side
13
11.9
R3.75
(Unit : mm)
4-R1.75
4.475
4.5
1. Less influence on the colors of reflected objects and their
reflectivity, due to optical triangle measuring method
2. Distance output type
(Detection range:20 to 150cm)
3. An external control circuit is not necessary
Output can be connected directly to a microcomputer
Terminal connection
❈ The dimensions marked ★ are
described the dimensions of
lens center position.
❈ Unspecified tolerance : ±0.3mm
1
2
3
VO
GND
VCC
■ Recommended Operating Conditions
Parameter
Operating Supply voltage
Notice
Symbol
VCC
Rating
4.5 to 5.5
Unit
V
In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP
devices shown in catalogs, data books, etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device.
Internet Internet address for Electronic Components Group http://sharp-world.com/ecg/
GP2Y0A02YK
■ Electro-optical Characteristics
Parameter
Symbol
∆L
VO
∆VO
ICC
Distance measuring range
Output terminal voltage
Difference of output voltage
Average dissipation current
MIN.
Conditions
*2 *3
20
L=150cm
*2
Output change at L=150cm to 20cm
−
0.25
*2
1.8
−
Note) L:Distance to reflective object
*2 Using reflective object:White paper (Made by Kodak Co. Ltd. gray cards R-27 ⋅ white face, reflective ratio;90%)
*3 Distance measuring range of the optical sensor system
Fig.1 Internal Block Diagram
VCC 5V
GND
PSD
Signal
processing
circuit
Voltage
regulator
Oscillation
circuit
LED drive
circuit
LED
VO
Output
circuit
Distance measuring IC
Fig.2 Timing Chart
VCC
(Power supply)
38.3ms±9.6ms
Distance
measuring
operation
First measurement
VO (Output)
Unstable output
Second
measurement
First output
MAX. 5.0ms
nth
measurement
Second output
nth output
(Ta=25°C, VCC=5V)
TYP. MAX. Unit
150
cm
−
V
0.4
0.55
2.05
V
2.3
33
50
mA
GP2Y0A02YK
Fig.3 Analog Output Voltage vs. Distance to
Reflective Object
3
White Reflectivity:90%
Gray Reflectivity:18%
Analog output voltage (V)
2.5
2
1.5
1
0.5
0
0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
Distance to reflective object L (cm)
NOTICE
●
The circuit application examples in this publication are provided to explain representative applications of SHARP
devices and are not intended to guarantee any circuit design or license any intellectual property rights. SHARP takes
no responsibility for any problems related to any intellectual property right of a third party resulting from the use of
SHARP's devices.
●
Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device. SHARP
reserves the right to make changes in the specifications, characteristics, data, materials, structure, and other contents
described herein at any time without notice in order to improve design or reliability. Manufacturing locations are
also subject to change without notice.
●
Observe the following points when using any devices in this publication. SHARP takes no responsibility for damage
caused by improper use of the devices which does not meet the conditions and absolute maximum ratings to be used
specified in the relevant specification sheet nor meet the following conditions:
(i) The devices in this publication are designed for use in general electronic equipment designs such as:
- - - Personal computers
- -- Office automation equipment
- -- Telecommunication equipment [terminal]
- - - Test and measurement equipment
- - - Industrial control
- -- Audio visual equipment
- -- Consumer electronics
(ii) Measures such as fail-safe function and redundant design should be taken to ensure reliability and safety when
SHARP devices are used for or in connection with equipment that requires higher reliability such as:
- -- Transportation control and safety equipment (i.e., aircraft, trains, automobiles, etc.)
- - - Traffic signals
- - - Gas leakage sensor breakers
- - - Alarm equipment
- -- Various safety devices, etc.
(iii)SHARP devices shall not be used for or in connection with equipment that requires an extremely high level of
reliability and safety such as:
- - - Space applications
- -- Telecommunication equipment [trunk lines]
- -- Nuclear power control equipment
- -- Medical and other life support equipment (e.g., scuba).
●
Contact a SHARP representative in advance when intending to use SHARP devices for any "specific" applications
other than those recommended by SHARP or when it is unclear which category mentioned above controls the
intended use.
●
If the SHARP devices listed in this publication fall within the scope of strategic products described in the Foreign
Exchange and Foreign Trade Control Law of Japan, it is necessary to obtain approval to export such SHARP devices.
●
This publication is the proprietary product of SHARP and is copyrighted, with all rights reserved. Under the copyright
laws, no part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, for any purpose, in whole or in part, without the express written permission of SHARP. Express written
permission is also required before any use of this publication may be made by a third party.
●
Contact and consult with a SHARP representative if there are any questions about the contents of this publication.
ANEXOS 3 - Fichas Técnicas do Hardware desenvolvido
L78xx
xl
L7800
SERIES
POSITIVE VOLTAGE REGULATORS
..
..
.
OUTPUT CURRENT UP TO 1.5A
OUTPUT VOLTAGES OF 5; 5.2; 6; 8; 8.5; 9; 12;
15; 18; 20; 24V
THERMAL OVERLOAD PROTECTION
SHORT CIRCUIT PROTECTION
OUTPUT TRANSISTOR SOA PROTECTION
DESCRIPTION
The L7800 series of three-terminal positive regulator is available in TO-220, ISOWATT220 and TO-3
packages and with several fixed output voltages
making it useful in a wide range of applications.
These regulators can provide local on-card regulation, eliminating the distribution problems associated with single point regulation. Each type employs
internal current limiting, thermal shut-down and safe
area protection, making it essentially indestructible.
If adequate heat sinking is provided, they can deliver
over 1A output current. Although designed primarily
as fixed voltage regulators, these devices can be
used with external components to obtain adjustable
voltages and currents.
TO-3
TO-220
ISOWATT220
BLOCK DIAGRAM
January 1993
1/24
L7800 SERIES
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Vi
DC Input Voltage (for V o = 5 to 18V)
(for V o = 20, 24V)
Io
Value
Unit
35
40
V
V
Output Current
Internally limited
Pt o t
Power Dissipation
Internally limited
To p
Operating Junction Temperature (for L7800 )
(for L7800C )
– 55 to + 150
0 to + 150
°C
°C
T stg
Storage Temperature
– 65 to + 150
°C
THERMAL DATA
Symbol
Parameter
Rthj-case Thermal Resistance Junction-case
Rthj-amb Thermal Resistance Junction-ambient
Max
Max
TO-220
ISOWATT220
TO-3
3
50
4
60
4
35
Unit
o
C/W
C/W
o
CONNECTION DIAGRAM AND ORDERING NUMBERS (top view)
TO-220 & ISOWATT220
Type
L7805
L7805C
L7852C
L7806
L7806C
L7808
L7808C
L7885C
L7809C
L7812
L7812C
L7815
L7815C
L7818
L7818C
L7820
L7820C
L7824
L7824C
2/24
TO-220
TO-3
ISOWATT220
L7805CV
L7852CV
L7805CP
L7852CP
L7806CV
L7806CP
L7808CV
L7885CV
L7809CV
L7808CP
L7885CP
L7809CP
L7812CV
L7812CP
L7815CV
L7815CP
L7818CV
L7818CP
L7820CV
L7820CP
L7824CV
L7824CP
TO-3
Output Voltage
L7805T
L7805CT
L7852CT
L7806T
L7806CT
L7808T
L7808CT
L7885CT
L7809CT
L7812T
L7812CT
L7815T
L7815CT
L7818T
L7818CT
L7820T
L7820CT
L7824T
L7824CT
5V
5V
5.2V
6V
6V
8V
8V
8.5V
9V
12V
12V
15V
15V
18V
18V
20V
20V
24V
24V
L7800 SERIES
APPLICATION CIRCUIT
SCHEMATIC DIAGRAM
3/24
L7800 SERIES
TEST CIRCUITS
Figure 1 : DC Parameters.
Figure 3 : Ripple Rejection.
4/24
Figure 2 : Load Regulation.
L7800 SERIES
ELECTRICAL CHARACTERISTICS FOR L7805 (refer to the test circuits, T j = -55 to 150 o C,
V i = 10V, Io = 500 mA, Ci = 0.33 µF, C o = 0.1 µF unless otherwise specified)
Symbol
Parameter
Test Conditions
Vo
Output Voltage
Tj = 25 oC
Vo
Output Voltage
Io = 5 mA to 1 A
Vi = 8 to 20 V
∆Vo*
Line Regulation
Vi = 7 to 25 V
Vi = 8 to 12 V
∆Vo*
Load Regulation
Io = 5 to 1500 mA
Io = 250 to 750 mA
Id
Quiescent Current
Tj = 25 oC
P o ≤ 15 W
Min.
Typ.
Max.
Unit
4.8
5
5.2
V
4.65
5
5.35
V
3
1
50
25
mV
mV
100
25
mV
mV
6
mA
Tj = 25 oC
Tj = 25 oC
Tj = 25 oC
Tj = 25 oC
∆Id
Quiescent Current Change
Io = 5 to 1000 mA
0.5
mA
∆Id
Quiescent Current Change
Vi = 8 to 25 V
0.8
mA
∆V o
∆T
Output Voltage Drift
Io = 5 mA
eN
Output Noise Voltage
B = 10Hz to 100KHz Tj = 25 oC
Supply Voltage Rejection
Vi = 8 to 18 V
SVR
Vd
Dropout Voltage
Io = 1 A
Ro
Output Resistance
f = 1 KHz
Isc
Short Circuit Current
Vi = 35 V
Iscp
Short Circuit Peak Current
mV/oC
0.6
f = 120 Hz
40
68
o
Tj = 25 C
dB
2
2.5
17
Tj = 25 oC
o
Tj = 25 C
1.3
µV/VO
V
mΩ
0.75
1.2
A
2.2
3.3
A
ELECTRICAL CHARACTERISTICS FOR L7806 (refer to the test circuits, T j = -55 to 150 o C,
V i = 15V, Io = 500 mA, Ci = 0.33 µF, C o = 0.1 µF unless otherwise specified)
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
5.75
6
6.25
V
5.65
6
6.35
V
60
30
mV
mV
100
30
mV
mV
6
mA
0.5
mA
Vo
Output Voltage
Tj = 25 oC
Vo
Output Voltage
Io = 5 mA to 1 A
Vi = 9 to 21 V
∆Vo*
Line Regulation
Vi = 8 to 25 V
Vi = 9 to 13 V
∆Vo*
Load Regulation
Io = 5 to 1500 mA
Io = 250 to 750 mA
Id
Quiescent Current
Tj = 25 oC
∆Id
Quiescent Current Change
Io = 5 to 1000 mA
∆Id
Quiescent Current Change
Vi = 9 to 25 V
0.8
mA
∆V o
∆T
Output Voltage Drift
Io = 5 mA
eN
Output Noise Voltage
B = 10Hz to 100KHz Tj = 25 oC
Supply Voltage Rejection
Vi = 9 to 19 V
SVR
Vd
Dropout Voltage
Io = 1 A
Ro
Output Resistance
f = 1 KHz
Isc
Short Circuit Current
Vi = 35 V
Iscp
Short Circuit Peak Current
o
Tj = 25 C
P o ≤ 15 W
Tj = 25 oC
Tj = 25 oC
Tj = 25 oC
Tj = 25 oC
mV/oC
0.7
f = 120 Hz
40
65
o
Tj = 25 C
dB
2
2.5
19
Tj = 25 oC
1.3
µV/VO
V
mΩ
0.75
1.2
A
2.2
3.3
A
* Load and line regulation are specified at constant junction temperature. Changes in Vo due to heating effects must be taken
into account separately. Pulce testing with low duty cycle is used.
5/24
L7800 SERIES
ELECTRICAL CHARACTERISTICS FOR L7808 (refer to the test circuits, T j = -55 to 150 o C,
V i = 14V, Io = 500 mA, Ci = 0.33 µF, C o = 0.1 µF unless otherwise specified)
Symbol
Min.
Typ.
Max.
Unit
Vo
Output Voltage
Parameter
Tj = 25 oC
Test Conditions
7.7
8
8.3
V
Vo
Output Voltage
Io = 5 mA to 1 A P o ≤ 15 W
Vi = 11.5 to 23 V
7.6
8
8.4
V
∆Vo*
Line Regulation
Vi = 10.5 to 25 V Tj = 25 oC
Vi = 11 to 17 V Tj = 25 oC
80
40
mV
mV
∆Vo*
Load Regulation
Io = 5 to 1500 mA
Io = 250 to 750 mA
100
40
mV
mV
Id
Quiescent Current
Tj = 25 oC
6
mA
Tj = 25 oC
Tj = 25 oC
∆Id
Quiescent Current Change
Io = 5 to 1000 mA
0.5
mA
∆Id
Quiescent Current Change
Vi = 11.5 to 25 V
0.8
mA
∆V o
∆T
Output Voltage Drift
Io = 5 mA
eN
Output Noise Voltage
B = 10Hz to 100KHz Tj = 25 oC
Supply Voltage Rejection
Vi = 11.5 to 21.5 V
SVR
Vd
Dropout Voltage
Io = 1 A
Ro
Output Resistance
f = 1 KHz
Isc
Short Circuit Current
Vi = 35 V
Iscp
Short Circuit Peak Current
mV/oC
1
f = 120 Hz
40
62
o
Tj = 25 C
dB
2
2.5
16
Tj = 25 oC
o
Tj = 25 C
1.3
µV/VO
V
mΩ
0.75
1.2
A
2.2
3.3
A
ELECTRICAL CHARACTERISTICS FOR L7812 (refer to the test circuits, T j = -55 to 150 o C,
V i = 19V, Io = 500 mA, Ci = 0.33 µF, C o = 0.1 µF unless otherwise specified)
Symbol
Min.
Typ.
Max.
Unit
Vo
Output Voltage
Tj = 25 oC
11.5
12
12.5
V
Vo
Output Voltage
Io = 5 mA to 1 A P o ≤ 15 W
Vi = 15.5 to 27 V
11.4
12
12.6
V
∆Vo*
Line Regulation
Vi = 14.5 to 30 V Tj = 25 oC
Vi = 16 to 22 V Tj = 25 oC
120
60
mV
mV
∆Vo*
Load Regulation
Io = 5 to 1500 mA
Io = 250 to 750 mA
100
60
mV
mV
Id
Quiescent Current
Tj = 25 oC
6
mA
∆Id
Quiescent Current Change
Io = 5 to 1000 mA
0.5
mA
∆Id
Quiescent Current Change
Vi = 15 to 30 V
0.8
mA
∆V o
∆T
Output Voltage Drift
Io = 5 mA
eN
Output Noise Voltage
B = 10Hz to 100KHz Tj = 25 oC
Supply Voltage Rejection
Vi = 15 to 25 V
SVR
Parameter
Test Conditions
Vd
Dropout Voltage
Io = 1 A
Ro
Output Resistance
f = 1 KHz
Isc
Short Circuit Current
Vi = 35 V
Iscp
Short Circuit Peak Current
o
Tj = 25 C
Tj = 25 oC
Tj = 25 oC
mV/oC
1.5
f = 120 Hz
40
61
o
Tj = 25 C
dB
2
2.5
18
Tj = 25 oC
1.3
µV/VO
V
mΩ
0.75
1.2
A
2.2
3.3
A
* Load and line regulation are specified at constant junction temperature. Changes in Vo due to heating effects must be taken
into account separately. Pulce testing with low duty cycle is used.
6/24
L7800 SERIES
ELECTRICAL CHARACTERISTICS FOR L7815 (refer to the test circuits, T j = -55 to 150 o C,
V i = 23V, Io = 500 mA, Ci = 0.33 µF, C o = 0.1 µF unless otherwise specified)
Symbol
Min.
Typ.
Max.
Unit
Vo
Output Voltage
Parameter
Tj = 25 oC
Test Conditions
14.4
15
15.6
V
Vo
Output Voltage
Io = 5 mA to 1 A P o ≤ 15 W
Vi = 18.5 to 30 V
14.25
15
15.75
V
∆Vo*
Line Regulation
Vi = 17.5 to 30 V Tj = 25 oC
Vi = 20 to 26 V Tj = 25 oC
150
75
mV
mV
∆Vo*
Load Regulation
Io = 5 to 1500 mA
Io = 250 to 750 mA
150
75
mV
mV
Id
Quiescent Current
Tj = 25 oC
6
mA
Tj = 25 oC
Tj = 25 oC
∆Id
Quiescent Current Change
Io = 5 to 1000 mA
0.5
mA
∆Id
Quiescent Current Change
Vi = 18.5 to 30 V
0.8
mA
∆V o
∆T
Output Voltage Drift
Io = 5 mA
eN
Output Noise Voltage
B = 10Hz to 100KHz Tj = 25 oC
Supply Voltage Rejection
Vi = 18.5 to 28.5 V
SVR
Vd
Dropout Voltage
Io = 1 A
Ro
Output Resistance
f = 1 KHz
Isc
Short Circuit Current
Vi = 35 V
Iscp
Short Circuit Peak Current
mV/oC
1.8
f = 120 Hz
40
60
o
Tj = 25 C
dB
2
2.5
19
Tj = 25 oC
o
Tj = 25 C
1.3
µV/VO
V
mΩ
0.75
1.2
A
2.2
3.3
A
ELECTRICAL CHARACTERISTICS FOR L7818 (refer to the test circuits, T j = -55 to 150 o C,
V i = 26V, Io = 500 mA, Ci = 0.33 µF, C o = 0.1 µF unless otherwise specified)
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
17.3
18
18.7
V
17.1
18
18.9
V
180
90
mV
mV
180
90
mV
mV
6
mA
0.5
mA
Vo
Output Voltage
Tj = 25 oC
Vo
Output Voltage
Io = 5 mA to 1 A
Vi = 22 to 33 V
∆Vo*
Line Regulation
Vi = 21 to 33 V
Vi = 24 to 30 V
∆Vo*
Load Regulation
Io = 5 to 1500 mA
Io = 250 to 750 mA
Id
Quiescent Current
Tj = 25 oC
∆Id
Quiescent Current Change
Io = 5 to 1000 mA
∆Id
Quiescent Current Change
Vi = 22 to 33 V
0.8
mA
∆V o
∆T
Output Voltage Drift
Io = 5 mA
eN
Output Noise Voltage
B = 10Hz to 100KHz Tj = 25 oC
Supply Voltage Rejection
Vi = 22 to 32 V
SVR
Vd
Dropout Voltage
Io = 1 A
Ro
Output Resistance
f = 1 KHz
Isc
Short Circuit Current
Vi = 35 V
Iscp
Short Circuit Peak Current
o
Tj = 25 C
P o ≤ 15 W
Tj = 25 oC
Tj = 25 oC
Tj = 25 oC
Tj = 25 oC
mV/oC
2.3
f = 120 Hz
40
59
o
Tj = 25 C
dB
2
2.5
22
Tj = 25 oC
1.3
µV/VO
V
mΩ
0.75
1.2
A
2.2
3.3
A
* Load and line regulation are specified at constant junction temperature. Changes in Vo due to heating effects must be taken
into account separately. Pulce testing with low duty cycle is used.
7/24
L7800 SERIES
ELECTRICAL CHARACTERISTICS FOR L7820 (refer to the test circuits, T j = -55 to 150 o C,
V i = 28V, Io = 500 mA, Ci = 0.33 µF, C o = 0.1 µF unless otherwise specified)
Symbol
Parameter
Test Conditions
Vo
Output Voltage
Tj = 25 oC
Vo
Output Voltage
Io = 5 mA to 1 A
Vi = 24 to 35 V
∆Vo*
Line Regulation
Vi = 22.5 to 35 V Tj = 25 oC
Vi = 26 to 32 V Tj = 25 oC
∆Vo*
Load Regulation
Io = 5 to 1500 mA
Io = 250 to 750 mA
Id
Quiescent Current
Tj = 25 oC
P o ≤ 15 W
Min.
Typ.
Max.
Unit
19.2
20
20.8
V
19
20
21
V
200
100
mV
mV
200
100
mV
mV
6
mA
Tj = 25 oC
Tj = 25 oC
∆Id
Quiescent Current Change
Io = 5 to 1000 mA
0.5
mA
∆Id
Quiescent Current Change
Vi = 24 to 35 V
0.8
mA
∆V o
∆T
Output Voltage Drift
Io = 5 mA
eN
Output Noise Voltage
B = 10Hz to 100KHz Tj = 25 oC
Supply Voltage Rejection
Vi = 24 to 35 V
SVR
Vd
Dropout Voltage
Io = 1 A
Ro
Output Resistance
f = 1 KHz
Isc
Short Circuit Current
Vi = 35 V
Iscp
Short Circuit Peak Current
mV/oC
2.5
f = 120 Hz
40
58
o
Tj = 25 C
dB
2
2.5
24
Tj = 25 oC
o
Tj = 25 C
1.3
µV/VO
V
mΩ
0.75
1.2
A
2.2
3.3
A
ELECTRICAL CHARACTERISTICS FOR L7824 (refer to the test circuits, T j = -55 to 150 o C,
V i = 33V, Io = 500 mA, Ci = 0.33 µF, C o = 0.1 µF unless otherwise specified)
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
23
24
25
V
22.8
24
25.2
V
240
120
mV
mV
240
120
mV
mV
6
mA
0.5
mA
Vo
Output Voltage
Tj = 25 oC
Vo
Output Voltage
Io = 5 mA to 1 A
Vi = 28 to 38 V
∆Vo*
Line Regulation
Vi = 27 to 38 V
Vi = 30 to 36 V
∆Vo*
Load Regulation
Io = 5 to 1500 mA
Io = 250 to 750 mA
Id
Quiescent Current
Tj = 25 oC
∆Id
Quiescent Current Change
Io = 5 to 1000 mA
∆Id
Quiescent Current Change
Vi = 28 to 38 V
0.8
mA
∆V o
∆T
Output Voltage Drift
Io = 5 mA
eN
Output Noise Voltage
B = 10Hz to 100KHz Tj = 25 oC
Supply Voltage Rejection
Vi = 28 to 38 V
SVR
Vd
Dropout Voltage
Io = 1 A
Ro
Output Resistance
f = 1 KHz
Isc
Short Circuit Current
Vi = 35 V
Iscp
Short Circuit Peak Current
o
Tj = 25 C
P o ≤ 15 W
Tj = 25 oC
Tj = 25 oC
Tj = 25 oC
Tj = 25 oC
mV/oC
3
f = 120 Hz
40
56
o
Tj = 25 C
dB
2
2.5
28
Tj = 25 oC
1.3
µV/VO
V
mΩ
0.75
1.2
A
2.2
3.3
A
* Load and line regulation are specified at constant junction temperature. Changes in Vo due to heating effects must be taken
into account separately. Pulce testing with low duty cycle is used.
8/24
L7800 SERIES
ELECTRICAL CHARACTERISTICS FOR L7805C (refer to the test circuits, Tj = 0 to 125 oC,
V i = 10V, Io = 500 mA, Ci = 0.33 µF, C o = 0.1 µF unless otherwise specified)
Symbol
Parameter
Test Conditions
Vo
Output Voltage
Tj = 25 oC
Vo
Output Voltage
Io = 5 mA to 1 A
Vi = 7 to 20 V
∆Vo*
Line Regulation
Vi = 7 to 25 V
Vi = 8 to 12 V
∆Vo*
Load Regulation
Io = 5 to 1500 mA
Io = 250 to 750 mA
Id
Quiescent Current
Tj = 25 oC
P o ≤ 15 W
Min.
Typ.
Max.
Unit
4.8
5
5.2
V
4.75
5
5.25
V
3
1
100
50
mV
mV
100
50
mV
mV
8
mA
Tj = 25 oC
Tj = 25 oC
Tj = 25 oC
Tj = 25 oC
∆Id
Quiescent Current Change
Io = 5 to 1000 mA
0.5
mA
∆Id
Quiescent Current Change
Vi = 7 to 25 V
0.8
mA
∆V o
∆T
Output Voltage Drift
Io = 5 mA
eN
Output Noise Voltage
B = 10Hz to 100KHz Tj = 25 oC
Supply Voltage Rejection
Vi = 8 to 18 V
SVR
Vd
Dropout Voltage
Io = 1 A
Ro
Output Resistance
f = 1 KHz
Isc
Short Circuit Current
Vi = 35 V
Iscp
Short Circuit Peak Current
f = 120 Hz
-1.1
mV/oC
40
µV
62
o
Tj = 25 C
Tj = 25 oC
o
Tj = 25 C
dB
2
V
17
mΩ
750
mA
2.2
A
ELECTRICAL CHARACTERISTICS FOR L7852C (refer to the test circuits, Tj = 0 to 125 oC,
V i = 10V, Io = 500 mA, Ci = 0.33 µF, C o = 0.1 µF unless otherwise specified)
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
5.0
5.2
5.4
V
4.95
5.2
5.45
V
3
1
105
52
mV
mV
105
52
mV
mV
8
mA
0.5
mA
Vo
Output Voltage
Tj = 25 oC
Vo
Output Voltage
Io = 5 mA to 1 A
Vi = 8 to 20 V
∆Vo*
Line Regulation
Vi = 7 to 25 V
Vi = 8 to 12 V
∆Vo*
Load Regulation
Io = 5 to 1500 mA
Io = 250 to 750 mA
Id
Quiescent Current
Tj = 25 oC
∆Id
Quiescent Current Change
Io = 5 to 1000 mA
∆Id
Quiescent Current Change
Vi = 7 to 25 V
1.3
mA
∆V o
∆T
Output Voltage Drift
Io = 5 mA
eN
Output Noise Voltage
B = 10Hz to 100KHz Tj = 25 oC
Supply Voltage Rejection
Vi = 8 to 18 V
SVR
Vd
Dropout Voltage
Io = 1 A
Ro
Output Resistance
f = 1 KHz
Isc
Short Circuit Current
Vi = 35 V
Iscp
Short Circuit Peak Current
o
Tj = 25 C
P o ≤ 15 W
Tj = 25 oC
Tj = 25 oC
Tj = 25 oC
Tj = 25 oC
f = 120 Hz
o
Tj = 25 C
Tj = 25 oC
-1.0
mV/oC
42
µV
61
dB
2
V
17
mΩ
750
mA
2.2
A
* Load and line regulation are specified at constant junction temperature. Changes in Vo due to heating effects must be taken
into account separately. Pulce testing with low duty cycle is used.
9/24
L7800 SERIES
ELECTRICAL CHARACTERISTICS FOR L7806C (refer to the test circuits, Tj = 0 to 125 oC,
V i = 11V, Io = 500 mA, Ci = 0.33 µF, C o = 0.1 µF unless otherwise specified)
Symbol
Parameter
Test Conditions
Vo
Output Voltage
Tj = 25 oC
Vo
Output Voltage
Io = 5 mA to 1 A
Vi = 8 to 21 V
∆Vo*
Line Regulation
Vi = 8 to 25 V
Vi = 9 to 13 V
∆Vo*
Load Regulation
Io = 5 to 1500 mA
Io = 250 to 750 mA
Id
Quiescent Current
Tj = 25 oC
P o ≤ 15 W
Min.
Typ.
Max.
Unit
5.75
6
6.25
V
5.7
6
6.3
V
120
60
mV
mV
120
60
mV
mV
8
mA
Tj = 25 oC
Tj = 25 oC
Tj = 25 oC
Tj = 25 oC
∆Id
Quiescent Current Change
Io = 5 to 1000 mA
0.5
mA
∆Id
Quiescent Current Change
Vi = 8 to 25 V
1.3
mA
∆V o
∆T
Output Voltage Drift
Io = 5 mA
eN
Output Noise Voltage
B = 10Hz to 100KHz Tj = 25 oC
Supply Voltage Rejection
Vi = 9 to 19 V
SVR
Vd
Dropout Voltage
Io = 1 A
Ro
Output Resistance
f = 1 KHz
Isc
Short Circuit Current
Vi = 35 V
Iscp
Short Circuit Peak Current
f = 120 Hz
-0.8
mV/oC
45
µV
59
o
Tj = 25 C
Tj = 25 oC
o
Tj = 25 C
dB
2
V
19
mΩ
550
mA
2.2
A
ELECTRICAL CHARACTERISTICS FOR L7808C (refer to the test circuits, Tj = 0 to 125 oC,
V i = 14V, Io = 500 mA, Ci = 0.33 µF, C o = 0.1 µF unless otherwise specified)
Symbol
Min.
Typ.
Max.
Unit
Vo
Output Voltage
Tj = 25 oC
7.7
8
8.3
V
Vo
Output Voltage
Io = 5 mA to 1 A P o ≤ 15 W
Vi = 10.5 to 25 V
7.6
8
8.4
V
∆Vo*
Line Regulation
Vi = 10.5 to 25 V Tj = 25 oC
Vi = 11 to 17 V Tj = 25 oC
160
80
mV
mV
∆Vo*
Load Regulation
Io = 5 to 1500 mA
Io = 250 to 750 mA
160
80
mV
mV
Id
Quiescent Current
Tj = 25 oC
8
mA
∆Id
Quiescent Current Change
Io = 5 to 1000 mA
0.5
mA
∆Id
Quiescent Current Change
Vi = 10.5 to 25 V
1
mA
∆V o
∆T
Output Voltage Drift
Io = 5 mA
eN
Output Noise Voltage
B = 10Hz to 100KHz Tj = 25 oC
Supply Voltage Rejection
Vi = 11.5 to 21.5 V
SVR
Parameter
Test Conditions
Vd
Dropout Voltage
Io = 1 A
Ro
Output Resistance
f = 1 KHz
Isc
Short Circuit Current
Vi = 35 V
Iscp
Short Circuit Peak Current
o
Tj = 25 C
Tj = 25 oC
Tj = 25 oC
f = 120 Hz
o
Tj = 25 C
Tj = 25 oC
-0.8
mV/oC
52
µV
56
dB
2
V
16
mΩ
450
mA
2.2
A
* Load and line regulation are specified at constant junction temperature. Changes in Vo due to heating effects must be taken
into account separately. Pulce testing with low duty cycle is used.
10/24
L7800 SERIES
ELECTRICAL CHARACTERISTICS FOR L7885C (refer to the test circuits, Tj = 0 to 125 oC,
V i = 14.5V, I o = 500 mA, C i = 0.33 µF, C o = 0.1 µF unless otherwise specified)
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
8.2
8.5
8.8
V
8.1
8.5
8.9
V
Vi = 11 to 27 V Tj = 25 oC
Vi = 11.5 to 17.5 V Tj = 25 oC
160
80
mV
mV
Tj = 25 oC
Tj = 25 oC
160
80
mV
mV
8
mA
Vo
Output Voltage
Tj = 25 oC
Vo
Output Voltage
Io = 5 mA to 1 A
Vi = 11 to 26 V
∆Vo*
Line Regulation
∆Vo*
Load Regulation
Io = 5 to 1500 mA
Io = 250 to 750 mA
Id
Quiescent Current
Tj = 25 oC
P o ≤ 15 W
∆Id
Quiescent Current Change
Io = 5 to 1000 mA
∆Id
Quiescent Current Change
Vi = 11 to 27 V
∆V o
∆T
Output Voltage Drift
Io = 5 mA
eN
Output Noise Voltage
B = 10Hz to 100KHz Tj = 25 oC
Supply Voltage Rejection
Vi = 12 to 22 V
SVR
Vd
Dropout Voltage
Io = 1 A
Ro
Output Resistance
f = 1 KHz
Isc
Short Circuit Current
Vi = 35 V
Iscp
Short Circuit Peak Current
f = 120 Hz
0.5
mA
1
mA
-0.8
mV/oC
55
µV
56
o
Tj = 25 C
Tj = 25 oC
o
Tj = 25 C
dB
2
V
16
mΩ
450
mA
2.2
A
ELECTRICAL CHARACTERISTICS FOR L7809C (refer to the test circuits, Tj = 0 to 125 oC,
V i = 15V, Io = 500 mA, Ci = 0.33 µF, C o = 0.1 µF unless otherwise specified)
Symbol
Min.
Typ.
Max.
Unit
Vo
Output Voltage
Tj = 25 oC
8.65
9
9.35
V
Vo
Output Voltage
Io = 5 mA to 1 A P o ≤ 15 W
Vi = 11.5 to 26 V
8.55
9
9.45
V
∆Vo*
Line Regulation
Vi = 11.5 to 26 V Tj = 25 oC
Vi = 12 to 18 V Tj = 25 oC
180
90
mV
mV
∆Vo*
Load Regulation
Io = 5 to 1500 mA
Io = 250 to 750 mA
180
90
mV
mV
Id
Quiescent Current
Tj = 25 oC
8
mA
∆Id
Quiescent Current Change
Io = 5 to 1000 mA
0.5
mA
∆Id
Quiescent Current Change
Vi = 11.5 to 26 V
1
mA
∆V o
∆T
Output Voltage Drift
Io = 5 mA
eN
Output Noise Voltage
B = 10Hz to 100KHz Tj = 25 oC
Supply Voltage Rejection
Vi = 12 to 23 V
SVR
Parameter
Test Conditions
Vd
Dropout Voltage
Io = 1 A
Ro
Output Resistance
f = 1 KHz
Isc
Short Circuit Current
Vi = 35 V
Iscp
Short Circuit Peak Current
o
Tj = 25 C
Tj = 25 oC
Tj = 25 oC
f = 120 Hz
o
Tj = 25 C
Tj = 25 oC
-1.0
mV/oC
70
µV
55
dB
2
V
17
mΩ
400
mA
2.2
A
* Load and line regulation are specified at constant junction temperature. Changes in Vo due to heating effects must be taken
into account separately. Pulce testing with low duty cycle is used.
11/24
L7800 SERIES
ELECTRICAL CHARACTERISTICS FOR L7812C (refer to the test circuits, Tj = 0 to 125 oC,
V i = 19V, Io = 500 mA, Ci = 0.33 µF, C o = 0.1 µF unless otherwise specified)
Symbol
Min.
Typ.
Max.
Unit
Vo
Output Voltage
Parameter
Tj = 25 oC
Test Conditions
11.5
12
12.5
V
Vo
Output Voltage
Io = 5 mA to 1 A P o ≤ 15 W
Vi = 14.5 to 27 V
11.4
12
12.6
V
∆Vo*
Line Regulation
Vi = 14.5 to 30 V Tj = 25 oC
Vi = 16 to 22 V Tj = 25 oC
240
120
mV
mV
∆Vo*
Load Regulation
Io = 5 to 1500 mA
Io = 250 to 750 mA
240
120
mV
mV
Id
Quiescent Current
Tj = 25 oC
8
mA
Tj = 25 oC
Tj = 25 oC
∆Id
Quiescent Current Change
Io = 5 to 1000 mA
0.5
mA
∆Id
Quiescent Current Change
Vi = 14.5 to 30 V
1
mA
∆V o
∆T
Output Voltage Drift
Io = 5 mA
-1
mV/oC
eN
Output Noise Voltage
B = 10Hz to 100KHz Tj = 25 oC
75
µV
Supply Voltage Rejection
Vi = 15 to 25 V
SVR
Vd
Dropout Voltage
Io = 1 A
Ro
Output Resistance
f = 1 KHz
Isc
Short Circuit Current
Vi = 35 V
Iscp
Short Circuit Peak Current
f = 120 Hz
55
o
Tj = 25 C
Tj = 25 oC
o
Tj = 25 C
dB
2
V
18
mΩ
350
mA
2.2
A
ELECTRICAL CHARACTERISTICS FOR L7815C (refer to the test circuits, Tj = 0 to 125 oC,
V i = 23V, Io = 500 mA, Ci = 0.33 µF, C o = 0.1 µF unless otherwise specified)
Symbol
Min.
Typ.
Max.
Unit
Vo
Output Voltage
Tj = 25 oC
14.4
15
15.6
V
Vo
Output Voltage
Io = 5 mA to 1 A P o ≤ 15 W
Vi = 17.5 to 30 V
14.25
15
15.75
V
∆Vo*
Line Regulation
Vi = 17.5 to 30 V Tj = 25 oC
Vi = 20 to 26 V Tj = 25 oC
300
150
mV
mV
∆Vo*
Load Regulation
Io = 5 to 1500 mA
Io = 250 to 750 mA
300
150
mV
mV
Id
Quiescent Current
Tj = 25 oC
8
mA
∆Id
Quiescent Current Change
Io = 5 to 1000 mA
0.5
mA
∆Id
Quiescent Current Change
Vi = 17.5 to 30 V
1
mA
∆V o
∆T
Output Voltage Drift
Io = 5 mA
-1
mV/oC
eN
Output Noise Voltage
B = 10Hz to 100KHz Tj = 25 oC
90
µV
Supply Voltage Rejection
Vi = 18.5 to 28.5 V
SVR
Parameter
Test Conditions
Vd
Dropout Voltage
Io = 1 A
Ro
Output Resistance
f = 1 KHz
Isc
Short Circuit Current
Vi = 35 V
Iscp
Short Circuit Peak Current
o
Tj = 25 C
Tj = 25 oC
Tj = 25 oC
f = 120 Hz
o
Tj = 25 C
Tj = 25 oC
54
dB
2
V
19
mΩ
230
mA
2.1
A
* Load and line regulation are specified at constant junction temperature. Changes in Vo due to heating effects must be taken
into account separately. Pulce testing with low duty cycle is used.
12/24
L7800 SERIES
ELECTRICAL CHARACTERISTICS FOR L7818C (refer to the test circuits, Tj = 0 to 125 oC,
V i = 26V, Io = 500 mA, Ci = 0.33 µF, C o = 0.1 µF unless otherwise specified)
Symbol
Parameter
Test Conditions
Vo
Output Voltage
Tj = 25 oC
Vo
Output Voltage
Io = 5 mA to 1 A
Vi = 21 to 33 V
∆Vo*
Line Regulation
Vi = 21 to 33 V
Vi = 24 to 30 V
∆Vo*
Load Regulation
Io = 5 to 1500 mA
Io = 250 to 750 mA
Id
Quiescent Current
Tj = 25 oC
P o ≤ 15 W
Quiescent Current Change
Io = 5 to 1000 mA
Quiescent Current Change
Vi = 21 to 33 V
∆V o
∆T
Output Voltage Drift
Io = 5 mA
eN
Output Noise Voltage
B = 10Hz to 100KHz Tj = 25 oC
Supply Voltage Rejection
Vi = 22 to 32 V
Dropout Voltage
Io = 1 A
Ro
Output Resistance
f = 1 KHz
Isc
Short Circuit Current
Vi = 35 V
Iscp
Short Circuit Peak Current
Max.
Unit
18
18.7
V
17.1
18
18.9
V
360
180
mV
mV
360
180
mV
mV
8
mA
Tj = 25 oC
Tj = 25 oC
∆Id
Vd
Typ.
17.3
Tj = 25 oC
Tj = 25 oC
∆Id
SVR
Min.
f = 120 Hz
0.5
mA
1
mA
-1
mV/oC
110
µV
53
o
Tj = 25 C
Tj = 25 oC
o
Tj = 25 C
dB
2
V
22
mΩ
200
mA
2.1
A
ELECTRICAL CHARACTERISTICS FOR L7820C (refer to the test circuits, Tj = 0 to 125 oC,
V i = 28V, Io = 500 mA, Ci = 0.33 µF, C o = 0.1 µF unless otherwise specified)
Symbol
Parameter
Test Conditions
Vo
Output Voltage
Tj = 25 oC
Vo
Output Voltage
Io = 5 mA to 1 A
Vi = 23 to 35 V
∆Vo*
Line Regulation
Vi = 22.5 to 35 V Tj = 25 oC
Vi = 26 to 32 V Tj = 25 oC
∆Vo*
Load Regulation
Io = 5 to 1500 mA
Io = 250 to 750 mA
Id
Quiescent Current
Tj = 25 oC
∆Id
Quiescent Current Change
Io = 5 to 1000 mA
∆Id
Quiescent Current Change
Vi = 23 to 35 V
∆V o
∆T
Output Voltage Drift
Io = 5 mA
eN
Output Noise Voltage
B = 10Hz to 100KHz Tj = 25 oC
Supply Voltage Rejection
Vi = 24 to 35 V
SVR
Vd
Dropout Voltage
Io = 1 A
Ro
Output Resistance
f = 1 KHz
Isc
Short Circuit Current
Vi = 35 V
Iscp
Short Circuit Peak Current
o
Tj = 25 C
P o ≤ 15 W
Min.
Typ.
Max.
Unit
19.2
20
20.8
V
19
20
21
V
400
200
mV
mV
400
200
mV
mV
Tj = 25 oC
Tj = 25 oC
f = 120 Hz
o
Tj = 25 C
Tj = 25 oC
8
mA
0.5
mA
1
mA
-1
mV/oC
150
µV
52
dB
2
V
24
mΩ
180
mA
2.1
A
* Load and line regulation are specified at constant junction temperature. Changes in Vo due to heating effects must be taken
into account separately. Pulce testing with low duty cycle is used.
13/24
L7800 SERIES
ELECTRICAL CHARACTERISTICS FOR L7824C (refer to the test circuits, Tj = 0 to 125 oC,
V i = 33V, Io = 500 mA, Ci = 0.33 µF, C o = 0.1 µF unless otherwise specified)
Symbol
Parameter
Test Conditions
Vo
Output Voltage
Tj = 25 oC
Vo
Output Voltage
Io = 5 mA to 1 A
Vi = 27 to 38 V
∆Vo*
Line Regulation
Vi = 27 to 38 V
Vi = 30 to 36 V
∆Vo*
Load Regulation
Io = 5 to 1500 mA
Io = 250 to 750 mA
Id
Quiescent Current
Tj = 25 oC
P o ≤ 15 W
Min.
Typ.
Max.
Unit
23
24
25
V
22.8
24
25.2
V
480
240
mV
mV
480
240
mV
mV
8
mA
Tj = 25 oC
Tj = 25 oC
Tj = 25 oC
Tj = 25 oC
∆Id
Quiescent Current Change
Io = 5 to 1000 mA
∆Id
Quiescent Current Change
Vi = 27 to 38 V
∆V o
∆T
Output Voltage Drift
Io = 5 mA
-1.5
mV/oC
eN
Output Noise Voltage
B = 10Hz to 100KHz Tj = 25 oC
170
µV
Supply Voltage Rejection
Vi = 28 to 38 V
SVR
Vd
Dropout Voltage
Io = 1 A
Ro
Output Resistance
f = 1 KHz
Isc
Short Circuit Current
Vi = 35 V
Iscp
Short Circuit Peak Current
o
Tj = 25 C
f = 120 Hz
o
Tj = 25 C
Tj = 25 oC
50
0.5
mA
1
mA
dB
2
V
28
mΩ
150
mA
2.1
A
* Load and line regulation are specified at constant junction temperature. Changes in Vo due to heating effects must be taken
into account separately. Pulce testing with low duty cycle is used.
14/24
L7800 SERIES
Figure 4 : Dropout Voltage vs. Junction Temperature.
Figure 5 : Peak Output Current vs. Input/output
Differential Voltage.
Figure 6 : Supply Voltage Rejection vs. Frequency.
Figure 7 : Output Voltage vs. Junction Temperature.
Figure 8 : Output Impedance vs. Frequency.
Figure 9 : Quiescent Current vs. Junction Temperature.
15/24
L7800 SERIES
Figure 10 : Load Transient Response.
Figure 11 : Line Transient Response.
Figure 12 : Quiescent Current vs. Input Voltage.
Figure 13 : Fixed Output Regulator.
Figure 14 : Current Regulator.
IO =
Notes : 1.
2.
3.
16/24
To specify an output voltage, substitute voltage
value for ”XX”.
Although no output capacitor is needed for stabili ty, it does improve transient response.
Required if regulator is located an appreciable
dis-tance from power supply filter.
VXX
R1
+ Id
L7800 SERIES
Figure 15 : Circuit for Increasing Output Voltage.
Figure 16 : Adjustable Output Regulator
(7 to 30V).
IR1 ≥ 5 Id
VO = VXX (1 +
R2
R1
) + Id R2
Figure 17 : 0.5 to 10V Regulator.
Figure 18 : High Current Voltage Regulator.
R1 =
IREQ –
VO = VXX
R4
R1
VBEQ1
IQ1
βQ1
IO = IREG + Q1 [IREG –
VBEQ1
R1
]
17/24
L7800 SERIES
Figure 19 : High Output Current with Short Circuit
Protection.
RSC =
Figure 20 : Tracking Voltage Regulator.
VBEQ2
ISC
Figure 21 : Split Power Supply (± 15V – 1A).
Figure 22 : Negative Output Voltage Circuit.
* Against potential latch-up problems.
Figure 23 : Switching Regulator.
Figure 24 : High Input Voltage Circuit.
VIN = Vi – (VZ + VBE)
18/24
L7800 SERIES
Figure 25 : High Input Voltage Circuit.
Figure 26 : High Output Voltage Regulator.
Figure 27 : High Input and Output Voltage.
Figure 28 : Reducing Power Dissipation with
Dropping Resistor.
VO = VXX + VZ1
R=
Vi(min) – VXX – VDROP(max)
IO(max) + Id(max)
Figure 29 : Remote Shutdown.
19/24
L7800 SERIES
Figure 30 : Power AM Modulator (unity voltage
gain, Io ≤ 1A).
Figure 31 : Adjustable Output Voltage with Temperature Compensation.
VO = VXX (1 +
Note : The circuit performs well up to 100KHz.
R2
) + VBE
R1
Note : Q2 is connected as a diode in order to compensate
the variation of the Q 1 VBE with the temperature. C allows a
slow rise-time of the VO
Figure 32 : Light Controllers (Vo min = Vxx + VBE).
VO falls when the light goes up
VO rises when the light goes up
Figure 33 : Protection against Input Short-circuit
with High Capacitance Loads.
Applications with high capacitance loads and an output voltage greater than 6 volts need an external diode (see fig. 33)
to protect the device against input short circuit. In this case
the input voltage falls rapidly while the output voltage decreases showly. The capacitance discharges by means of
the Base-Emitter junction of the series pass transistor in the
regulator. If the energy is sufficiently high, the tran-sistor
20/24
L7800 SERIES
TO-3 MECHANICAL DATA
mm
DIM.
MIN.
inch
TYP.
MAX.
MIN.
TYP.
MAX.
A
11.00
13.10
0.433
0.516
B
0.97
1.15
0.038
0.045
C
1.50
1.65
0.059
0.065
D
8.32
8.92
0.327
0.351
E
19.00
20.00
0.748
0.787
G
10.70
11.10
0.421
0.437
N
16.50
17.20
0.649
0.677
P
25.00
26.00
0.984
1.023
R
4.00
4.09
0.157
0.161
U
38.50
39.30
1.515
1.547
V
30.00
30.30
1.187
1.193
A
P
C
O
N
B
V
E
G
U
D
R
P003F
21/24
L7800 SERIES
TO-220 MECHANICAL DATA
mm
DIM.
MIN.
inch
MAX.
MIN.
A
4.40
TYP.
4.60
0.173
0.181
C
1.23
1.32
0.048
0.051
D
2.40
2.72
0.094
D1
TYP.
MAX.
0.107
1.27
0.050
E
0.49
0.70
0.019
0.027
F
0.61
0.88
0.024
0.034
F1
1.14
1.70
0.044
0.067
F2
1.14
1.70
0.044
0.067
G
4.95
5.15
0.194
0.203
G1
2.4
2.7
0.094
0.106
H2
10.0
10.40
0.393
L2
0.409
16.4
0.645
13.0
14.0
0.511
0.551
L5
2.65
2.95
0.104
0.116
L6
15.2
15.9
0.598
0.625
L7
6.2
6.6
0.244
0.260
L9
3.5
4.2
0.137
0.165
DIA.
3.75
3.85
0.147
0.151
D1
C
D
A
E
L4
H2
G
G1
F1
L2
F2
F
Dia.
L5
L9
L7
L6
L4
P011C
22/24
L7800 SERIES
ISOWATT220 MECHANICAL DATA
mm
DIM.
MIN.
inch
TYP.
MAX.
MIN.
TYP.
MAX.
A
4.4
4.6
0.173
0.181
B
2.5
2.7
0.098
0.106
D
2.5
2.75
0.098
0.108
E
0.4
0.7
0.015
0.027
F
0.75
1
0.030
0.039
F1
1.15
1.7
0.045
0.067
F2
1.15
1.7
0.045
0.067
G
4.95
5.2
0.195
0.204
G1
2.4
2.7
0.094
0.106
H
10
10.4
0.393
0.409
L2
16
0.630
28.6
30.6
1.126
1.204
L4
9.8
10.6
0.385
0.417
L6
15.9
16.4
0.626
0.645
L7
9
9.3
0.354
3.66
Ø
3
3.2
0.118
0.126
B
D
A
E
L3
L3
L6
F
F1
L7
F2
H
G
G1
Ø
1 2 3
L2
L4
P011G
23/24
L7800 SERIES
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronics products are not authorized for use ascritical components in life support devices or systems without express
written approval of SGS-THOMSON Microelectonics.
 1994 SGS-THOMSON Microelectronics - All Rights Reserved
SGS-THOMSON Microelectronics GROUP OF COMPANIES
Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A
24/24
ANEXOS 3 - Fichas Técnicas do Hardware desenvolvido
1N4001
lxv
1N4001 thru 1N4007
Vishay Semiconductors
formerly General Semiconductor
General Purpose Plastic Rectifier
DO-204AL
(DO-41)
Reverse Voltage
50 to 1000V
Forward Current 1.0A
Features
1.0 (25.4)
MIN.
• Plastic package has Underwriters Laboratories
Flammability Classification 94V-0
• Construction utilizes void-free molded plastic technique
• Low reverse leakage
• High forward surge capability
• High temperature soldering guaranteed: 350°C/10 seconds,
0.375" (9.5mm) lead length, 5 lbs. (2.3kg) tension
0.107 (2.7)
0.080 (2.0)
DIA.
0.205 (5.2)
0.160 (4.1)
Mechanical Data
Case: JEDEC DO-204AL, molded plastic body
Terminals: Plated axial leads, solderable per
MIL-STD-750, Method 2026
Polarity: Color band denotes cathode end
Mounting Position: Any
Weight: 0.012 oz., 0.3 g
1.0 (25.4)
MIN.
0.034 (0.86)
0.028 (0.71)
DIA.
NOTE: Lead diameter is 0.026 (0.66)
0.023 (0.58)
for suffix "E" part numbers
Dimensions in inches and (millimeters)
Maximum Ratings & Thermal Characteristics
Ratings at 25°C ambient temperature unless otherwise specified.
Parameter
Symb.
1N
4001
1N
4002
1N
4003
1N
4004
1N
4005
1N
4006
1N
4007
Unit
Maximum repetitive peak reverse voltage
VRRM
50
100
200
400
600
800
1000
V
* Maximum RMS voltage
VRMS
35
70
140
280
420
560
700
V
* Maximum DC blocking voltage
VDC
50
100
200
400
600
800
1000
V
* Maximum average forward rectified current
0.375" (9.5mm) lead length at TA = 75°C
IF(AV)
1.0
A
* Peak forward surge current 8.3ms single half sine-wave
superimposed on rated load (JEDEC Method) TA = 75°C
IFSM
30
A
* Maximum full load reverse current, full cycle
average 0.375" (9.5mm) lead length TL = 75°C
IR(AV)
30
µA
Typical thermal resistance (1)
RθJA
RθJL
50
25
°C/W
TA
+150
V
TJ, TSTG
–50 to +175
°C
* Maximum DC blocking voltage temperature
* Operating junction and storage temperature range
Electrical Characteristics
Ratings at 25°C ambient temperature unless otherwise specified.
Maximum instantaneous forward voltage at 1.0A
* Maximum DC reverse current
at rated DC blocking voltage
TA = 25°C
TA = 125°C
Typical junction capacitance at 4.0V, 1MHz
VF
1.1
V
IR
5.0
50
µA
CJ
15
pF
Note: (1) Thermal resistance from junction to ambient at 0.375” (9.5mm) lead length, P.C.B. mounted
Document Number 88503
13-Jan-03
*JEDEC registered values
www.vishay.com
1
1N4001 thru 1N4007
Vishay Semiconductors
formerly General Semiconductor
Ratings and
Characteristic Curves (TA = 25°C unless otherwise noted)
Fig. 2 – Maximum Non-Repetitive
Peak Forward Surge Current
Fig. 1 – Forward Current Derating Curve
30
60HZ Resistive or
Inductive Load
Peak Forward Surge Current (A)
Average Forward Rectified Current (A)
1.0
0.8
0.2 x 0.2" (5.0 x 5.0mm)
Copper Pads
0.6
0.4
0.2
0.375" (9.5mm)
Lead Length
0
TA = 75°C
8.3ms Single Half Sine-Wave
(JEDEC Method)
25
20
15
10
5.0
0
25
50
75
100
125
150
1
175
10
Ambient Temperature (°C)
Fig. 3 – Typical Instantaneous
Forward Characteristics
Fig. 4 – Typical Reverse Characteristics
1,000
10
Instantaneous Reverse Current (µA)
Instantaneous Forward Current (A)
20
TJ = 25°C
Pulse Width = 300µs
1% Duty Cycle
1
0.1
0.01
0.6
TJ = 150°C
100
10
TJ = 100°C
1
TJ = 25°C
0.1
0.01
0.8
1.0
1.2
1.4
1.6
1.8
0
60
80
100
100
100
Transient Thermal Impedance (°C/W)
TJ = 25°C
f = 1.0MHZ
Vsig = 50mVp-p
10
1
10
Reverse Voltage (V)
www.vishay.com
2
40
Fig. 6 – Typical Transient Thermal
Impedance
Fig. 5 – Typical Junction Capacitance
1
0.1
20
Percentage of Peak Reverse Voltage (%)
Instantaneous Forward Voltage (V)
Junction Capacitance (pF)
100
Number of Cycles at 60HZ
100
10
1
0.1
0.01
0.1
1
10
100
t -- Pulse Duration (sec)
Document Number 88503
13-Jan-03
ANEXOS 3 - Fichas Técnicas do Hardware desenvolvido
GL494
lxviii
GL494
GL494
PWM CONTROL CIRCUIT
Pin Configuration
Description
The GL494 incorporates on a single monolithic chip all the
functions required in the construction of a pulse-widthmodulation control circuit. Designed primarily for power
supply control, the GL494 contains an on-chip 5-volt
regulator, two error amplifiers, adjustable oscillator, deadtime control comparator, pulse-steering flip-flop, and
output-control circuitry. The uncommitted output
transistors pro-vide either common-emitter or emitterfollower output capability. Push-pull or single-ended
output operation may be selected through the outputcontrol function. The ar-chitecture of the GL494 prohibits
the possibility of either output being pulsed twice during
push-pull operation.
NONINV INPUT
1
16
NON INV INPUT
INV. INPUT
2
15
INV. INPUT
FEEDBACK
3
14
REF. OUT
4
13
OUTPUT CONTROL
Cr
5
12
Vcc
Rr
6
11
C2
GND
7
10
E2
C1
8
9
E1
DEAD TIME CONTROL
Features
— Complete PWM Power Control Circuitry
— Uncommitted Outputs for 200mA Sink or Source
— Output Control Selects Single-Ended or Push-Pull
Operation
— Internal Circuitry Prohibits Double Pulse at Either
Output
— Internal Regulator Provides a Stable 5V Reference
Supply
— Variable Dead-Time Provides Control Over Total
Range
Function Table
Output Control
Output Function
Grounded
Single-ended or Parallel Output
At Vref
Normal Push-Pull Operation
Block Diagram
RT
CT
OUTPUT
CONTROL
OSCILLATOR
(See Function Table)
DEAD
TIME
CONTROL
PULSE STEERING
FLIP FLOP
Q
0.1V
T
(4)
ERROR AMPLIFIERS
NONINVERTING(1)
+
INPUT
INVERTING
INPUT
(2)
INVERTING
INPUT
FEEDBACK
Q
PWM
COMPARATOR
(15)
E1(9) C1(8)
−
ERROR AMP1
NONINVERTING(16)
INPUT
(13)
+
−
VCC
(12)
REFERENCE
REGULATOR
ERROR AMP2
REF OUT
(14)
GND
(7)
(3)
1
E1(10) C2(11)
GL494
Absolute Maximum Ratings
Supply Voltage, VCC ……………………………………………………………………….. 41
Amplifier Input Voltage ……………………………………………………………….. VCC +0.3
Collector Output Voltage ……………………………………………………………………… 41
Continuous Total dissipation at (or below) 25 °C ………………………………………. 1000
Operating Free-Air Temperature Range ……………………………………………… -20 to 85
Storage Temperature Range ……………………………………………………….….. -65 to 150
Collector Output Current ………………………………………………………………….. 250
V
V
V
mW
°C
°C
mA
Recommended Operation Conditions
PARAMETER
MIN
MAX
UNIT
Supply Voltage, VCC
7
40
V
Amplifier Input Voltage, V1
-0.3
VCC -2
V
Collector Output Voltage, Vo
40
V
Collector Output Current
(Each Transistor)
200
mA
Current Into Feed back Terminal
0.3
mA
Timing Capacitor, C T
0.47
10,000
nF
Timing Resistor, R T
1.8
500
KΩ
Oscillator Frequency
1
300
KHz
°C
Operating Free-Air Temperature
-20
85
Electrical Characteristics (Temperature −20 ~ 85°C , VCC =15V, f=10KHz)
Reference Section
PARAMETER
TEST CONDITIONS
MIN
TYP(1)
MAX
UNIT
4.75
5
5.25
V
Output voltage ( Vref )
IO = 1mA
Input regulation
VCC = 7 V to 40V, TA = 25°C
2
25
mV
Output regulation
IO = 1 to 10mA, TA = 25°C
1
15
mV
Output Voltage change
with temperature
TA = −20°C to 85°C
0.2
1
%
Short-circuit
Output current(2)
Vref = 0
35
mA
Oscillator Section
PARAMETER
TEST CONDITIONS
MIN
TYP(1)
MAX
UNIT
Frequency
C T = 0.01µF , R T = 12 kΩ
10
KHz
Standard deviation
of frequency (3)
All values of VCC ,
C T , R T , TA Constant
10
%
Frequency change with
Voltage
VCC = 7 V to 40V, TA = 25°C
0.1
%
Frequency change with
temperature
C T = 0.01µF , R T = 12 kΩ
TA = −20°C to 85°C
2
2
%
GL494
Dead Time Control Section
PARAMETER
TEST CONDITIONS
Input bias current (pin 4)
VI=0 to 5.25V
Maximum duty cycle,
Each output
VI ( pin 4) =0V
Input threshold voltage
(pin 4)
MIN
TYP(1)
MAX
UNIT
-2
-10
µA
45
Zero duty cycle
%
3
Maximum duty cycle
3.3
0
V
V
Error Amp Sections
PARAMETER
TEST CONDITIONS
MIN
TYP(1)
MAX
UNIT
Input offset voltage
VO( PIN3) = 2.5V
2
10
mV
Input offset current
VO( PIN3) = 2.5V
25
250
nA
Input bias current
VO( PIN3) = 2.5V
0.2
1
µA
Common-mode input
voltage range
VCC = 7V to 40V
Open-loop voltage
Amplification
∆VO = 3V, VO = 0.5 to3.
5V
LOW
-0.3
HIGH
VCC − 2
70
Unity-gain bandwidth
V
95
dB
800
KHz
Common-mode rejection ratio
VCC = 40V , TA = 25°C
65
80
dB
Output sink current (pin 3)
VID = −15mV to –5V,
VO( pin 3) = 0.7V
0.3
0.7
mA
Output source current (pin 3)
VID = 15mV to 5V,
VO( pin 3) = 3.5V
-2
mA
PWM Comparaor Section
PARAMETER
TEST CONDITIONS
MIN
TYP(1)
MAX
UNIT
4
4.5
V
Input threshold voltage (pin 3)
Zero duty cycle
Input sink current (pin 3)
VO( pin 3) = 0.7V
0.3
0.7
TEST CONDITIONS
MIN
TYP(1)
MAX
UNIT
Common-emitter configuration,
See Test Circuit 3
100
200
ns
25
100
ns
Emitter-follower configuration,
See Test Circuit 4
100
200
ns
40
100
ns
mA
Switching Characteristics
PARAMETER
Output Voltage rise time
Output Voltage fall time
Output Voltage rise time
Output Voltage fall time
3
GL494
Output Section
PARAMETER
TEST CONDITIONS
Collector off-state current
VCE = 40V, VCC = 40V
Emitter off-state current
VCC = VC = 40V, VE = 0
MIN TYP(1) MAX UNIT
2
100
mA
-100
mA
Collector-emitter Common-emitter
Saturation voltage Emitter-follower
VE = 0, I C = 200mA
1.1
1.3
VC = 15V, I E = −200mA
1.5
2.5
Output control input current
VI = Vref
V
3.5
mA
TYP(1)
MAX
UNIT
VCC = 15V
6
10
mA
VCC = 40V
9
15
mA
Total Device
PARAMETER
Standby supply current
Average supply current
TEST CONDITIONS
All other inputs &
Outputs open
V( pin 4) = 2V
See Test circuit 1
MIN
7.5
Notes:
(1)
All typical values except for temperature coefficients are at TA = 25 °C
(2)
Duration of the short circuit should not exceed one second.
(3)
Standard deviation is a measure of the statistical distribution about the mean as derived from the formula
N
σ=
∑ (X n − X ) 2
n =1
N −1
4
mA
GL494
Parameter Measurement Information
1.Dead time and Feedback Control
Vcc=15V
TEST
INPUTS
0
Vcc
VOLTAGE
AT C2
OUTPUT 1
DEAD TIME (4)
(8) C1
(9) E1
12kΩ FEEDBACK (3)
Re (6)
Cr (5)
(11) C2
0.01µF
(+) (16) ERROR (12) E2
(-) (15)
AMP
(+) (1)
ERROR
(-) (2)
AMP
(14) REF
OUTPUT
50kΩ
CONTROL GND (7) OUT
Vcc
VOLTAGE
AT C1
150Ω 150Ω
2W 2W
0
OUTPUT 2
VOLTAGE
AT CT
THRESHOLD VOLTAGE
DEAD-TIME
CONTROL
INTPUT
(13)
FEEDBACK
0V
THRESHOLD VOLTAGE
0.7V
MAX
0%
DUTY
CYCLE
TEST CIRCUIT
MAX
VOLTAGE WAVEFORMS
2. Error Amplifier Characteristics
+
ERROR AMPLIFIER
UNDER TEST
FEEDBACK
TERMINAL
V1
–
+
VREF
–
OTHER
ERROR
AMPLIFIER
3. Common-Emitter Configuration
15V
(EACH OUTPUT
CIRCUIT)
68Ω
2W
90%
90%
OUTPUT
CL=15pF
(INCLUDES PROBE AND
JIG CAPACITANCE)
10%
tr
TEST CIRCUIT
10%
tf
OUTPUT VOLTAGE WAVEFORM
5
0%
GL494
4. Emitter-Follower Configuration
(EACH OUTPUT
EIRCUIT)
15V
90%
90%
10%
10%
OUTPUT
68Ω
2W
tr
tf
CL=15pF
(INCLUDES PROBE AND
JIG CAPACITANCE)
TEST CIRCUIT
OUTPUT VOLTAGE WAVEFORM
Typical Performance Curves
FIGURE 1 – OSCILLATOR FREQUENCY versus
TIMING RESISTANCE
100k
0.001 µF
10k
AVOL, OPEN-LOOP VOATAGE GAIN (db)
300k
Vcc=15V
CT=0.01 µF
1k
0.1 µF
100
0.1 µF
30
1k
2k
5k
10k
20k
50k
FIGURE 2 – OPEN LOOP VOLTAGE GAIN AND PHASE
versus FREQUENCY
20
100
100k 200k 500k 1M
90
0
70
AVOL
60
ACH OUTPUT
%DT. PERCENT DEADTIME, EACH OUTPUT
10
9
7
CT=0.01 µF
6
-40
-80
40
-100
30
-120
20
-140
10
-160
0
1.0
10
100
1k
10k
100k
-80
1M
f, FREQUENCY (Hz)
FIGURE 3 – PERCENT DEAD TIME
versus OSCILLATOR FREQUENCY
Vcc=15V
Voc=Vref
V(PIN4)=0V
-20
-60
θ
50
RT, TIMING RESISTANCE (Ω)
8
Vcc=15V
Vo=3V
RL=2kΩ
80
FIGURE 4 – PERCENT DUTY CYCLE versus
DEAD-TIME CONTROL VOLTAGE
50
Vcc=15V
Voc=Vref
1) CT=0.01
RT=10k
2) CT=0.001
RT=30K
40
30
1
5
20
4
2
3
0.01 µF
2
10
1
0
0
100
1k
10k
100k
0
fo, OSCILLATOR FREQUENCY (Hz)
1.0
2.0
DEAD TIME CONTROL VOLTAGE (V)
6
3.0
3.5
GL494
1.9
FIGURE 5 – EMITTER-FOLLOWER CONFIGURATION
OUTPUT-SATURATION VOLTAGE
versus EMITTER CURRENT
1.3
1.2
Vcc=15V
1.7
VCE(SAT), SATURATION VOLTAGE (V)
VCE(SAT), SATURATION VOLTAGE (V)
1.8
1.6
1.5
1.4
1.3
1.2
1.1
0
50
100
150
200
250
IE, EMITTER CURRENT (mA)
FUGURE 7 – STANDBY-SUPPLY CURRENT
versus SUPPLY VOLTAGE
8.0
Icc, SUPPLY CURRENT (mA)
FIGURE 6 – COMMON-EMITTER CONFIGURATION
OUTPUT-SATURATION VOLTAGE
versus COLLECTOR CURRENT
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0
0
5.0
10
15
20
25
30
35
40
Vcc, SUPPLY VOLTAGE (V)
7
Vcc=15V
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0
50
100
150
200
Ic, COLLECTOR CURRENT (mA)
250
ANEXOS 3 - Fichas Técnicas do Hardware desenvolvido
L293
lxxvi
L293, L293D
QUADRUPLE HALF-H DRIVERS
SLRS008B – SEPTEMBER 1986 – REVISED JUNE 2002
D
D
D
D
D
D
D
D
D
D
Featuring Unitrode L293 and L293D
Products Now From Texas Instruments
Wide Supply-Voltage Range: 4.5 V to 36 V
Separate Input-Logic Supply
Internal ESD Protection
Thermal Shutdown
High-Noise-Immunity Inputs
Functional Replacements for SGS L293 and
SGS L293D
Output Current 1 A Per Channel
(600 mA for L293D)
Peak Output Current 2 A Per Channel
(1.2 A for L293D)
Output Clamp Diodes for Inductive
Transient Suppression (L293D)
N, NE PACKAGE
(TOP VIEW)
1,2EN
1A
1Y
HEAT SINK AND
GROUND
16
2
15
3
14
4
13
5
12
2Y
2A
6
11
7
10
VCC2
8
9
VCC1
4A
4Y
HEAT SINK AND
GROUND
3Y
3A
3,4EN
DWP PACKAGE
(TOP VIEW)
1,2EN
1A
1Y
NC
NC
NC
description
The L293 and L293D are quadruple high-current
half-H drivers. The L293 is designed to provide
bidirectional drive currents of up to 1 A at voltages
from 4.5 V to 36 V. The L293D is designed to
provide bidirectional drive currents of up to
600-mA at voltages from 4.5 V to 36 V. Both
devices are designed to drive inductive loads such
as relays, solenoids, dc and bipolar stepping
motors, as well as other high-current/high-voltage
loads in positive-supply applications.
1
HEAT SINK AND
GROUND
1
28
2
27
3
26
4
25
5
24
6
23
7
22
8
21
9
20
NC
NC
2Y
2A
10
19
11
18
12
17
13
16
VCC2
14
15
VCC1
4A
4Y
NC
NC
NC
HEAT SINK AND
GROUND
NC
NC
3Y
3A
3,4EN
All inputs are TTL compatible. Each output is a complete totem-pole drive circuit, with a Darlington transistor
sink and a pseudo-Darlington source. Drivers are enabled in pairs, with drivers 1 and 2 enabled by 1,2EN and
drivers 3 and 4 enabled by 3,4EN. When an enable input is high, the associated drivers are enabled and their
outputs are active and in phase with their inputs. When the enable input is low, those drivers are disabled and
their outputs are off and in the high-impedance state. With the proper data inputs, each pair of drivers forms
a full-H (or bridge) reversible drive suitable for solenoid or motor applications.
On the L293, external high-speed output clamp diodes should be used for inductive transient suppression.
A VCC1 terminal, separate from VCC2, is provided for the logic inputs to minimize device power dissipation.
The L293and L293D are characterized for operation from 0°C to 70°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
L293, L293D
QUADRUPLE HALF-H DRIVERS
SLRS008B – SEPTEMBER 1986 – REVISED JUNE 2002
block diagram
VCC1
1
0
1
0
1
16
2
15
1
M
14
4
13
5
12
6
11
3
7
10
9
8
VC
NOTE: Output diodes are internal in L293D.
TEXAS INSTRUMENTS
AVAILABLE OPTIONS
PACKAGE
PLASTIC
DIP
(NE)
TA
L293NE
L293DNE
0°C to 70°C
AVAILABLE OPTIONS
PACKAGED DEVICES
TA
0°C to 70°C
SMALL
OUTLINE
(DWP)
PLASTIC
DIP
(N)
L293DWP
L293DDWP
L293N
L293DN
The DWP package is available taped and reeled. Add
the suffix TR to device type (e.g., L293DWPTR).
2
POST OFFICE BOX 655303
M
4
3
2
1
0
1
0
• DALLAS, TEXAS 75265
1
0
1
0
M
L293, L293D
QUADRUPLE HALF-H DRIVERS
SLRS008B – SEPTEMBER 1986 – REVISED JUNE 2002
FUNCTION TABLE
(each driver)
INPUTS†
OUTPUT
A
EN
Y
H
H
H
L
H
L
X
L
Z
H = high level, L = low level, X = irrelevant,
Z = high impedance (off)
† In the thermal shutdown mode, the output is
in the high-impedance state, regardless of
the input levels.
logic diagram
1A
1,2EN
2A
3A
3,4EN
4A
2
1
7
10
9
15
ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
3
6
11
14
1Y
2Y
3Y
4Y
schematics of inputs and outputs (L293)
EQUIVALENT OF EACH INPUT
TYPICAL OF ALL OUTPUTS
VCC2
VCC1
Current
Source
Input
Output
GND
GND
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
L293, L293D
QUADRUPLE HALF-H DRIVERS
SLRS008B – SEPTEMBER 1986 – REVISED JUNE 2002
schematics of inputs and outputs (L293D)
EQUIVALENT OF EACH INPUT
TYPICAL OF ALL OUTPUTS
VCC2
VCC1
Current
Source
Output
Input
GND
GND
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VCC1 (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 V
Output supply voltage, VCC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 V
Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Output voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –3 V to VCC2 + 3 V
Peak output current, IO (nonrepetitive, t ≤ 5 ms): L293 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±2 A
Peak output current, IO (nonrepetitive, t ≤ 100 µs): L293D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 1.2 A
Continuous output current, IO: L293 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±1 A
Continuous output current, IO: L293D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 600 mA
Continuous total dissipation at (or below) 25°C free-air temperature (see Notes 2 and 3) . . . . . . . 2075 mW
Continuous total dissipation at 80°C case temperature (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . 5000 mW
Maximum junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to the network ground terminal.
2. For operation above 25°C free-air temperature, derate linearly at the rate of 16.6 mW/°C.
3. For operation above 25°C case temperature, derate linearly at the rate of 71.4 mW/°C. Due to variations in individual device electrical
characteristics and thermal resistance, the built-in thermal overload protection may be activated at power levels slightly above or
below the rated dissipation.
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
L293, L293D
QUADRUPLE HALF-H DRIVERS
SLRS008B – SEPTEMBER 1986 – REVISED JUNE 2002
recommended operating conditions
Supply voltage
VCC1
VCC2
VIH
High level input voltage
High-level
VCC1 ≤ 7 V
VCC1 ≥ 7 V
VIL
Low-level output voltage
MIN
MAX
4.5
7
VCC1
2.3
36
2.3
–0.3†
UNIT
V
VCC1
7
V
1.5
V
V
TA
Operating free-air temperature
0
70
°C
† The algebraic convention, in which the least positive (most negative) designated minimum, is used in this data sheet for logic voltage levels.
electrical characteristics, VCC1 = 5 V, VCC2 = 24 V, TA = 25°C
PARAMETER
TEST CONDITIONS
VOH
High-level output voltage
L293: IOH = –1 A
L293D: IOH = – 0.6 A
VOL
Low-level output voltage
L293: IOL = 1 A
L293D: IOL = 0.6 A
VOKH
VOKL
High-level output clamp voltage
L293D: IOK = – 0.6 A
Low-level output clamp voltage
L293D: IOK = 0.6 A
IIH
High level input current
High-level
IIL
Low level input current
Low-level
ICC1
Logic supply current
A
EN
A
EN
MIN
TYP
VCC2–1.8
VCC2–1.4
1.2
Output supply current
IO = 0
V
V
V
100
0.2
10
–3
–10
–2
–100
All outputs at high level
13
22
All outputs at low level
35
60
All outputs at high impedance
ICC2
1.8
0.2
VI = 0
UNIT
V
VCC2 + 1.3
1.3
VI = 7 V
IO = 0
MAX
8
24
All outputs at high level
14
24
All outputs at low level
2
6
All outputs at high impedance
2
4
µA
µA
mA
mA
switching characteristics, VCC1 = 5 V, VCC2 = 24 V, TA = 25°C
PARAMETER
TEST CONDITIONS
tPLH
tPHL
Propagation delay time, low-to-high-level output from A input
tTLH
tTHL
Transition time, low-to-high-level output
Propagation delay time, high-to-low-level output from A input
CL = 30 pF,
pF
L293NE, L293DNE
MIN
See Figure 1
Transition time, high-to-low-level output
TYP
MAX
UNIT
800
ns
400
ns
300
ns
300
ns
switching characteristics, VCC1 = 5 V, VCC2 = 24 V, TA = 25°C
PARAMETER
TEST CONDITIONS
L293DWP, L293N
L293DDWP, L293DN
MIN
TYP
UNIT
MAX
tPLH
tPHL
Propagation delay time, low-to-high-level output from A input
750
ns
Propagation delay time, high-to-low-level output from A input
200
ns
tTLH
tTHL
Transition time, low-to-high-level output
100
ns
350
ns
CL = 30 pF,
pF
See Figure 1
Transition time, high-to-low-level output
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• DALLAS, TEXAS 75265
5
L293, L293D
QUADRUPLE HALF-H DRIVERS
SLRS008B – SEPTEMBER 1986 – REVISED JUNE 2002
PARAMETER MEASUREMENT INFORMATION
tf
tr
Input
5 V 24 V
Input
50%
50%
10%
Pulse
Generator
(see Note B)
VCC1 VCC2
10%
0
tw
A
tPLH
tPHL
Y
3V
EN
Output
CL = 30 pF
(see Note A)
90%
90%
50%
50%
10%
tTHL
TEST CIRCUIT
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. The pulse generator has the following characteristics: tr ≤ 10 ns, tf ≤ 10 ns, tw = 10 µs, PRR = 5 kHz, ZO = 50 Ω.
Figure 1. Test Circuit and Voltage Waveforms
POST OFFICE BOX 655303
VOH
Output
10%
6
3V
90%
90%
• DALLAS, TEXAS 75265
VOL
tTLH
L293, L293D
QUADRUPLE HALF-H DRIVERS
SLRS008B – SEPTEMBER 1986 – REVISED JUNE 2002
APPLICATION INFORMATION
5V
24 V
VCC2
VCC1
16
10 kΩ
3
1,2EN
1
Control A
1A
1Y
2
3
Motor
2A
2Y
7
6
3,4EN
9
Control B
3A
3Y
10
11
4A
4Y
15
14
Thermal
Shutdown
4, 5, 12, 13
GND
Figure 2. Two-Phase Motor Driver (L293)
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
L293, L293D
QUADRUPLE HALF-H DRIVERS
SLRS008B – SEPTEMBER 1986 – REVISED JUNE 2002
APPLICATION INFORMATION
5V
24 V
VCC1
10 kΩ
VCC2
3
16
1,2EN
1
Control A
1Y
1A
2
3
Motor
2A
2Y
7
6
3,4EN
9
Control B
3A
10
3Y
4A
15
4Y
11
14
Thermal
Shutdown
4, 5, 12, 13
GND
Figure 3. Two-Phase Motor Driver (L293D)
8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
L293, L293D
QUADRUPLE HALF-H DRIVERS
SLRS008B – SEPTEMBER 1986 – REVISED JUNE 2002
APPLICATION INFORMATION
VCC2
SES5001
M1
SES5001
M2
3A
10
11
4A
15
EN
3A
H
H
Fast motor stop
H
Run
H
L
Run
L
Fast motor stop
X
Free-running motor
stop
X
Free-running motor
stop
14
16
8
VCC1
L
1/2 L293
9
EN
M1
4A
M2
L = low, H = high, X = don’t care
4, 5, 12, 13
GND
Figure 4. DC Motor Controls
(connections to ground and to
supply voltage)
VCC2
2 × SES5001
M
2A
1A
7
6
3
1A
2A
H
L
H
Turn right
H
H
L
Turn left
EN
2 × SES5001
2
16
8
1/2 L293
1
VCC1
FUNCTION
H
L
L
Fast motor stop
H
H
H
Fast motor stop
L
X
X
Fast motor stop
EN
L = low, H = high, X = don’t care
4, 5, 12, 13
GND
Figure 5. Bidirectional DC Motor Control
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
9
L293, L293D
QUADRUPLE HALF-H DRIVERS
SLRS008B – SEPTEMBER 1986 – REVISED JUNE 2002
APPLICATION INFORMATION
IL1/IL2 = 300 mA
C1
0.22 µF
16
L293
1
2
D5
L1
VCC2
IL1
15
+
D1
+
D8
3
14
4
13
5
12
6
11
+
D6
VCC1
D4
L2
IL2
+
7
10
8
9
D7
D3
D2
D1–D8 = SES5001
Figure 6. Bipolar Stepping-Motor Control
mounting instructions
The Rthj-amp of the L293 can be reduced by soldering the GND pins to a suitable copper area of the printed
circuit board or to an external heatsink.
Figure 9 shows the maximum package power PTOT and the θJA as a function of the side of two equal square
copper areas having a thickness of 35 µm (see Figure 7). In addition, an external heat sink can be used (see
Figure 8).
During soldering, the pin temperature must not exceed 260°C, and the soldering time must not be longer than
12 seconds.
The external heatsink or printed circuit copper area must be connected to electrical ground.
10
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
L293, L293D
QUADRUPLE HALF-H DRIVERS
SLRS008B – SEPTEMBER 1986 – REVISED JUNE 2002
APPLICATION INFORMATION
Copper Area 35-µm Thickness
Printed Circuit Board
Figure 7. Example of Printed Circuit Board Copper Area
(used as heat sink)
17.0 mm
11.9 mm
38.0 mm
Figure 8. External Heat Sink Mounting Example
(θJA = 25°C/W)
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
11
L293, L293D
QUADRUPLE HALF-H DRIVERS
SLRS008B – SEPTEMBER 1986 – REVISED JUNE 2002
APPLICATION INFORMATION
MAXIMUM POWER AND JUNCTION
vs
THERMAL RESISTANCE
MAXIMUM POWER DISSIPATION
vs
AMBIENT TEMPERATURE
4
80
2
60
40
PTOT (TA = 70°C)
1
20
0
0
0
10
30
20
Side
40
50
P TOT – Power Dissipation – W
θJA
3
θ JA – Thermal Resistance – °C/W
P TOT – Power Dissipation – W
5
With Infinite Heat Sink
4
3
Heat Sink With θJA = 25°C/W
2
Free Air
1
0
–50
50
100
TA – Ambient Temperature – °C
– mm
Figure 9
12
0
Figure 10
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
150
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Copyright  2002, Texas Instruments Incorporated
ANEXOS 3 - Fichas Técnicas do Hardware desenvolvido
MAX1112
cxxxvii
19-1231; Rev 1; 10/98
KIT
ATION
EVALU
E
L
B
A
AVAIL
+5V, Low-Power, Multi-Channel,
Serial 8-Bit ADCs
____________________________Features
The MAX1112/MAX1113 are low-power, 8-bit, 8-channel analog-to-digital converters (ADCs) that feature an
internal track/hold, voltage reference, clock, and serial
interface. They operate from a single +4.5V to +5.5V
supply and consume only 135µA while sampling at
rates up to 50ksps. The MAX1112’s 8 analog inputs
and the MAX1113’s 4 analog inputs are software-configurable, allowing unipolar/bipolar and singleended/differential operation.
♦ +4.5V to +5.5V Single Supply
Successive-approximation conversions are performed
using either the internal clock or an external serial-interface clock. The full-scale analog input range is determined by the 4.096V internal reference, or by an
externally applied reference ranging from 1V to V DD.
The 4-wire serial interface is compatible with the SPI™,
QSPI™, and MICROWIRE™ serial-interface standards.
A serial-strobe output provides the end-of-conversion
signal for interrupt-driven processors.
♦ Internal Track/Hold; 50kHz Sampling Rate
The MAX1112/MAX1113 have a software-programmable, 2µA automatic power-down mode to minimize
power consumption. Using power-down, the supply
current is reduced to 13µA at 1ksps, and only 82µA at
10ksps. Power-down can also be controlled using the
SHDN input pin. Accessing the serial interface automatically powers up the device.
The MAX1112 is available in 20-pin SSOP and DIP
packages. The MAX1113 is available in small 16-pin
QSOP and DIP packages.
♦ Low Power: 135µA at 50ksps
13µA at 1ksps
♦ 8-Channel Single-Ended or 4-Channel Differential
Inputs (MAX1112)
♦ 4-Channel Single-Ended or 2-Channel Differential
Inputs (MAX1113)
♦ Internal 4.096V Reference
♦ SPI/QSPI/MICROWIRE-Compatible Serial Interface
♦ Software-Configurable Unipolar or Bipolar Inputs
♦ Total Unadjusted Error: ±1LSB (max)
±0.3LSB (typ)
Ordering Information
PART
TEMP. RANGE
PIN-PACKAGE
MAX1112CPP
0°C to +70°C
20 Plastic DIP
MAX1112CAP
0°C to +70°C
20 SSOP
MAX1112C/D
0°C to +70°C
Dice*
*Dice are specified at TA = +25°C, DC parameters only.
Ordering Information continued at end of data sheet.
Functional Diagram
________________________Applications
Portable Data Logging
Hand-Held Measurement Devices
CS
SCLK
DIN
Medical Instruments
SHDN
System Diagnostics
CH0
CH1
CH2
CH3
CH4*
CH5*
CH6*
CH7*
Solar-Powered Remote Systems
4–20mA-Powered Remote
Data-Acquisition Systems
INPUT
SHIFT
REGISTER
INT
CLOCK
CONTROL
LOGIC
OUTPUT
SHIFT
REGISTER
ANALOG
INPUT
MUX
REFOUT
SSTRB
T/H
COM
Pin Configurations appear at end of data sheet.
DOUT
+4.096V
REFERENCE
CLOCK
IN
8-BIT
SAR ADC
OUT
REF
VDD
DGND
MAX1112
MAX1113
AGND
REFIN
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
*MAX1112 ONLY
________________________________________________________________ Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 1-800-835-8769.
MAX1112/MAX1113
General Description
MAX1112/MAX1113
+5V, Low-Power, Multi-Channel,
Serial 8-Bit ADCs
ABSOLUTE MAXIMUM RATINGS
VDD to AGND ..............................................................-0.3V to 6V
AGND to DGND .......................................................-0.3V to 0.3V
CH0–CH7, COM, REFIN,
REFOUT to AGND ...................................-0.3V to (VDD + 0.3V)
Digital Inputs to DGND ...............................................-0.3V to 6V
Digital Outputs to DGND ............................-0.3V to (VDD + 0.3V)
Continuous Power Dissipation (TA = +70°C)
16 Plastic DIP (derate 10.53mW/°C above +70°C) ......842mW
16 QSOP (derate 8.30mW/°C above +70°C) ................667mW
16 CERDIP (derate 10.00mW/°C above +70°C) ..........800mW
20 Plastic DIP (derate 11.11mW/°C above +70°C) ......889mW
20 SSOP (derate 8.00mW/°C above +70°C) ................640mW
20 CERDIP (derate 11.11mW/°C above +70°C) ..........889mW
Operating Temperature Ranges
MAX1112C_P/MAX1113C_E................................0°C to +70°C
MAX1112E_P/MAX1113E_E .............................-40°C to +85°C
MAX1112MJP/MAX1113MJE..........................-55°C to +125°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10sec) .............................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = +4.5V to +5.5V; unipolar input mode; COM = 0V; fSCLK = 500kHz, external clock (50% duty cycle); 10 clocks/conversion
cycle (50ksps); 1µF capacitor at REFOUT; TA = TMIN to TMAX; unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC ACCURACY
Resolution
8
Relative Accuracy (Note 1)
INL
Differential Nonlinearity
DNL
Bits
±0.1
No missing codes over temperature
Offset Error
±0.3
Gain Error (Note 2)
Internal or external reference
Gain Temperature Coefficient
External reference, 4.096V
±0.8
MAX111_C/E
±0.3
Total Unadjusted Error
TUE
Channel-to-Channel
Offset Matching
±0.5
LSB
±1
LSB
±1
LSB
±1
LSB
ppm/°C
±1
LSB
±0.1
LSB
SINAD
49
dB
Total Harmonic Distortion
(up to the 5th harmonic)
THD
-70
dB
Spurious-Free Dynamic Range
SFDR
68
dB
DYNAMIC SPECIFICATIONS (10.034kHz sine-wave input, 4.096Vp-p, 50ksps, 500kHz external clock)
Signal-to-Noise
and Distortion Ratio
Channel-to-Channel Crosstalk
VCH_ = 4.096Vp-p, 25kHz (Note 3)
-75
dB
Small-Signal Bandwidth
-3dB rolloff
1.5
MHz
800
kHz
Full-Power Bandwidth
2
_______________________________________________________________________________________
+5V, Low-Power, Multi-Channel,
Serial 8-Bit ADCs
(VDD = +4.5V to +5.5V; unipolar input mode; COM = 0V; fSCLK = 500kHz, external clock (50% duty cycle); 10 clocks/conversion
cycle (50ksps); 1µF capacitor at REFOUT; TA = TMIN to TMAX; unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
External clock, 500kHz, 10 clocks/conversion
20
External clock, 2MHz
1
TYP
MAX
25
55
UNITS
CONVERSION RATE
Conversion Time (Note 4)
tCONV
Track/Hold Acquisition Time
tACQ
Internal clock
µs
µs
Aperture Delay
10
ns
Aperture Jitter
<50
ps
Internal Clock Frequency
400
kHz
(Note 5)
External Clock-Frequency Range
50
Used for data transfer only
500
kHz
2
MHz
ANALOG INPUT
Unipolar input, COM = 0V
Input Voltage Range, SingleEnded and Differential (Note 6)
Bipolar input, COM = VREFIN / 2
Multiplexer Leakage Current
On/off leakage current, VCH_ = 0V or VDD
0
VREFIN
COM ±
VREFIN / 2
±0.01
Input Capacitance
±1
18
V
µA
pF
INTERNAL REFERENCE
REFOUT Voltage
3.936
REFOUT Short-Circuit Current
REFOUT Temperature Coefficient
Load Regulation (Note 7)
0mA to 0.5mA output load
Capacitive Bypass at REFOUT
4.096
4.256
V
6
mA
±50
ppm/°C
4.5
mV
1
µF
EXTERNAL REFERENCE AT REFIN
VDD +
50mV
1
Input Voltage Range
Input Current
(Note 8)
V
1
20
µA
5.5
V
Operating mode
135
250
Reference disabled
95
Software
2
POWER REQUIREMENTS
Supply Voltage
VDD
Supply Current
IDD
4.5
Full-scale input
CLOAD = 10pF
Power-down
Power-Supply Rejection
(Note 9)
PSR
SHDN at DGND
VDD = 4.5V to 5.5V; external reference,
4.096V; full-scale input
µA
µA
3.2
10
±0.4
±4
mV
_______________________________________________________________________________________
3
MAX1112/MAX1113
ELECTRICAL CHARACTERISTICS (continued)
MAX1112/MAX1113
+5V, Low-Power, Multi-Channel,
Serial 8-Bit ADCs
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +4.5V to +5.5V; unipolar input mode; COM = 0V; fSCLK = 500kHz, external clock (50% duty cycle); 10 clocks/conversion
cycle (50ksps); 1µF capacitor at REFOUT; TA = TMIN to TMAX; unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL INPUTS: DIN, SCLK, CS
DIN, SCLK, CS Input High Voltage
VIH
DIN, SCLK, CS Input Low Voltage
VIL
DIN, SCLK, CS Input Hysteresis
3
VHYST
V
0.8
V
0.2
V
DIN, SCLK, CS Input Leakage
IIN
Digital inputs = 0V or VDD
±1
µA
DIN, SCLK, CS Input Capacitance
CIN
(Note 5)
15
pF
SHDN INPUT
SHDN Input High Voltage
VSH
VDD - 0.4
SHDN Input Mid-Voltage
VSM
1.1
SHDN Voltage, Floating
VFLT
SHDN Input Low Voltage
VSL
SHDN = open
SHDN Input Current
SHDN = 0V or VDD
SHDN Maximum Allowed Leakage
for Mid-Input
SHDN = open
V
VDD - 1.1
VDD / 2
V
V
0.4
V
±4
µA
±100
nA
DIGITAL OUTPUTS: DOUT, SSTRB
Output Low Voltage
VOL
Output High Voltage
VOH
Three-State Leakage Current
Three-State Output Capacitance
4
IL
COUT
ISINK = 5mA
0.4
ISINK = 16mA
0.8
ISOURCE = 0.5mA
CS = VDD
VDD - 0.5
V
V
±0.01
CS = VDD (Note 5)
_______________________________________________________________________________________
±10
µA
15
pF
+5V, Low-Power, Multi-Channel,
Serial 8-Bit ADCs
MAX1112/MAX1113
TIMING CHARACTERISTICS (Figures 8 and 9)
(VDD = +4.5V to +5.5V, TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER
Track/Hold Acquisition Time
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
tACQ
1
µs
DIN to SCLK Setup
tDS
100
ns
DIN to SCLK Hold
tDH
0
ns
SCLK Fall to Output Data Valid
tDO
Figure 1,
CLOAD = 100pF
CS Fall to Output Enable
tDV
Figure 1, CLOAD = 100pF
240
ns
CS Rise to Output Disable
tTR
Figure 2, CLOAD = 100pF
240
ns
MAX111_C/E
20
200
MAX111_M
20
240
ns
CS to SCLK Rise Setup
tCSS
100
ns
CS to SCLK Rise Hold
tCSH
0
ns
SCLK Pulse Width High
tCH
200
ns
SCLK Pulse Width Low
SCLK Fall to SSTRB
tCL
tSSTRB
200
ns
CLOAD = 100pF
240
ns
CS Fall to SSTRB Output Enable
(Note 5)
tSDV
Figure 1, external clock mode only,
CLOAD = 100pF
240
ns
CS Rise to SSTRB Output
Disable (Note 5)
tSTR
Figure 2, external clock mode only,
CLOAD = 100pF
240
ns
SSTRB Rise to SCLK Rise
(Note 5)
tSCK
Figure 11, internal clock mode only
Wakeup Time
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
tWAKE
0
ns
External reference
20
µs
Internal reference (Note 10)
24
ms
Relative accuracy is the analog value’s deviation (at any code) from its theoretical value after the full-scale range is calibrated.
VREFIN = 4.096V, offset nulled.
On-channel grounded; sine wave applied to all off-channels.
Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Guaranteed by design. Not subject to production testing.
Common-mode range for the analog inputs is from AGND to VDD.
External load should not change during the conversion for specified accuracy.
External reference at 4.096V, full-scale input, 500kHz external clock.
Measured as | VFS (4.5V) - VFS (5.5V) |.
1µF at REFOUT; internal reference settling to 0.5LSB.
_______________________________________________________________________________________
5
__________________________________________Typical Operating Characteristics
(VDD = +5.0V; fSCLK = 500kHz; external clock (50% duty cycle); RL = ∞; TA = +25°C, unless otherwise noted.)
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
140
VDD = 4.5V
120
MAX1112/13-02
0.3
8
0.2
0.1
6
4
-0.1
2
-0.2
0
100
-60
-20
20
60
100
-0.3
-60
140
-20
20
60
100
TEMPERATURE (°C)
TEMPERATURE (°C)
OFFSET ERROR vs. TEMPERATURE
INTEGRAL NONLINEARITY
vs. CODE
0.5
140
0
64
128
192
256
DIGITAL CODE
0.20
MAX1112/13-04
0.6
0
FFT PLOT
20
0.15
fCH_ = 10.034kHz, 4Vp-p
fSAMPLE = 50ksps
0
MAX1112/13-06
VDD = 5.5V
SHDN = DGND
DNL (LSB)
160
10
MAX1112/13-05
0.10
INL (LSB)
0.4
0.3
AMPLITUDE (dB)
SUPPLY CURRENT (µA)
OUTPUT CODE = FULL SCALE
CLOAD = 10pF
SHUTDOWN SUPPLY CURRENT (µA)
MAX1112/13-01
180
DIFFERENTIAL NONLINEARITY
vs. CODE
MAX1112/13-03
SUPPLY CURRENT vs. TEMPERATURE
OFFSET ERROR (LSB)
MAX1112/MAX1113
+5V, Low-Power, Multi-Channel,
Serial 8-Bit ADCs
0.05
0
-0.05
0.2
-20
-40
-60
-0.10
0.1
-0.20
0
-60
-20
20
60
TEMPERATURE (°C)
6
-80
-0.15
100
140
-100
0
64
128
DIGITAL CODE
192
256
0
5
10
15
FREQUENCY (kHz)
_______________________________________________________________________________________
20
25
+5V, Low-Power, Multi-Channel,
Serial 8-Bit ADCs
PIN
NAME
FUNCTION
MAX1112
MAX1113
1–4
1–4
CH0–CH3
Sampling Analog Inputs
5–8
—
CH4–CH7
Sampling Analog Inputs
9
5
COM
Ground Reference for Analog Inputs. Sets zero-code voltage in single-ended mode.
Must be stable to ±0.5LSB.
10
6
SHDN
Three-Level Shutdown Input. Normally floats. Pulling SHDN low shuts the MAX1112/
MAX1113 down to 10µA (max) supply current; otherwise, the devices are fully operational. Pulling SHDN high shuts down the internal reference.
11
7
REFIN
Reference Voltage Input for Analog-to-Digital Conversion. Connect to REFOUT to use
the internal reference.
12
8
REFOUT
13
9
AGND
Analog Ground
14
10
DGND
Digital Ground
15
11
DOUT
Serial-Data Output. Data is clocked out on SCLK’s falling edge. High impedance when
CS is high.
Serial-Strobe Output. In internal clock mode, SSTRB goes low when the MAX1112/
MAX1113 begin the A/D conversion and goes high when the conversion is complete.
In external clock mode, SSTRB pulses high for two clock periods before the MSB is
shifted out. High impedance when CS is high (external clock mode only).
Internal Reference Generator Output. Bypass with a 1µF capacitor to AGND.
16
12
SSTRB
17
13
DIN
Serial-Data Input. Data is clocked in at SCLK’s rising edge.
18
14
CS
Active-Low Chip Select. Data is not clocked into DIN unless CS is low. When CS is
high, DOUT is high impedance.
19
15
SCLK
20
16
VDD
Serial-Clock Input. Clocks data in and out of serial interface. In external clock mode,
SCLK also sets the conversion speed (duty cycle must be 45% to 55%).
Positive Supply Voltage, +4.5V to +5.5V
+5V
DOUT
DOUT
3k
+5V
DOUT
CLOAD
CLOAD
DGND
DGND
a) High-Z to VOH and VOL to VOH
b) High-Z to VOL and VOH to VOL
Figure 1. Load Circuits for Enable Time
3k
3k
DOUT
3k
CLOAD
DGND
a) VOH to High-Z
CLOAD
DGND
b) VOL to High-Z
Figure 2. Load Circuits for Disable Time
_______________________________________________________________________________________
7
MAX1112/MAX1113
Pin Description
MAX1112/MAX1113
+5V, Low-Power, Multi-Channel,
Serial 8-Bit ADCs
_______________Detailed Description
The MAX1112/MAX1113 analog-to-digital converters
(ADCs) use a successive-approximation conversion
technique and input track/hold (T/H) circuitry to convert
an analog signal to an 8-bit digital output. A flexible serial interface provides easy interface to microprocessors
(µPs). Figure 3 shows the Typical Operating Circuit.
Pseudo-Differential Input
The sampling architecture of the ADC’s analog comparator is illustrated in Figure 4, the equivalent input circuit. In single-ended mode, IN+ is internally switched to
the selected input channel, CH_, and IN- is switched to
COM. In differential mode, IN+ and IN- are selected
from the following pairs: CH0/CH1, CH2/CH3,
CH4/CH5, and CH6/CH7. Configure the MAX1112
channels with Table 1 and the MAX1113 channels with
Table 2.
In differential mode, IN- and IN+ are internally switched
to either of the analog inputs. This configuration is
pseudo-differential to the effect that only the signal at
IN+ is sampled. The return side (IN-) must remain stable within ±0.5LSB (±0.1LSB for best results) with
respect to AGND during a conversion. To accomplish
this, connect a 0.1µF capacitor from IN- (the selected
analog input) to AGND if necessary.
During the acquisition interval, the channel selected as
the positive input (IN+) charges capacitor CHOLD. The
acquisition interval spans two SCLK cycles and ends
on the falling SCLK edge after the last bit of the input
control word has been entered. At the end of the acquisition interval, the T/H switch opens, retaining charge
on CHOLD as a sample of the signal at IN+.
The conversion interval begins with the input multiplexer switching CHOLD from the positive input (IN+) to the
negative input (IN-). In single-ended mode, IN- is simply COM. This unbalances node ZERO at the input of
the comparator. The capacitive DAC adjusts during the
remainder of the conversion cycle to restore node
ZERO to 0V within the limits of 8-bit resolution. This
action is equivalent to transferring a charge of 18pF x
(VIN+ - VIN-) from CHOLD to the binary-weighted capacitive DAC, which in turn forms a digital representation of
the analog input signal.
Track/Hold
The T/H enters its tracking mode on the falling clock
edge after the sixth bit of the 8-bit control byte has
been shifted in. It enters its hold mode on the falling
clock edge after the eighth bit of the control byte has
been shifted in. If the converter is set up for singleended inputs, IN- is connected to COM, and the converter samples the “+” input; if it is set up for differential
inputs, IN- connects to the “-” input, and the difference
(IN+ - IN-) is sampled. At the end of the conversion, the
positive input connects back to IN+, and C HOLD
charges to the input signal.
+5V
CH0
VDD
CH7
AGND
DGND
COM
0.1µF
ANALOG
INPUTS
CAPACITIVE DAC
REFIN
VDD
1µF
CPU
MAX1112
MAX1113
REFOUT
REFIN
1µF
CS
SCLK
DIN
DOUT
I/O
SCK (SK)
MOSI (SO)
MISO (SI)
Figure 3. Typical Operating Circuit
8
CH4*
CH5*
CH6*
CH7*
ZERO
18pF
CH2
CH3
6.5k
RIN
CSWITCH
TRACK
T/H
SWITCH
COM
SSTRB
SHDN
CH0
CH1
COMPARATOR
CHOLD
INPUT
MUX –
+
VSS
HOLD
AT THE SAMPLING INSTANT,
THE MUX INPUT SWITCHES
FROM THE SELECTED IN+
CHANNEL TO THE SELECTED
IN- CHANNEL.
SINGLE-ENDED MODE: IN+ = CHO–CH7, IN- = COM.
DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS OF
CH0/CH1, CH2/CH3, CH4*/CH5*, CH6*/CH7*.
*MAX1112 ONLY
Figure 4. Equivalent Input Circuit
_______________________________________________________________________________________
+5V, Low-Power, Multi-Channel,
Serial 8-Bit ADCs
MAX1112/MAX1113
Table 1a. MAX1112 Channel Selection in Single-Ended Mode (SGL/DIF = 1)
SEL2
SEL1
SEL0
CH0
0
0
0
+
1
0
0
0
0
1
1
0
1
0
1
0
1
1
0
0
1
1
1
1
1
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
–
+
–
+
–
+
–
+
–
+
–
+
–
+
–
Table 1b. MAX1112 Channel Selection in Differential Mode (SGL/DIF = 0)
SEL2
SEL1
SEL0
CH0
CH1
0
0
0
+
–
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
–
CH2
CH3
+
–
CH4
CH5
+
–
CH6
CH7
+
–
–
+
+
–
+
–
+
Table 2a. MAX1113 Channel Selection in Single-Ended Mode (SGL/DIF = 1)
SEL2
SEL1
SEL0
CH0
0
0
X
+
1
0
X
0
1
X
1
1
X
CH1
CH2
CH3
COM
–
+
–
+
–
+
–
Table 2b. MAX1113 Channel Selection in Differential Mode (SGL/DIF = 0)
SEL2
SEL1
SEL0
CH0
CH1
0
0
X
+
–
0
1
X
1
0
X
–
+
1
1
X
CH2
CH3
+
–
–
+
_______________________________________________________________________________________
9
MAX1112/MAX1113
+5V, Low-Power, Multi-Channel,
Serial 8-Bit ADCs
The time required for the T/H to acquire an input signal
is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens, and more time must be
allowed between conversions. The acquisition time,
tACQ, is the minimum time needed for the signal to be
acquired. It is calculated by:
tACQ = 6 x (RS + RIN) x 18pF
where RIN = 6.5kΩ, RS = the source impedance of the
input signal, and tACQ is never less than 1µs. Note that
source impedances below 2.4kΩ do not significantly
affect the AC performance of the ADC.
Input Bandwidth
The ADC’s input tracking circuitry has a 1.5MHz smallsignal bandwidth, so it is possible to digitize highspeed transient events and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. To avoid highfrequency signals being aliased into the frequency
band of interest, anti-alias filtering is recommended.
Analog Inputs
Internal protection diodes, which clamp the analog
input to VDD and AGND, allow the channel input pins to
swing from (AGND - 0.3V) to (VDD + 0.3V) without dam-
age. However, for accurate conversions near full scale,
the inputs must not exceed VDD by more than 50mV or
be lower than AGND by 50mV.
If the analog input exceeds 50mV beyond the supplies, do not forward bias the protection diodes of
off channels over 2mA.
The MAX1112/MAX1113 can be configured for differential or single-ended inputs with bits 2 and 3 of the control byte (Table 3). In single-ended mode, analog inputs
are internally referenced to COM with a full-scale input
range from COM to VREFIN + COM. For bipolar operation, set COM to VREFIN / 2.
In differential mode, choosing unipolar mode sets the
differential input range at 0V to VREFIN. In unipolar
mode, the output code is invalid (code zero) when a
negative differential input voltage is applied. Bipolar
mode sets the differential input range to ±VREFIN / 2.
Note that in this mode, the common-mode input range
includes both supply rails. Refer to Table 4 for input
voltage ranges.
Quick Look
To quickly evaluate the MAX1112/MAX1113’s analog
performance, use the circuit of Figure 5. The
MAX1112/MAX1113 require a control byte to be written
to DIN before each conversion. Tying DIN to +5V feeds
Table 3. Control-Byte Format
10
BIT 7
(MSB)
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
(LSB)
START
SEL2
SEL1
SEL0
UNI/BIP
SGL/DIF
PD1
PD0
BIT
NAME
7 (MSB)
START
6
5
4
SEL2
SEL1
SEL0
3
UNI/BIP
1 = unipolar, 0 = bipolar. Selects unipolar or bipolar conversion mode (Table 4).
2
SGL/DIF
1 = single ended, 0 = differential. Selects single-ended or differential conversions. In singleended mode, input signal voltages are referred to COM. In differential mode, the voltage difference between two channels is measured. See Tables 1 and 2.
1
PD1
1 = fully operational, 0 = power-down.
Selects fully operational or power-down mode.
0 (LSB)
PD0
1 = external clock mode, 0 = internal clock mode.
Selects external or internal clock mode.
DESCRIPTION
The first logic “1” bit after CS goes low defines the beginning of the control byte.
Select which of the input channels are to be used for the conversion (Tables 1 and 2).
______________________________________________________________________________________
+5V, Low-Power, Multi-Channel,
Serial 8-Bit ADCs
UNIPOLAR MODE
BIPOLAR MODE
Full Scale
Zero Scale
Positive
Full Scale
Zero
Scale
Negative
Full Scale
VREFIN + COM
COM
+VREFIN / 2
+ COM
COM
-VREFIN / 2
+ COM
in control bytes of $FF (hex), which trigger singleended, unipolar conversions on CH7 (MAX1112) or
CH3 (MAX1113) in external clock mode without powering down between conversions. In external clock mode,
the SSTRB output pulses high for two clock periods
before the most significant bit (MSB) of the 8-bit conversion result is shifted out of DOUT. Varying the analog input alters the output code. A total of 10 clock
cycles is required per conversion. All transitions of the
SSTRB and DOUT outputs occur on SCLK’s falling
edge.
How to Start a Conversion
A conversion is started by clocking a control byte into
DIN. With CS low, each rising edge on SCLK clocks a bit
from DIN into the MAX1112/MAX1113’s internal shift register. After CS falls, the first arriving logic “1” bit at DIN
defines the MSB of the control byte. Until this first start bit
arrives, any number of logic “0” bits can be clocked into
DIN with no effect. Table 3 shows the control-byte format.
The MAX1112/MAX1113 are compatible with
MICROWIRE, SPI, and QSPI devices. For SPI, select the
correct clock polarity and sampling edge in the SPI control registers: set CPOL = 0 and CPHA = 0. MICROWIRE,
SPI, and QSPI all transmit a byte and receive a byte at the
same time. Using the Typical Operating Circuit (Figure 3),
the simplest software interface requires three 8-bit transfers to perform a conversion (one 8-bit transfer to configure the ADC, and two more 8-bit transfers to clock out the
VDD
OSCILLOSCOPE
+5V
0.1µF
1µF
DGND
MAX1112
MAX1113
0V TO
+4.096V
ANALOG 0.01µF
INPUT
CH7 (CH3)
SCLK
AGND
SSTRB
CS
DOUT*
SCLK
COM
+5V
DIN
500kHz
OSCILLATOR
CH1
CH2
CH3
CH4
SSTRB
REFOUT
DOUT
REFIN
SHDN
N.C.
C1
1µF
*FULL-SCALE ANALOG INPUT, CONVERSION RESULT = $FF (HEX)
( ) ARE FOR THE MAX1113.
Figure 5. Quick-Look Circuit
______________________________________________________________________________________
11
MAX1112/MAX1113
Table 4. Full-Scale and Zero-Scale Voltages
+5V, Low-Power, Multi-Channel,
Serial 8-Bit ADCs
MAX1112/MAX1113
8-bit conversion result). Figure 6 shows the MAX1112/
MAX1113 common serial-interface connections.
I/O
CS
SCK
Simple Software Interface
Make sure the CPU’s serial interface runs in master
mode so the CPU generates the serial clock. Choose a
clock frequency from 50kHz to 500kHz.
SCLK
MISO
DOUT
+5V
MAX1112
MAX1113
1) Set up the control byte for external clock mode and
call it TB1. TB1 should be of the format 1XXXXX11
binary, where the Xs denote the particular channel
and conversion mode selected.
2) Use a general-purpose I/O line on the CPU to pull
CS low.
3) Transmit TB1 and, simultaneously, receive a byte
and call it RB1. Ignore RB1.
SS
a) SPI
CS
CS
SCK
SCLK
MISO
DOUT
+5V
MAX1112
MAX1113
SS
4) Transmit a byte of all zeros ($00 hex) and, simultaneously, receive byte RB2.
5) Transmit a byte of all zeros ($00 hex) and, simultaneously, receive byte RB3.
b) QSPI
I/O
CS
6) Pull CS high.
SK
SCLK
SI
DOUT
Figure 7 shows the timing for this sequence. Bytes RB2
and RB3 contain the result of the conversion padded
with two leading zeros and six trailing zeros. The total
conversion time is a function of the serial-clock
frequency and the amount of idle time between 8-bit
transfers. Make sure that the total conversion time does
not exceed 1ms, to avoid excessive T/H droop.
MAX1112
MAX1113
c) MICROWIRE
Figure 6. Common Serial-Interface Connections to the
MAX1112/MAX1113
CS
tACQ
SCLK
1
4
SEL2 SEL1 SEL0 UNI/
BIP
DIN
8
SGL/ PD1
DIF
12
16
20
24
PD0
START
SSTRB
A/D STATE
B7
IDLE
RB3
RB2
RB1
DOUT
B6
ACQUISITION
4µs
B5
B4
B3
B2
B1
B0
FILLED WITH ZEROS
CONVERSION
(fSCLK = 500kHz)
Figure 7. Single-Conversion Timing, External Clock Mode, 24 Clocks
12
______________________________________________________________________________________
IDLE
+5V, Low-Power, Multi-Channel,
Serial 8-Bit ADCs
conversion steps. SSTRB pulses high for two clock
periods after the last bit of the control byte. Successiveapproximation bit decisions are made and appear at
DOUT on each of the next eight SCLK falling edges
(Figure 7). After the eight data bits are clocked out,
subsequent clock pulses clock out zeros from the
DOUT pin.
SSTRB and DOUT go into a high-impedance state
when CS goes high; after the next CS falling edge,
SSTRB outputs a logic low. Figure 9 shows the SSTRB
timing in external clock mode.
The conversion must complete in 1ms, or droop on the
sample-and-hold capacitors may degrade conversion
results. Use internal clock mode if the serial-clock frequency is less than 50kHz, or if serial-clock interruptions
could cause the conversion interval to exceed 1ms.
Clock Modes
The MAX1112/MAX1113 can use either an external serial clock or the internal clock to perform the successiveapproximation conversion. In both clock modes, the
external clock shifts data in and out of the devices. Bit
PD0 of the control byte programs the clock mode.
Figures 8–11 show the timing characteristics common
to both modes.
External Clock
In external clock mode, the external clock not only
shifts data in and out, it also drives the analog-to-digital
CS
•••
tCSS
tCL
tCH
SCLK
tCSH
•••
tDS
tDH
•••
DIN
tDO
tDV
tDO
tTR
•••
DOUT
Figure 8. Detailed Serial-Interface Timing
CS
•••
•••
tSTR
tSDV
SSTRB
•••
•••
tSSTRB
SCLK
tSSTRB
••••
••••
PD0 CLOCKED IN
Figure 9. External Clock Mode SSTRB Detailed Timing
______________________________________________________________________________________
13
MAX1112/MAX1113
Digital Output
In unipolar input mode, the output is straight binary
(Figure 15). For bipolar inputs, the output is two’s-complement (Figure 16). Data is clocked out at SCLK’s
falling edge in MSB-first format.
MAX1112/MAX1113
+5V, Low-Power, Multi-Channel,
Serial 8-Bit ADCs
CS
SCLK
DIN
1
4
5
SEL2 SEL1 SEL0
UNI/
BIP
2
3
7
8
SGL/
DIF PD1
PD0
6
9
10
11
12
15
16
17
18
START
SSTRB
tCONV
DOUT
A/D STATE
B7
B6
B1
B0
FILLED WITH
ZEROS
CONVERSION
25µs TYP
IDLE
IDLE
tACQ
4µs (fSCLK = 500kHz)
Figure 10. Internal Clock Mode Timing
CS
tCONV
tCSS
tSCK
tCSH
SSTRB
tSSTRB
SCLK
PD0 CLOCK IN
NOTE: FOR BEST NOISE PERFORMANCE, KEEP SCLK LOW DURING CONVERSION.
Figure 11. Internal Clock Mode SSTRB Detailed Timing
Internal Clock
Internal clock mode frees the µP from the burden of
running the SAR conversion clock. This allows the conversion results to be read back at the processor’s convenience, at any clock rate up to 2MHz. SSTRB goes
low at the start of the conversion and then goes high
when the conversion is complete. SSTRB is low for
25µs (typically), during which time SCLK should remain
low for best noise performance.
An internal register stores data when the conversion is
in progress. SCLK clocks the data out of this register at
any time after the conversion is complete. After SSTRB
goes high, the second falling clock edge produces the
MSB of the conversion at DOUT, followed by the
14
remaining bits in MSB-first format (Figure 10). CS does
not need to be held low once a conversion is started.
Pulling CS high prevents data from being clocked into
the MAX1112/MAX1113 and three-states DOUT, but it
does not adversely affect an internal clock-mode conversion already in progress. When internal clock mode
is selected, SSTRB does not go into a high-impedance
state when CS goes high.
Figure 11 shows the SSTRB timing in internal clock
mode. In this mode, data can be shifted in and out of
the MAX1112/MAX1113 at clock rates up to 2MHz, provided that the minimum acquisition time, tACQ, is kept
above 1µs.
______________________________________________________________________________________
+5V, Low-Power, Multi-Channel,
Serial 8-Bit ADCs
MAX1112/MAX1113
CS
1
8
10
1
8
10
1
8
10
1
SCLK
S
DIN
CONTROL BYTE 0
S
B7
DOUT
S
CONTROL BYTE 1
B0
B7
B0
CONVERSION RESULT 1
CONVERSION RESULT 0
S
CONTROL BYTE 2
CONTROL BYTE 3
B7
CONVERSION RESULT 2
SSTRB
Figure 12a. Continuous Conversions, External Clock Mode, 10 Clocks/Conversion Timing
CS
SCLK
DIN
DOUT
S
S
CONTROL BYTE 0
B7
CONTROL BYTE 1
B0
CONVERSION RESULT 0
B7
CONVERSION RESULT 1
Figure 12b. Continuous Conversions, External Clock Mode, 16 Clocks/Conversion Timing
Data Framing
The falling edge of CS does not start a conversion. The
first logic high clocked into DIN is interpreted as a start
bit and defines the first bit of the control byte. A conversion starts on the falling edge of SCLK, after the eighth
bit of the control byte (the PD0 bit) is clocked into DIN.
The start bit is defined as:
The first high bit clocked into DIN with CS low any
time the converter is idle, e.g., after VDD is applied.
OR
The first high bit clocked into DIN after the MSB of a
conversion in progress is clocked onto the DOUT
pin.
If CS is toggled before the current conversion is complete, then the next high bit clocked into DIN is recognized as a start bit; the current conversion is
terminated, and a new one is started.
The fastest the MAX1112/MAX1113 can run is 10
clocks per conversion. Figure 12a shows the serialinterface timing necessary to perform a conversion
every 10 SCLK cycles in external clock mode.
Many microcontrollers require that conversions occur in
multiples of eight SCLK clocks; 16 clocks per conversion is typically the fastest that a microcontroller can
drive the MAX1112/MAX1113. Figure 12b shows the
serial-interface timing necessary to perform a conversion every 16 SCLK cycles in external clock mode.
______________________________________________________________________________________
15
__________Applications Information
Power-On Reset
When power is first applied, and if SHDN is not pulled
low, internal power-on reset circuitry activates the
MAX1112/MAX1113 in internal clock mode. SSTRB is
high on power-up and, if CS is low, the first logical 1 on
DIN is interpreted as a start bit. Until a conversion takes
place, DOUT shifts out zeros. No conversions should
be performed until the reference voltage has stabilized
(see the Wakeup Time specifications in the Timing
Characteristics).
Hard-Wired Power-Down
Pulling SHDN low places the converters in hard-wired
power-down. Unlike software power-down, the conversion is not completed; it stops coincidentally with SHDN
being brought low. SHDN also controls the state of the
internal reference (Table 5). Letting SHDN float enables
the internal 4.096V voltage reference. When returning to
normal operation with SHDN floating, there is a tRC
delay of approximately 1MΩ x CLOAD, where CLOAD is
the capacitive loading on the SHDN pin. Pulling SHDN
high disables the internal reference, which saves power
when using an external reference.
Power-Down
External Reference
When operating at speeds below the maximum sampling rate, the MAX1112/MAX1113’s automatic powerdown mode can save considerable power by placing
the converters in a low-current shutdown state between
conversions. Figure 13 shows the average supply current as a function of the sampling rate.
Select power-down with PD1 of the DIN control byte
with SHDN high or floating (Table 3). Pull SHDN low at
any time to shut down the converters completely. SHDN
overrides PD1 of the control byte. Figures 14a and 14b
illustrate the various power-down sequences in both
external and internal clock modes.
An external reference between 1V and VDD should be
connected directly at the REFIN terminal. The DC input
impedance at REFIN is extremely high, consisting of
leakage current only (typically 10nA). During a conversion, the reference must be able to deliver up to 20µA
average load current and have an output impedance of
1kΩ or less at the conversion clock frequency. If the
reference has higher output impedance or is noisy,
bypass it close to the REFIN pin with a 0.1µF capacitor.
If an external reference is used with the MAX1112/
MAX1113, tie SHDN to VDD to disable the internal reference and decrease power consumption.
Table 5. Hard-Wired Power-Down and
Internal Reference State
16
SHDN
STATE
DEVICE
MODE
INTERNAL
REFERENCE
1
Enabled
Disabled
Floating
Enabled
Enabled
0
Power-Down
Disabled
1000
MAX1112/13-fig13
Software Power-Down
Software power-down is activated using bit PD1 of the
control byte. When software power-down is asserted, the
ADCs continue to operate in the last specified clock
mode until the conversion is complete. The ADCs then
power down into a low quiescent-current state. In internal
clock mode, the interface remains active, and conversion
results may be clocked out after the MAX1112/
MAX1113 have entered a software power-down.
The first logical 1 on DIN is interpreted as a start bit,
which powers up the MAX1112/MAX1113. If the DIN byte
contains PD1 = 1, then the chip remains powered up. If
PD1 = 0, power-down resumes after one conversion.
SUPPLY CURRENT (µA)
MAX1112/MAX1113
+5V, Low-Power, Multi-Channel,
Serial 8-Bit ADCs
CLOAD = 60pF
CODE = 10101010
100
CLOAD = 30pF
CODE = 10101010
CLOAD = 30pF
CODE = 11111111
VDD = VREFIN = 5V
CLOAD AT DOUT + SSTRB
10
0
10
20
30
40
50
SAMPLING RATE (ksps)
Figure 13. Average Supply Current vs. Sampling Rate
______________________________________________________________________________________
+5V, Low-Power, Multi-Channel,
Serial 8-Bit ADCs
INTERNAL
EXTERNAL
MAX1112/MAX1113
CLOCK
MODE
EXTERNAL
SHDN
SETS POWERDOWN MODE
SETS EXTERNAL
CLOCK MODE
DIN
S X X X X X 1 1
S X X X X X 0 1
S X X X X X 1 1
DATA VALID
DATA VALID
DOUT
DATA
INVALID
POWERDOWN
POWERED UP
MODE
SETS EXTERNAL
CLOCK MODE
POWERED
UP
POWERDOWN
POWERED UP
Figure 14a. Power-Down Modes, External Clock Timing Diagram
INTERNAL CLOCK MODE
SETS POWER-DOWN MODE
SETS INTERNAL
CLOCK MODE
DIN
S X X X X X 1 0
S X X X X X 0 0
MODE
DATA VALID
DATA VALID
DOUT
SSTRB
S
CONVERSION
CONVERSION
POWERED UP
POWER-DOWN
POWERED
UP
Figure 14b. Power-Down Modes, Internal Clock Timing Diagram
Internal Reference
Transfer Function
To use the MAX1112/MAX1113 with the internal reference, connect REFIN to REFOUT. The full-scale range
of the MAX1112/MAX1113 with the internal reference is
typically 4.096V with unipolar inputs, and ±2.048V with
bipolar inputs. The internal reference should be
bypassed to AGND with a 1µF capacitor placed as
close to the REFIN pin as possible.
Table 4 shows the full-scale voltage ranges for unipolar
and bipolar modes. Figure 15 depicts the nominal,
unipolar I/O transfer function, and Figure 16 shows the
bipolar I/O transfer function when using a 4.096V reference. Code transitions occur at integer LSB values.
Output coding is binary, with 1LSB = 16mV
(4.096V/256) for unipolar operation and 1LSB = 16mV
[(4.096V/2 - -4.096V/2)/256] for bipolar operation.
______________________________________________________________________________________
17
MAX1112/MAX1113
+5V, Low-Power, Multi-Channel,
Serial 8-Bit ADCs
OUTPUT CODE
FULL-SCALE
TRANSITION
11111111
SUPPLIES
11111110
+5V
11111101
FS = VREFIN + COM
V
1LSB = REFIN
256
GND
R* = 10Ω
00000011
VDD
00000010
AGND
DGND
+5V
DGND
00000001
00000000
0
1
2
(COM)
3
MAX1112
MAX1113
FS
INPUT VOLTAGE (LSB)
FS - 1LSB
Figure 15. Unipolar Transfer Function
DIGITAL
CIRCUITRY
* OPTIONAL
Figure 17. Power-Supply Grounding Connections
Layout, Grounding, and Bypassing
OUTPUT CODE
01111111
01111110
00000010
00000001
00000000
VREFIN
+ COM
2
VREFIN
COM =
2
-VREFIN
-FS =
+ COM
2
V
1LSB = REFIN
256
+FS =
11111111
11111110
11111101
10000001
10000000
-FS
COM
INPUT VOLTAGE (LSB)
1
+FS - 2 LSB
For best performance, use printed circuit boards. Wirewrap boards are not recommended. Board layout
should ensure that digital and analog signal lines are
separated from each other. Do not run analog and digital (especially clock) lines parallel to one another, or
digital lines underneath the ADC package.
Figure 17 shows the recommended system ground
connections. A single-point analog ground (star ground
point) should be established at AGND, separate from
the logic ground. Connect all other analog grounds and
DGND to the star ground. No other digital system
ground should be connected to this ground. The
ground return to the power supply for the star ground
should be low impedance and as short as possible for
noise-free operation.
High-frequency noise in the VDD power supply may
affect the comparator in the ADC. Bypass the supply to
the star ground with 0.1µF and 1µF capacitors close to
the V DD pin of the MAX1112/MAX1113. Minimize
capacitor lead lengths for best supply-noise rejection. If
the +5V power supply is very noisy, a 10Ω resistor can
be connected to form a lowpass filter.
Figure 16. Bipolar Transfer Function
18
______________________________________________________________________________________
+5V, Low-Power, Multi-Channel,
Serial 8-Bit ADCs
TOP VIEW
CH0 1
20 VDD
CH1 2
19 SCLK
CH0 1
16 VDD
CH2 3
18 CS
CH1 2
15 SCLK
17 DIN
CH2 3
16 SSTRB
CH3 4
CH5 6
15 DOUT
COM 5
12 SSTRB
CH6 7
CH3 4
MAX1112
CH4 5
14 CS
MAX1113
13 DIN
14 DGND
SHDN 6
11 DOUT
CH7 8
13 AGND
REFIN 7
10 DGND
COM 9
12 REFOUT
SHDN 10
11 REFIN
9
REFOUT 8
AGND
DIP/QSOP
DIP/SSOP
Ordering Information (continued)
PART
TEMP. RANGE
PIN-PACKAGE
MAX1112EPP
-40°C to +85°C
20 Plastic DIP
MAX1112EAP
MAX1112MJP
MAX1113CPE
-40°C to +85°C
-55°C to +125°C
0°C to +70°C
20 SSOP
20 CERDIP**
16 Plastic DIP
MAX1113CEE
0°C to +70°C
MAX1113EPE
MAX1113EEE
MAX1113MJE
-40°C to +85°C
-40°C to +85°C
-55°C to +125°C
___________________Chip Information
TRANSISTOR COUNT: 1996
SUBSTRATE CONNECTED TO DGND
16 QSOP
16 Plastic DIP
16 QSOP
16 CERDIP**
**Contact factory for availability.
______________________________________________________________________________________
19
MAX1112/MAX1113
Pin Configurations
QSOP.EPS
________________________________________________________Package Information
SSOP.EPS
MAX1112/MAX1113
+5V, Low-Power, Multi-Channel,
Serial 8-Bit ADCs
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
20 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 1998 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
ANEXOS 3 - Fichas Técnicas do Hardware desenvolvido
MAX233
cxxxvii
19-4323; Rev 10; 8/01
+5V-Powered, Multichannel RS-232
Drivers/Receivers
The MAX220–MAX249 family of line drivers/receivers is
intended for all EIA/TIA-232E and V.28/V.24 communications interfaces, particularly applications where ±12V is
not available.
These parts are especially useful in battery-powered systems, since their low-power shutdown mode reduces
power dissipation to less than 5µW. The MAX225,
MAX233, MAX235, and MAX245/MAX246/MAX247 use
no external components and are recommended for applications where printed circuit board space is critical.
____________________________Features
Superior to Bipolar
♦ Operate from Single +5V Power Supply
(+5V and +12V—MAX231/MAX239)
♦ Low-Power Receive Mode in Shutdown
(MAX223/MAX242)
♦ Meet All EIA/TIA-232E and V.28 Specifications
♦ Multiple Drivers and Receivers
♦ 3-State Driver and Receiver Outputs
♦ Open-Line Detection (MAX243)
Ordering Information
________________________Applications
PART
MAX220CPE
MAX220CSE
MAX220CWE
MAX220C/D
MAX220EPE
MAX220ESE
MAX220EWE
MAX220EJE
MAX220MJE
Portable Computers
Low-Power Modems
Interface Translation
Battery-Powered RS-232 Systems
Multidrop RS-232 Networks
TEMP. RANGE
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-55°C to +125°C
PIN-PACKAGE
16 Plastic DIP
16 Narrow SO
16 Wide SO
Dice*
16 Plastic DIP
16 Narrow SO
16 Wide SO
16 CERDIP
16 CERDIP
Ordering Information continued at end of data sheet.
*Contact factory for dice specifications.
Selection Table
Part
Number
MAX220
MAX222
MAX223 (MAX213)
MAX225
MAX230 (MAX200)
MAX231 (MAX201)
MAX232 (MAX202)
MAX232A
MAX233 (MAX203)
MAX233A
MAX234 (MAX204)
MAX235 (MAX205)
MAX236 (MAX206)
MAX237 (MAX207)
MAX238 (MAX208)
MAX239 (MAX209)
MAX240
MAX241 (MAX211)
MAX242
MAX243
MAX244
MAX245
MAX246
MAX247
MAX248
MAX249
Power
Supply
(V)
+5
+5
+5
+5
+5
+5 and
+7.5 to +13.2
+5
+5
+5
+5
+5
+5
+5
+5
+5
+5 and
+7.5 to +13.2
+5
+5
+5
+5
+5
+5
+5
+5
+5
+5
No. of
RS-232
Drivers/Rx
2/2
2/2
4/5
5/5
5/0
2/2
Nominal
No. of
Cap. Value
Ext. Caps (µF)
4
0.1
4
0.1
4
1.0 (0.1)
0
—
4
1.0 (0.1)
2
1.0 (0.1)
SHDN
& ThreeState
No
Yes
Yes
Yes
Yes
No
Rx
Active in
SHDN
—
—
✔
✔
—
—
Data Rate
(kbps)
120
200
120
120
120
120
2/2
2/2
2/2
2/2
4/0
5/5
4/3
5/3
4/4
3/5
4
4
0
0
4
0
4
4
4
2
1.0 (0.1)
0.1
—
—
1.0 (0.1)
—
1.0 (0.1)
1.0 (0.1)
1.0 (0.1)
1.0 (0.1)
No
No
No
No
No
Yes
Yes
No
No
No
—
—
—
—
—
—
—
—
—
—
120 (64)
200
120
200
120
120
120
120
120
120
5/5
4/5
2/2
2/2
8/10
8/10
8/10
8/9
8/8
6/10
4
4
4
4
4
0
0
0
4
4
1.0
1.0 (0.1)
0.1
0.1
1.0
—
—
—
1.0
1.0
Yes
Yes
Yes
No
No
Yes
Yes
Yes
Yes
Yes
—
—
✔
—
—
✔
✔
✔
✔
✔
120
120
200
200
120
120
120
120
120
120
Features
Ultra-low-power, industry-standard pinout
Low-power shutdown
MAX241 and receivers active in shutdown
Available in SO
5 drivers with shutdown
Standard +5/+12V or battery supplies;
same functions as MAX232
Industry standard
Higher slew rate, small caps
No external caps
No external caps, high slew rate
Replaces 1488
No external caps
Shutdown, three state
Complements IBM PC serial port
Replaces 1488 and 1489
Standard +5/+12V or battery supplies;
single-package solution for IBM PC serial port
DIP or flatpack package
Complete IBM PC serial port
Separate shutdown and enable
Open-line detection simplifies cabling
High slew rate
High slew rate, int. caps, two shutdown modes
High slew rate, int. caps, three shutdown modes
High slew rate, int. caps, nine operating modes
High slew rate, selective half-chip enables
Available in quad flatpack package
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MAX220–MAX249
General Description
MAX220–MAX249
+5V-Powered, Multichannel RS-232
Drivers/Receivers
ABSOLUTE MAXIMUM RATINGS—MAX220/222/232A/233A/242/243
20-Pin Plastic DIP (derate 8.00mW/°C above +70°C) ..440mW
16-Pin Narrow SO (derate 8.70mW/°C above +70°C) ...696mW
16-Pin Wide SO (derate 9.52mW/°C above +70°C)......762mW
18-Pin Wide SO (derate 9.52mW/°C above +70°C)......762mW
20-Pin Wide SO (derate 10.00mW/°C above +70°C)....800mW
20-Pin SSOP (derate 8.00mW/°C above +70°C) ..........640mW
16-Pin CERDIP (derate 10.00mW/°C above +70°C).....800mW
18-Pin CERDIP (derate 10.53mW/°C above +70°C).....842mW
Operating Temperature Ranges
MAX2_ _AC_ _, MAX2_ _C_ _ .............................0°C to +70°C
MAX2_ _AE_ _, MAX2_ _E_ _ ..........................-40°C to +85°C
MAX2_ _AM_ _, MAX2_ _M_ _ .......................-55°C to +125°C
Storage Temperature Range .............................-65°C to +160°C
Lead Temperature (soldering, 10sec) .............................+300°C
Supply Voltage (VCC) ...............................................-0.3V to +6V
Input Voltages
TIN..............................................................-0.3V to (VCC - 0.3V)
RIN (Except MAX220) ........................................................±30V
RIN (MAX220).....................................................................±25V
TOUT (Except MAX220) (Note 1) .......................................±15V
TOUT (MAX220)...............................................................±13.2V
Output Voltages
TOUT ...................................................................................±15V
ROUT .........................................................-0.3V to (VCC + 0.3V)
Driver/Receiver Output Short Circuited to GND.........Continuous
Continuous Power Dissipation (TA = +70°C)
16-Pin Plastic DIP (derate 10.53mW/°C above +70°C)....842mW
18-Pin Plastic DIP (derate 11.11mW/°C above +70°C)....889mW
Note 1: Input voltage measured with TOUT in high-impedance state, SHDN or VCC = 0V.
Note 2: For the MAX220, V+ and V- can have a maximum magnitude of 7V, but their absolute difference cannot exceed 13V.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS—MAX220/222/232A/233A/242/243
(VCC = +5V ±10%, C1–C4 = 0.1µF‚ MAX220, C1 = 0.047µF, C2–C4 = 0.33µF, TA = TMIN to TMAX‚ unless otherwise noted.)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
0.8
V
RS-232 TRANSMITTERS
Output Voltage Swing
All transmitter outputs loaded with 3kΩ to GND
±5
Input Logic Threshold Low
Input Logic Threshold High
Logic Pull-Up/lnput Current
Output Leakage Current
±8
1.4
All devices except MAX220
MAX220: VCC = 5.0V
2
V
1.4
V
2.4
All except MAX220, normal operation
5
40
SHDN = 0V, MAX222/242, shutdown, MAX220
±0.01
±1
VCC = 5.5V, SHDN = 0V, VOUT = ±15V, MAX222/242
±0.01
±10
VCC = SHDN = 0V, VOUT = ±15V
±0.01
±10
200
116
Data Rate
µA
µA
kb/s
Transmitter Output Resistance
VCC = V+ = V- = 0V, VOUT = ±2V
300
10M
Ω
Output Short-Circuit Current
VOUT = 0V
±7
±22
mA
RS-232 RECEIVERS
RS-232 Input Voltage Operating Range
±30
RS-232 Input Threshold Low
VCC = 5V
RS-232 Input Threshold High
VCC = 5V
RS-232 Input Hysteresis
All except MAX243 R2IN
0.8
MAX243 R2IN (Note 2)
-3
1.8
2.4
MAX243 R2IN (Note 2)
-0.5
-0.1
0.5
1
All except MAX243, VCC = 5V, no hysteresis in shdn.
0.2
MAX243
1
3
V
V
5
7
kΩ
0.2
0.4
V
TTL/CMOS Output Voltage Low
IOUT = 3.2mA
TTL/CMOS Output Voltage High
IOUT = -1.0mA
3.5
VCC - 0.2
Sourcing VOUT = GND
-2
-10
Shrinking VOUT = VCC
10
30
TTL/CMOS Output Short-Circuit Current
V
All except MAX243 R2IN
RS-232 Input Resistance
2
1.3
V
_______________________________________________________________________________________
V
mA
+5V-Powered, Multichannel RS-232
Drivers/Receivers
(VCC = +5V ±10%, C1–C4 = 0.1µF‚ MAX220, C1 = 0.047µF, C2–C4 = 0.33µF, TA = TMIN to TMAX‚ unless otherwise noted.)
PARAMETER
CONDITIONS
TTL/CMOS Output Leakage Current
SHDN = VCC or EN = VCC (SHDN = 0V for MAX222),
0V ≤ VOUT ≤ VCC
EN Input Threshold Low
MAX242
EN Input Threshold High
MAX242
2.0
Operating Supply Voltage
3kΩ load
both inputs
MAX220
UNITS
±0.05
±10
µA
1.4
0.8
V
1.4
V
5.5
0.5
2
4
10
MAX220
12
MAX222/232A/233A/242/243
15
TA = +25°C
0.1
10
TA = 0°C to +70°C
2
50
TA = -40°C to +85°C
2
50
TA = -55°C to +125°C
35
100
MAX222/242
SHDN Input Leakage Current
MAX222/242
SHDN Threshold Low
MAX222/242
SHDN Threshold High
MAX222/242
CL = 50pF to 2500pF,
MAX222/232A/233A/242/243
RL = 3kΩ to 7kΩ,
VCC = 5V, TA = +25°C,
measured from +3V MAX220
to -3V or -3V to +3V
MAX222/232A/233A/242/243
tPHLT
MAX220
Transmitter Propagation Delay
TLL to RS-232 (normal operation),
Figure 1
MAX
MAX222/232A/233A/242/243
Shutdown Supply Current
Transition Slew Rate
TYP
4.5
No load
VCC Supply Current (SHDN = VCC),
Figures 5, 6, 11, 19
MIN
1.4
V
mA
µA
±1
µA
0.8
V
2.0
1.4
V
6
12
30
1.5
3
30
1.3
3.5
V/µs
4
10
1.5
3.5
5
10
MAX222/232A/233A/242/243
0.5
1
MAX220
0.6
3
MAX222/232A/233A/242/243
0.6
1
MAX220
0.8
3
tPHLS
MAX242
0.5
10
tPLHS
MAX242
2.5
10
Receiver-Output Enable Time, Figure 3 tER
MAX242
125
500
ns
Receiver-Output Disable Time, Figure 3 tDR
MAX242
160
500
ns
Transmitter-Output Enable Time
(SHDN goes high), Figure 4
tET
MAX222/242, 0.1µF caps
(includes charge-pump start-up)
250
µs
Transmitter-Output Disable Time
(SHDN goes low), Figure 4
tDT
MAX222/242, 0.1µF caps
600
ns
Transmitter + to - Propagation
Delay Difference (normal operation)
tPHLT - tPLHT
MAX222/232A/233A/242/243
300
MAX220
2000
Receiver + to - Propagation
Delay Difference (normal operation)
tPHLR - tPLHR
MAX222/232A/233A/242/243
100
MAX220
225
Receiver Propagation Delay
RS-232 to TLL (normal operation),
Figure 2
Receiver Propagation Delay
RS-232 to TLL (shutdown), Figure 2
tPLHT
tPHLR
tPLHR
MAX222/232A/233A/242/243
MAX220
µs
µs
µs
ns
ns
Note 3: MAX243 R2OUT is guaranteed to be low when R2IN is ≥ 0V or is floating.
_______________________________________________________________________________________
3
MAX220–MAX249
ELECTRICAL CHARACTERISTICS—MAX220/222/232A/233A/242/243 (continued)
__________________________________________Typical Operating Characteristics
MAX220/MAX222/MAX232A/MAX233A/MAX242/MAX243
VCC = ±5V
NO LOAD ON
TRANSMITTER OUTPUTS
(EXCEPT MAX220, MAX233A)
2
0
0.1µF
V- LOADED, NO LOAD ON V+
-2
1µF
0.1µF
-4
10
ALL CAPS
1µF
9
VCC = +5.25V
8
ALL CAPS
0.1µF
7
+10V
1µF CAPS
V+
V+, V- VOLTAGE (V)
4
OUTPUT LOAD CURRENT
FLOWS FROM V+ TO V-
MAX220-02
6
EITHER V+ OR V- LOADED
OUTPUT CURRENT (mA)
1µF
8
11
MAX220-01
10
MAX222/MAX242
ON-TIME EXITING SHUTDOWN
VCC = +4.75V
+5V
+5V
V+
0.1µF CAPS
SHDN
0V
0V
1µF CAPS
6
-6
V+ LOADED, NO LOAD ON V-
-10
0
5
10
15
LOAD CURRENT (mA)
4
0.1µF CAPS
5
-8
20
25
V4
V-
-10V
0
10
20
30
40
50
60
500µs/div
DATA RATE (kbits/sec)
_______________________________________________________________________________________
MAX220-03
AVAILABLE OUTPUT CURRENT
vs. DATA RATE
OUTPUT VOLTAGE vs. LOAD CURRENT
OUTPUT VOLTAGE (V)
MAX220–MAX249
+5V-Powered, Multichannel RS-232
Drivers/Receivers
+5V-Powered, Multichannel RS-232
Drivers/Receivers
20-Pin Wide SO (derate 10 00mW/°C above +70°C).......800mW
24-Pin Wide SO (derate 11.76mW/°C above +70°C).......941mW
28-Pin Wide SO (derate 12.50mW/°C above +70°C) .............1W
44-Pin Plastic FP (derate 11.11mW/°C above +70°C) .....889mW
14-Pin CERDIP (derate 9.09mW/°C above +70°C) ..........727mW
16-Pin CERDIP (derate 10.00mW/°C above +70°C) ........800mW
20-Pin CERDIP (derate 11.11mW/°C above +70°C) ........889mW
24-Pin Narrow CERDIP
(derate 12.50mW/°C above +70°C) ..............1W
24-Pin Sidebraze (derate 20.0mW/°C above +70°C)..........1.6W
28-Pin SSOP (derate 9.52mW/°C above +70°C).............762mW
Operating Temperature Ranges
MAX2 _ _ C _ _......................................................0°C to +70°C
MAX2 _ _ E _ _ ...................................................-40°C to +85°C
MAX2 _ _ M _ _ ...............................................-55°C to +125°C
Storage Temperature Range .............................-65°C to +160°C
Lead Temperature (soldering, 10sec) .............................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS—MAX223/MAX230–MAX241
(MAX223/230/232/234/236/237/238/240/241, VCC = +5V ±10; MAX233/MAX235, VCC = 5V ±5%‚ C1–C4 = 1.0µF; MAX231/MAX239,
VCC = 5V ±10%; V+ = 7.5V to 13.2V; TA = TMIN to TMAX; unless otherwise noted.)
PARAMETER
Output Voltage Swing
CONDITIONS
All transmitter outputs loaded with 3kΩ to ground
MIN
TYP
±5.0
±7.3
MAX232/233
VCC Power-Supply Current
No load,
TA = +25°C
V+ Power-Supply Current
MAX223/230/234–238/240/241
10
7
15
0.4
1
MAX231
1.8
5
MAX239
5
15
MAX223
15
50
MAX230/235/236/240/241
1
10
TA = +25°C
Input Logic Threshold Low
TIN; EN, SHDN (MAX233); EN, SHDN (MAX230/235–241)
0.8
TIN
2.0
Input Logic Threshold High
EN, SHDN (MAX223);
EN, SHDN (MAX230/235/236/240/241)
2.4
Logic Pull-Up Current
TIN = 0V
mA
mA
µA
V
V
1.5
-30
UNITS
V
5
MAX231/239
Shutdown Supply Current
Receiver Input Voltage
Operating Range
MAX
200
µA
30
V
_______________________________________________________________________________________
5
MAX220–MAX249
ABSOLUTE MAXIMUM RATINGS—MAX223/MAX230–MAX241
VCC ...........................................................................-0.3V to +6V
V+ ................................................................(VCC - 0.3V) to +14V
V- ............................................................................+0.3V to -14V
Input Voltages
TIN ............................................................-0.3V to (VCC + 0.3V)
RIN......................................................................................±30V
Output Voltages
TOUT ...................................................(V+ + 0.3V) to (V- - 0.3V)
ROUT .........................................................-0.3V to (VCC + 0.3V)
Short-Circuit Duration, TOUT ......................................Continuous
Continuous Power Dissipation (TA = +70°C)
14-Pin Plastic DIP (derate 10.00mW/°C above +70°C)....800mW
16-Pin Plastic DIP (derate 10.53mW/°C above +70°C)....842mW
20-Pin Plastic DIP (derate 11.11mW/°C above +70°C)....889mW
24-Pin Narrow Plastic DIP
(derate 13.33mW/°C above +70°C) ..........1.07W
24-Pin Plastic DIP (derate 9.09mW/°C above +70°C)......500mW
16-Pin Wide SO (derate 9.52mW/°C above +70°C).........762mW
MAX220–MAX249
+5V-Powered, Multichannel RS-232
Drivers/Receivers
ELECTRICAL CHARACTERISTICS—MAX223/MAX230–MAX241 (continued)
(MAX223/230/232/234/236/237/238/240/241, VCC = +5V ±10; MAX233/MAX235, VCC = 5V ±5%‚ C1–C4 = 1.0µF; MAX231/MAX239,
VCC = 5V ±10%; V+ = 7.5V to 13.2V; TA = TMIN to TMAX; unless otherwise noted.)
PARAMETER
RS-232 Input Threshold Low
RS-232 Input Threshold High
CONDITIONS
TA = +25°C,
VCC = 5V
TA = +25°C,
VCC = 5V
Normal operation
SHDN = 5V (MAX223)
SHDN = 0V (MAX235/236/240/241)
MIN
TYP
0.8
1.2
0.6
Normal operation
SHDN = 5V (MAX223)
SHDN = 0V (MAX235/236/240/241)
1.5
1.7
1.5
2.4
0.2
0.5
1.0
V
3
5
7
kΩ
0.4
V
RS-232 Input Resistance
TA = +25°C, VCC = 5V
TTL/CMOS Output Voltage Low
IOUT = 1.6mA (MAX231/232/233, IOUT = 3.2mA)
TTL/CMOS Output Voltage High
IOUT = -1mA
TTL/CMOS Output Leakage Current
0V ≤ ROUT ≤ VCC; EN = 0V (MAX223);
EN = VCC (MAX235–241 )
Receiver Output Enable Time
Normal
operation
MAX223
600
MAX235/236/239/240/241
400
Receiver Output Disable Time
Normal
operation
MAX223
900
MAX235/236/239/240/241
250
Propagation Delay
Normal operation
RS-232 IN to
TTL/CMOS OUT, SHDN = 0V
CL = 150pF
(MAX223)
Transmitter Output Short-Circuit
Current
6
2.4
V
Shutdown (MAX223)
SHDN = 0V,
EN = 5V (R4IN‚ R5IN)
VCC = 5V, no hysteresis in shutdown
Transmitter Output Resistance
UNITS
V
Shutdown (MAX223)
SHDN = 0V,
EN = 5V (R4IN, R5IN)
RS-232 Input Hysteresis
Transition Region Slew Rate
MAX
3.5
0.05
V
±10
ns
0.5
10
4
40
tPLHS
6
40
5.1
30
3
µA
ns
tPHLS
MAX223/MAX230/MAX234–241, TA = +25°C, VCC = 5V,
RL = 3kΩ to 7kΩ‚ CL = 50pF to 2500pF, measured from
+3V to -3V or -3V to +3V
µs
V/µs
MAX231/MAX232/MAX233, TA = +25°C, VCC = 5V,
RL = 3kΩ to 7kΩ, CL = 50pF to 2500pF, measured from
+3V to -3V or -3V to +3V
VCC = V+ = V- = 0V, VOUT = ±2V
VCC - 0.4
4
30
Ω
300
±10
_______________________________________________________________________________________
mA
mA
+5V-Powered, Multichannel RS-232
Drivers/Receivers
TRANSMITTER OUTPUT VOLTAGE (VOH)
vs. LOAD CAPACITANCE AT
DIFFERENT DATA RATES
2 TRANSMITTERS
LOADED
7.2
7.0
6.5
4.5
6.6
TA = +25°C
VCC = +5V
3 TRANSMITTERS LOADED
RL = 3kΩ
C1–C4 = 1µF
6.4
6.2
6.0
0
500
1000
1500
8.0
7.0
3 TRANSMITTERS
LOADED
4 TRANSMITTERS
LOADED
6.0
5.0
4.0
0
2500
2000
500
1000
1500
2000
2500
LOAD CAPACITANCE (pF)
TRANSMITTER OUTPUT
VOLTAGE (VOL) vs. VCC
TRANSMITTER OUTPUT VOLTAGE (VOL)
vs. LOAD CAPACITANCE AT
DIFFERENT DATA RATES
TRANSMITTER OUTPUT VOLTAGE (V+, V-)
vs. LOAD CURRENT
TA = +25°C
VCC = +5V
3 TRANSMITTERS LOADED
RL = 3kΩ
C1–C4 = 1µF
-6.2
-6.4
VOL (V)
-6.6
-7.5
1 TRANSMITTER
LOADED
2 TRANSMITTERS
LOADED
10
8
6
-7.0
TA = +25°C
VCC = +5V
C1–C4 = 1µF
V- LOADED,
V+ AND VNO LOAD
EQUALLY
ON V+
LOADED
4
160kbits/sec
80kbits/sec
20Kkbits/sec
-6.8
MAX220-09
-6.0
MAX220-08
TA = +25°C
C1–C4 = 1µF
TRANSMITTER
LOADS =
3kΩ || 2500pF
2
V+, V- (V)
-7.0
0
-2
V+ LOADED,
NO LOAD
ON V-
-4
-7.2
3 TRANSMITTERS
LOADED
-6
-7.4
-8
5.0
VCC (V)
5.5
ALL TRANSMITTERS UNLOADED
-10
-7.6
-9.0
4.5
2 TRANSMITTERS
LOADED
9.0
LOAD CAPACITANCE (pF)
4 TRANSMITTERS
LOADED
-8.5
SLEW RATE (V/µs)
160kbits/sec
80kbits/sec
20kbits/sec
VCC (V)
-6.5
-8.0
TA = +25°C
VCC = +5V
LOADED, RL = 3kΩ
C1–C4 = 1µF
10.0
6.8
5.5
5.0
-6.0
VOL (V)
VOH (V)
3 TRANSMITTERS
LOADED
TA = +25°C
C1–C4 = 1µF
TRANSMITTER
4 TRANSMITTERS LOADS =
3kΩ || 2500pF
LOADED
7.5
1 TRANSMITTER LOADED
11.0
7.0
1 TRANSMITTER
LOADED
MAX220-07
VOH (V)
8.0
12.0
MAX220-05
7.4
MAX220-04
8.5
TRANSMITTER SLEW RATE
vs. LOAD CAPACITANCE
MAX220-06
TRANSMITTER OUTPUT
VOLTAGE (VOH) vs. VCC
0
500
1000
1500
0
2500
2000
5
10 15 20 25 30 35 40 45 50
CURRENT (mA)
LOAD CAPACITANCE (pF)
V+, V- WHEN EXITING SHUTDOWN
(1µF CAPACITORS)
MAX220-13
V+
O
V-
SHDN*
500ms/div
*SHUTDOWN POLARITY IS REVERSED
FOR NON MAX241 PARTS
_______________________________________________________________________________________
7
MAX220–MAX249
__________________________________________Typical Operating Characteristics
MAX223/MAX230–MAX241
MAX220–MAX249
+5V-Powered, Multichannel RS-232
Drivers/Receivers
ABSOLUTE MAXIMUM RATINGS—MAX225/MAX244–MAX249
Supply Voltage (VCC) ...............................................-0.3V to +6V
Input Voltages
TIN‚ ENA, ENB, ENR, ENT, ENRA,
ENRB, ENTA, ENTB..................................-0.3V to (VCC + 0.3V)
RIN .....................................................................................±25V
TOUT (Note 3).....................................................................±15V
ROUT ........................................................-0.3V to (VCC + 0.3V)
Short Circuit (one output at a time)
TOUT to GND ............................................................Continuous
ROUT to GND............................................................Continuous
Continuous Power Dissipation (TA = +70°C)
28-Pin Wide SO (derate 12.50mW/°C above +70°C) .............1W
40-Pin Plastic DIP (derate 11.11mW/°C above +70°C) ...611mW
44-Pin PLCC (derate 13.33mW/°C above +70°C) ...........1.07W
Operating Temperature Ranges
MAX225C_ _, MAX24_C_ _ ..................................0°C to +70°C
MAX225E_ _, MAX24_E_ _ ...............................-40°C to +85°C
Storage Temperature Range .............................-65°C to +160°C
Lead Temperature (soldering,10sec) ..............................+300°C
Note 4: Input voltage measured with transmitter output in a high-impedance state, shutdown, or VCC = 0V.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS—MAX225/MAX244–MAX249
(MAX225, VCC = 5.0V ±5%; MAX244–MAX249, VCC = +5.0V ±10%, external capacitors C1–C4 = 1µF; TA = TMIN to TMAX; unless otherwise noted.)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
1.4
0.8
V
RS-232 TRANSMITTERS
Input Logic Threshold Low
Input Logic Threshold High
2
Normal operation
Logic Pull-Up/lnput Current
Tables 1a–1d
Data Rate
Tables 1a–1d, normal operation
Output Voltage Swing
All transmitter outputs loaded with 3kΩ to GND
Output Leakage Current (shutdown)
Tables 1a–1d
Shutdown
±5
1.4
V
10
50
±0.01
±1
120
64
±7.5
µA
kbits/sec
V
ENA, ENB, ENT, ENTA, ENTB =
VCC, VOUT = ±15V
±0.01
±25
VCC = 0V,
VOUT = ±15V
±0.01
±25
µA
Transmitter Output Resistance
VCC = V+ = V- = 0V, VOUT = ±2V (Note 4)
300
10M
Ω
Output Short-Circuit Current
VOUT = 0V
±7
±30
mA
RS-232 Input Threshold Low
VCC = 5V
0.8
1.3
RS-232 Input Threshold High
VCC = 5V
RS-232 Input Hysteresis
VCC = 5V
RS-232 RECEIVERS
RS-232 Input Voltage Operating Range
±25
RS-232 Input Resistance
8
1.8
2.4
0.5
1.0
V
3
5
7
kΩ
0.2
0.4
V
IOUT = 3.2mA
TTL/CMOS Output Voltage High
IOUT = -1.0mA
3.5
VCC - 0.2
Sourcing VOUT = GND
-2
-10
Shrinking VOUT = VCC
10
30
TTL/CMOS Output Leakage Current
Normal operation, outputs disabled,
Tables 1a–1d, 0V ≤ VOUT ≤ VCC, ENR_ = VCC
V
0.2
TTL/CMOS Output Voltage Low
TTL/CMOS Output Short-Circuit Current
V
±0.05
_______________________________________________________________________________________
V
V
mA
±0.10
µA
+5V-Powered, Multichannel RS-232
Drivers/Receivers
(MAX225, VCC = 5.0V ±5%; MAX244–MAX249, VCC = +5.0V ±10%, external capacitors C1–C4 = 1µF; TA = TMIN to TMAX; unless otherwise noted.)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
POWER SUPPLY AND CONTROL LOGIC
Operating Supply Voltage
No load
VCC Supply Current
(normal operation)
Shutdown Supply Current
3kΩ loads on
all outputs
MAX225
4.75
5.25
MAX244–MAX249
4.5
5.5
MAX225
10
20
MAX244–MAX249
11
30
MAX225
40
MAX244–MAX249
57
TA = +25°C
8
TA = TMIN to TMAX
50
Leakage current
Control Input
25
±1
Threshold low
1.4
Threshold high
0.8
2.4
1.4
5
10
30
V
mA
µA
µA
V
AC CHARACTERISTICS
Transition Slew Rate
CL = 50pF to 2500pF, RL = 3kΩ to 7kΩ, VCC = 5V,
TA = +25°C, measured from +3V to -3V or -3V to +3V
V/µs
Transmitter Propagation Delay
TLL to RS-232 (normal operation),
Figure 1
tPHLT
1.3
3.5
tPLHT
1.5
3.5
Receiver Propagation Delay
TLL to RS-232 (normal operation),
Figure 2
tPHLR
0.6
1.5
tPLHR
0.6
1.5
Receiver Propagation Delay
TLL to RS-232 (low-power mode),
Figure 2
tPHLS
0.6
10
tPLHS
3.0
10
Transmitter + to - Propagation
Delay Difference (normal operation)
tPHLT - tPLHT
350
ns
Receiver + to - Propagation
Delay Difference (normal operation)
tPHLR - tPLHR
350
ns
µs
µs
µs
Receiver-Output Enable Time, Figure 3 tER
100
500
ns
Receiver-Output Disable Time, Figure 3 tDR
100
500
ns
Transmitter Enable Time
Transmitter Disable Time, Figure 4
tET
tDT
MAX246–MAX249
(excludes charge-pump start-up)
5
µs
MAX225/MAX245–MAX249
(includes charge-pump start-up)
10
ms
100
ns
Note 5: The 300Ω minimum specification complies with EIA/TIA-232E, but the actual resistance when in shutdown mode or VCC =
0V is 10MΩ as is implied by the leakage specification.
_______________________________________________________________________________________
9
MAX220–MAX249
ELECTRICAL CHARACTERISTICS—MAX225/MAX244–MAX249 (continued)
__________________________________________Typical Operating Characteristics
MAX225/MAX244–MAX249
8
V+ AND V- LOADED
EXTERNAL POWER SUPPLY
1µF CAPACITORS
12
10
40kb/s DATA RATE
8 TRANSMITTERS
LOADED WITH 3kΩ
8
6
4
VCC = 5V
EXTERNAL CHARGE PUMP
1µF CAPACITORS
8 TRANSMITTERS
DRIVING 5kΩ AND
2000pF AT 20kbits/sec
2
0
-2
EITHER V+ OR
V- LOADED
2
3
LOAD CAPACITANCE (nF)
4
5
40kb/sec
7.0
60kb/sec
6.0
V+ AND V- LOADED
100kb/sec
200kb/sec
5.5
-8
1
20kb/sec
7.5
V- LOADED
V+ LOADED
-10
0
8.0
6.5
-4
-6
2
VCC = 5V WITH ALL TRANSMITTERS DRIVEN
LOADED WITH 5kΩ
10kb/sec
8.5
V+, V (V)
OUTPUT VOLTAGE (V)
6
14
9.0
MAX220-11
VCC = 5V
4
10
10
MAX220-10
18
16
TRANSMITTER OUTPUT VOLTAGE (V+, V-)
vs. LOAD CAPACITANCE AT
DIFFERENT DATA RATES
OUTPUT VOLTAGE
vs. LOAD CURRENT FOR V+ AND V-
MAX220-12
TRANSMITTER SLEW RATE
vs. LOAD CAPACITANCE
TRANSMITTER SLEW RATE (V/µs)
MAX220–MAX249
+5V-Powered, Multichannel RS-232
Drivers/Receivers
ALL CAPACITIORS 1µF
5.0
0
5
10
15
20
25
LOAD CURRENT (mA)
30
35
0
1
2
3
LOAD CAPACITANCE (nF)
______________________________________________________________________________________
4
5
+5V-Powered, Multichannel RS-232
Drivers/Receivers
MAX220–MAX249
+3V
0V*
+3V
50%
50%
50%
50%
INPUT
INPUT
0V
VCC
OUTPUT
V+
0V
V-
OUTPUT
tPLHT
GND
tPLHR
tPLHS
tPHLR
tPHLS
tPHLT
*EXCEPT FOR R2 ON THE MAX243
WHERE -3V IS USED.
Figure 1. Transmitter Propagation-Delay Timing
Figure 2. Receiver Propagation-Delay Timing
EN
RX OUT
RX IN
1k
RX
VCC - 2V
SHDN
+3V
0V
a) TEST CIRCUIT
150pF
EN INPUT
OUTPUT DISABLE TIME (tDT)
+3V
V+
0V
+5V
EN
OUTPUT ENABLE TIME (tER)
0V
-5V
+3.5V
V-
RECEIVER
OUTPUTS
+0.8V
a) TIMING DIAGRAM
b) ENABLE TIMING
+3V
EN INPUT
EN
1 OR 0
0V
TX
3k
OUTPUT DISABLE TIME (tDR)
VOH
VOH - 0.5V
RECEIVER
OUTPUTS
VOL
50pF
VCC - 2V
VOL + 0.5V
b) TEST CIRCUIT
c) DISABLE TIMING
Figure 3. Receiver-Output Enable and Disable Timing
Figure 4. Transmitter-Output Disable Timing
______________________________________________________________________________________
11
MAX220–MAX249
+5V-Powered, Multichannel RS-232
Drivers/Receivers
Table 1a. MAX245 Control Pin Configurations
ENT
ENR
0
0
Normal Operation
All Active
All Active
0
1
Normal Operation
All Active
All 3-State
1
0
Shutdown
All 3-State
All Low-Power Receive Mode
1
1
Shutdown
All 3-State
All 3-State
OPERATION STATUS
TRANSMITTERS
RECEIVERS
Table 1b. MAX245 Control Pin Configurations
TRANSMITTERS
RECEIVERS
OPERATION
STATUS
TA1–TA4
TB1–TB4
0
Normal Operation
All Active
All Active
All Active
All Active
0
1
Normal Operation
All Active
All Active
RA1–RA4 3-State,
RA5 Active
RB1–RB4 3-State,
RB5 Active
1
0
Shutdown
All 3-State
All 3-State
All Low-Power
Receive Mode
All Low-Power
Receive Mode
1
1
Shutdown
All 3-State
All 3-State
RA1–RA4 3-State,
RA5 Low-Power
Receive Mode
RB1–RB4 3-State,
RB5 Low-Power
Receive Mode
ENT
ENR
0
RA1–RA5
RB1–RB5
Table 1c. MAX246 Control Pin Configurations
12
OPERATION
STATUS
TRANSMITTERS
RECEIVERS
ENA
ENB
TA1–TA4
TB1–TB4
0
0
Normal Operation
All Active
All Active
All Active
All Active
0
1
Normal Operation
All Active
All 3-State
All Active
RB1–RB4 3-State,
RB5 Active
1
0
Shutdown
All 3-State
All Active
RA1–RA4 3-State,
RA5 Active
All Active
1
1
Shutdown
All 3-State
All 3-State
RA1–RA4 3-State,
RA5 Low-Power
Receive Mode
RB1–RB4 3-State,
RA5 Low-Power
Receive Mode
RA1–RA5
______________________________________________________________________________________
RB1–RB5
+5V-Powered, Multichannel RS-232
Drivers/Receivers
TRANSMITTERS
ENTA ENTB ENRA ENRB
OPERATION
STATUS
RECEIVERS
MAX247
TA1–TA4
TB1–TB4
RA1–RA4
RB1–RB5
MAX248
TA1–TA4
TB1–TB4
RA1–RA4
RB1–RB4
TA1–TA3
TB1–TB3
0
0
0
0
Normal Operation
MAX249
All Active
All Active
All Active
RA1–RA5
All Active
RB1–RB5
0
0
0
1
Normal Operation
All Active
All Active
All Active
All 3-State, except
RB5 stays active on
MAX247
0
0
1
0
Normal Operation
All Active
All Active
All 3-State
All Active
0
0
1
1
Normal Operation
All Active
All Active
All 3-State
All 3-State, except
RB5 stays active on
MAX247
0
1
0
0
Normal Operation
All Active
All 3-State
All Active
All Active
0
1
0
1
Normal Operation
All Active
All 3-State
All Active
All 3-State, except
RB5 stays active on
MAX247
0
1
1
0
Normal Operation
All Active
All 3-State
All 3-State
All Active
0
1
1
1
Normal Operation
All Active
All 3-State
All 3-State
All 3-State, except
RB5 stays active on
MAX247
1
0
0
0
Normal Operation
All 3-State
All Active
All Active
All Active
1
0
0
1
Normal Operation
All 3-State
All Active
All Active
All 3-State, except
RB5 stays active on
MAX247
1
0
1
0
Normal Operation
All 3-State
All Active
All 3-State
All Active
1
0
1
1
Normal Operation
All 3-State
All Active
All 3-State
All 3-State, except
RB5 stays active on
MAX247
1
1
0
0
Shutdown
All 3-State
All 3-State
Low-Power
Receive Mode
Low-Power
Receive Mode
1
1
0
1
Shutdown
All 3-State
All 3-State
Low-Power
Receive Mode
All 3-State, except
RB5 stays active on
MAX247
1
1
1
0
Shutdown
All 3-State
All 3-State
All 3-State
Low-Power
Receive Mode
1
1
1
1
Shutdown
All 3-State
All 3-State
All 3-State
All 3-State, except
RB5 stays active on
MAX247
______________________________________________________________________________________
13
MAX220–MAX249
Table 1d. MAX247/MAX248/MAX249 Control Pin Configurations
MAX220–MAX249
+5V-Powered, Multichannel RS-232
Drivers/Receivers
_______________Detailed Description
The MAX220–MAX249 contain four sections: dual
charge-pump DC-DC voltage converters, RS-232 drivers, RS-232 receivers, and receiver and transmitter
enable control inputs.
Dual Charge-Pump Voltage Converter
The MAX220–MAX249 have two internal charge-pumps
that convert +5V to ±10V (unloaded) for RS-232 driver
operation. The first converter uses capacitor C1 to double the +5V input to +10V on C3 at the V+ output. The
second converter uses capacitor C2 to invert +10V to
-10V on C4 at the V- output.
A small amount of power may be drawn from the +10V
(V+) and -10V (V-) outputs to power external circuitry
(see the Typical Operating Characteristics section),
except on the MAX225 and MAX245–MAX247, where
these pins are not available. V+ and V- are not regulated,
so the output voltage drops with increasing load current.
Do not load V+ and V- to a point that violates the minimum ±5V EIA/TIA-232E driver output voltage when
sourcing current from V+ and V- to external circuitry.
When using the shutdown feature in the MAX222,
MAX225, MAX230, MAX235, MAX236, MAX240,
MAX241, and MAX245–MAX249, avoid using V+ and Vto power external circuitry. When these parts are shut
down, V- falls to 0V, and V+ falls to +5V. For applications where a +10V external supply is applied to the V+
pin (instead of using the internal charge pump to generate +10V), the C1 capacitor must not be installed and
the SHDN pin must be tied to VCC. This is because V+
is internally connected to VCC in shutdown mode.
RS-232 Drivers
The typical driver output voltage swing is ±8V when
loaded with a nominal 5kΩ RS-232 receiver and VCC =
+5V. Output swing is guaranteed to meet the EIA/TIA232E and V.28 specification, which calls for ±5V minimum driver output levels under worst-case conditions.
These include a minimum 3kΩ load, VCC = +4.5V, and
maximum operating temperature. Unloaded driver output voltage ranges from (V+ -1.3V) to (V- +0.5V).
Input thresholds are both TTL and CMOS compatible.
The inputs of unused drivers can be left unconnected
since 400kΩ input pull-up resistors to VCC are built in
(except for the MAX220). The pull-up resistors force the
outputs of unused drivers low because all drivers invert.
The internal input pull-up resistors typically source 12µA,
except in shutdown mode where the pull-ups are disabled. Driver outputs turn off and enter a high-impedance state—where leakage current is typically
microamperes (maximum 25µA)—when in shutdown
14
mode, in three-state mode, or when device power is
removed. Outputs can be driven to ±15V. The powersupply current typically drops to 8µA in shutdown mode.
The MAX220 does not have pull-up resistors to force the
outputs of the unused drivers low. Connect unused
inputs to GND or VCC.
The MAX239 has a receiver three-state control line, and
the MAX223, MAX225, MAX235, MAX236, MAX240,
and MAX241 have both a receiver three-state control
line and a low-power shutdown control. Table 2 shows
the effects of the shutdown control and receiver threestate control on the receiver outputs.
The receiver TTL/CMOS outputs are in a high-impedance, three-state mode whenever the three-state enable
line is high (for the MAX225/MAX235/MAX236/MAX239–
MAX241), and are also high-impedance whenever the
shutdown control line is high.
When in low-power shutdown mode, the driver outputs
are turned off and their leakage current is less than 1µA
with the driver output pulled to ground. The driver output
leakage remains less than 1µA, even if the transmitter
output is backdriven between 0V and (VCC + 6V). Below
-0.5V, the transmitter is diode clamped to ground with
1kΩ series impedance. The transmitter is also zener
clamped to approximately V CC + 6V, with a series
impedance of 1kΩ.
The driver output slew rate is limited to less than 30V/µs
as required by the EIA/TIA-232E and V.28 specifications. Typical slew rates are 24V/µs unloaded and
10V/µs loaded with 3Ω and 2500pF.
RS-232 Receivers
EIA/TIA-232E and V.28 specifications define a voltage
level greater than 3V as a logic 0, so all receivers invert.
Input thresholds are set at 0.8V and 2.4V, so receivers
respond to TTL level inputs as well as EIA/TIA-232E and
V.28 levels.
The receiver inputs withstand an input overvoltage up
to ±25V and provide input terminating resistors with
Table 2. Three-State Control of Receivers
PART
SHDN SHDN
EN(R)
RECEIVERS
X
Low
High
EN
__
High Impedance
Active
High Impedance
MAX223
__
Low
High
High
MAX225
__
__
__
Low
High
High Impedance
Active
MAX235
MAX236
MAX240
Low
Low
High
__
__
Low
High
X
High Impedance
Active
High Impedance
______________________________________________________________________________________
+5V-Powered, Multichannel RS-232
Drivers/Receivers
The receiver input hysteresis is typically 0.5V with a
guaranteed minimum of 0.2V. This produces clear output transitions with slow-moving input signals, even
with moderate amounts of noise and ringing. The
receiver propagation delay is typically 600ns and is
independent of input swing direction.
Low-Power Receive Mode
The low-power receive-mode feature of the MAX223,
MAX242, and MAX245–MAX249 puts the IC into shutdown mode but still allows it to receive information. This
is important for applications where systems are periodically awakened to look for activity. Using low-power
receive mode, the system can still receive a signal that
will activate it on command and prepare it for communication at faster data rates. This operation conserves
system power.
Negative Threshold—MAX243
The MAX243 is pin compatible with the MAX232A, differing only in that RS-232 cable fault protection is removed
on one of the two receiver inputs. This means that control
lines such as CTS and RTS can either be driven or left
floating without interrupting communication. Different
cables are not needed to interface with different pieces of
equipment.
The input threshold of the receiver without cable fault
protection is -0.8V rather than +1.4V. Its output goes
positive only if the input is connected to a control line
that is actively driven negative. If not driven, it defaults
to the 0 or “OK to send” state. Normally‚ the MAX243’s
other receiver (+1.4V threshold) is used for the data line
(TD or RD)‚ while the negative threshold receiver is connected to the control line (DTR‚ DTS‚ CTS‚ RTS, etc.).
Other members of the RS-232 family implement the
optional cable fault protection as specified by EIA/TIA232E specifications. This means a receiver output goes
high whenever its input is driven negative‚ left floating‚
or shorted to ground. The high output tells the serial
communications IC to stop sending data. To avoid this‚
the control lines must either be driven or connected
with jumpers to an appropriate positive voltage level.
Shutdown—MAX222–MAX242
On the MAX222‚ MAX235‚ MAX236‚ MAX240‚ and
MAX241‚ all receivers are disabled during shutdown.
On the MAX223 and MAX242‚ two receivers continue to
operate in a reduced power mode when the chip is in
shutdown. Under these conditions‚ the propagation
delay increases to about 2.5µs for a high-to-low input
transition. When in shutdown, the receiver acts as a
CMOS inverter with no hysteresis. The MAX223 and
MAX242 also have a receiver output enable input (EN
for the MAX242 and EN for the MAX223) that allows
receiver output control independent of SHDN (SHDN
for MAX241). With all other devices‚ SHDN (SHDN for
MAX241) also disables the receiver outputs.
The MAX225 provides five transmitters and five
receivers‚ while the MAX245 provides ten receivers and
eight transmitters. Both devices have separate receiver
and transmitter-enable controls. The charge pumps
turn off and the devices shut down when a logic high is
applied to the ENT input. In this state, the supply current drops to less than 25µA and the receivers continue
to operate in a low-power receive mode. Driver outputs
enter a high-impedance state (three-state mode). On
the MAX225‚ all five receivers are controlled by the
ENR input. On the MAX245‚ eight of the receiver outputs are controlled by the ENR input‚ while the remaining two receivers (RA5 and RB5) are always active.
RA1–RA4 and RB1–RB4 are put in a three-state mode
when ENR is a logic high.
Receiver and Transmitter Enable
Control Inputs
The MAX225 and MAX245–MAX249 feature transmitter
and receiver enable controls.
The receivers have three modes of operation: full-speed
receive (normal active)‚ three-state (disabled)‚ and lowpower receive (enabled receivers continue to function
at lower data rates). The receiver enable inputs control
the full-speed receive and three-state modes. The
transmitters have two modes of operation: full-speed
transmit (normal active) and three-state (disabled). The
transmitter enable inputs also control the shutdown
mode. The device enters shutdown mode when all
transmitters are disabled. Enabled receivers function in
the low-power receive mode when in shutdown.
______________________________________________________________________________________
15
MAX220–MAX249
nominal 5kΩ values. The receivers implement Type 1
interpretation of the fault conditions of V.28 and
EIA/TIA-232E.
MAX220–MAX249
+5V-Powered, Multichannel RS-232
Drivers/Receivers
Tables 1a–1d define the control states. The MAX244
has no control pins and is not included in these tables.
The MAX246 has ten receivers and eight drivers with
two control pins, each controlling one side of the
device. A logic high at the A-side control input (ENA)
causes the four A-side receivers and drivers to go into
a three-state mode. Similarly, the B-side control input
(ENB) causes the four B-side drivers and receivers to
go into a three-state mode. As in the MAX245, one Aside and one B-side receiver (RA5 and RB5) remain
active at all times. The entire device is put into shutdown mode when both the A and B sides are disabled
(ENA = ENB = +5V).
The MAX247 provides nine receivers and eight drivers
with four control pins. The ENRA and ENRB receiver
enable inputs each control four receiver outputs. The
ENTA and ENTB transmitter enable inputs each control
four drivers. The ninth receiver (RB5) is always active.
The device enters shutdown mode with a logic high on
both ENTA and ENTB.
The MAX248 provides eight receivers and eight drivers
with four control pins. The ENRA and ENRB receiver
enable inputs each control four receiver outputs. The
ENTA and ENTB transmitter enable inputs control four
drivers each. This part does not have an always-active
receiver. The device enters shutdown mode and transmitters go into a three-state mode with a logic high on
both ENTA and ENTB.
16
The MAX249 provides ten receivers and six drivers with
four control pins. The ENRA and ENRB receiver enable
inputs each control five receiver outputs. The ENTA
and ENTB transmitter enable inputs control three drivers each. There is no always-active receiver. The
device enters shutdown mode and transmitters go into
a three-state mode with a logic high on both ENTA and
ENTB. In shutdown mode, active receivers operate in a
low-power receive mode at data rates up to
20kbits/sec.
__________Applications Information
Figures 5 through 25 show pin configurations and typical operating circuits. In applications that are sensitive
to power-supply noise, VCC should be decoupled to
ground with a capacitor of the same value as C1 and
C2 connected as close as possible to the device.
______________________________________________________________________________________
+5V-Powered, Multichannel RS-232
Drivers/Receivers
MAX220–MAX249
+5V INPUT
C3
TOP VIEW
C5
C1+ 1
1
16 VCC
C1
V+ 2
15 GND
C1- 3
14 T1OUT
C2+ 4
C2- 5
MAX220
MAX232
MAX232A
V- 6
C2
12 R1OUT
9
11 T1IN
-10V
C4
T1OUT 14
RS-232
OUTPUTS
400k
T2OUT 7
10 T2IN
R2OUT
12 R1OUT
CAPACITANCE (µF)
C1 C2 C3 C4
4.7 4.7 10 10
1.0 1.0 1.0 1.0
0.1 0.1 0.1 0.1
6
+5V
TTL/CMOS
INPUTS
DIP/SO
DEVICE
MAX220
MAX232
MAX232A
V-
+5V
400k
10 T2IN
R2IN 8
V+ 2 +10V
3 C14
C2+
+10V TO -10V
5 C2- VOLTAGE INVERTER
13 R1IN
11 T1IN
T2OUT 7
16
VCC
+5V TO +10V
VOLTAGE DOUBLER
C1+
R1IN 13
TTL/CMOS
OUTPUTS
C5
4.7
1.0
0.1
RS-232
INPUTS
5k
R2IN 8
9 R2OUT
5k
GND
15
Figure 5. MAX220/MAX232/MAX232A Pin Configuration and Typical Operating Circuit
+5V INPUT C3
ALL CAPACITORS = 0.1µF
TOP VIEW
C5
17
VCC
3 +10V
C1+
+5V TO +10V
V+
4 C1- VOLTAGE DOUBLER
5
C2+
7 -10V
+10V TO -10V
V6 C2C4
VOLTAGE INVERTER
2
(N.C.) EN 1
(N.C.) EN 1
C1+ 2
19 VCC
17 VCC
V+ 3
18 GND
V+ 3
16 GND
C1- 4
17 T1OUT
C1- 4
15 T1OUT
C2+ 5
14 R1IN
C2- 6
C1+ 2
C2+ 5
C2- 6
18 SHDN
MAX222
MAX242
13 R1OUT
MAX222
MAX242
15 R1IN
V- 7
14 R1OUT
12 T1IN
T2OUT 8
13 N.C.
T2OUT 8
11 T2IN
R2IN 9
12 T1IN
R2OUT 10
11 T2IN
10 R2OUT
DIP/SO
C2
+5V
16 N.C.
V- 7
R2IN 9
C1
20 SHDN
TTL/CMOS
INPUTS
400k
12 T1IN
+5V
(EXCEPT MAX220)
400k
11 T2IN
(EXCEPT MAX220)
T1OUT 15
T2OUT 8
13 R1OUT
R1IN 14
TTL/CMOS
OUTPUTS
SSOP
RS-232
INPUTS
5k
R2IN 9
10 R2OUT
1 (N.C.) EN
( ) ARE FOR MAX222 ONLY.
PIN NUMBERS IN TYPICAL OPERATING CIRCUIT ARE FOR DIP/SO PACKAGES ONLY.
RS-232
OUTPUTS
5k
SHDN
GND
18
16
Figure 6. MAX222/MAX242 Pin Configurations and Typical Operating Circuit
______________________________________________________________________________________
17
MAX220–MAX249
+5V-Powered, Multichannel RS-232
Drivers/Receivers
+5V
TOP VIEW
0.1
+5V
28
VCC
27
VCC
400k
T1IN
3
ENR 1
28 VCC
ENR 2
27 VCC
T1IN 3
26 ENT
T2IN 4
R1OUT 5
4
23 T5IN
R3OUT 7
22 R4OUT
R3IN 8
21 R5OUT
R2IN 9
20 R5IN
R1IN 10
18 T3OUT
T2OUT 12
17 T4OUT
GND 13
16 T5OUT
GND 14
15 T5OUT
T3IN
25
12
T3OUT
+5V
18
400k
T4IN
24
+5V
T4OUT
17
400k
19 R4IN
T1OUT 11
T2OUT
+5V
400k
24 T4IN
R2OUT 6
11
400k
T2IN
25 T3IN
MAX225
T1OUT
+5V
T5OUT
T5IN
23
ENT
26
T5OUT
R1OUT
5
R1IN
16
15
10
5k
SO
R2OUT
6
R2IN
9
5k
R3OUT
7
MAX225 FUNCTIONAL DESCRIPTION
5 RECEIVERS
5 TRANSMITTERS
2 CONTROL PINS
1 RECEIVER ENABLE (ENR)
1 TRANSMITTER ENABLE (ENT)
R3IN
8
R4IN
19
5k
R4OUT
22
5k
R5OUT
21
R5IN
5k
PINS (ENR, GND, VCC, T5OUT) ARE INTERNALLY CONNECTED.
CONNECT EITHER OR BOTH EXTERNALLY. T5OUT IS A SINGLE DRIVER.
1
2
ENR
ENR
GND
13
GND
14
Figure 7. MAX225 Pin Configuration and Typical Operating Circuit
18
______________________________________________________________________________________
20
+5V-Powered, Multichannel RS-232
Drivers/Receivers
MAX220–MAX249
+5V INPUT
TOP VIEW
1.0µF
12
11
VCC
+5V TO +10V
VOLTAGE DOUBLER
C1+
1.0µF
14
C115
C2+
1.0µF
16 C2-
+10V TO -10V
VOLTAGE INVERTER
T1OUT 2
27 R3IN
T2OUT 3
26 R3OUT
R2IN 4
25 SHDN (SHDN)
R2OUT 5
T2IN 6
24 EN (EN)
MAX223
MAX241
T1IN 7
400k
6 T2IN
21 T4IN
R1IN 9
20 T3IN
GND 10
19 R5OUT*
VCC 11
18 R5IN*
C1+ 12
17 V-
V+ 13
16 C2-
C1- 14
15 C2+
Wide SO/
SSOP
RS-232
OUTPUTS
400k
20 T3IN
T3OUT 1
T3
23 R4IN*
R1OUT 8
T2OUT 3
T2
+5V
22 R4OUT*
T1OUT 2
T1
+5V
TTL/CMOS
INPUTS
17
400k
7 T1IN
28 T4OUT
V-
13
1.0µF
+5V
T3OUT 1
1.0µF
V+
+5V
21 T4IN
8 R1OUT
400k
T4
T4OUT 28
R1
R1IN 9
5k
5 R2OUT
R2IN 4
R2
5k
LOGIC
OUTPUTS
26 R3OUT
R3
R3IN
27
R4IN
23
R5IN
18
5k
22 R4OUT
R4
RS-232
INPUTS
5k
19 R5OUT
R5
*R4 AND R5 IN MAX223 REMAIN ACTIVE IN SHUTDOWN
NOTE: PIN LABELS IN ( ) ARE FOR MAX241
5k
24 EN (EN)
GND
SHDN 25
(SHDN)
10
Figure 8. MAX223/MAX241 Pin Configuration and Typical Operating Circuit
______________________________________________________________________________________
19
MAX220–MAX249
+5V-Powered, Multichannel RS-232
Drivers/Receivers
+5V INPUT
TOP VIEW
1.0µF
1.0µF
T3OUT
20 T4OUT
1
T1OUT 2
19 T5IN
T2OUT 3
18 N.C.
T2IN 4
1.0µF
17 SHDN
MAX230
T1IN 5
16 T5OUT
GND 6
15 T4IN
VCC 7
14 T3IN
C1+ 8
13 V-
V+ 9
12 C2-
C1- 10
11 C2+
TTL/CMOS
INPUTS
DIP/SO
7
VCC
V+ 9
+5V TO +10V
VOLTAGE DOUBLER
8 C1+
10 C1-
11
+10V TO -10V
C2+
12
VC2- VOLTAGE INVERTER
+5V
400k
T1OUT
5 T1IN
T1
+5V
400k
T2OUT
4 T2IN
T2
+5V
400k
T3OUT
14 T3IN
T3
+5V
400k
T4OUT
15 T4IN
T4
+5V
400k
T5OUT
19 T5IN
T5
N.C. x 18
13
1.0µF
2
3
RS-232
OUTPUTS
1
20
16
17
GND
1.0µF
SHDN
6
Figure 9. MAX230 Pin Configuration and Typical Operating Circuit
+5V INPUT
TOP VIEW
+7.5V TO +12V
1.0µF
13 (15)
1
2
1.0µF
C+ 1
CV-
2
3
T2OUT 4
MAX231
R2IN 5
14 V+
C+ 1
16 V+
13 VCC
C- 2
15 VCC
12 GND
V- 3
14 GND
11 T1OUT
T2OUT 4
10 R1IN
R2IN 5
R2OUT 6
9
R1OUT
T2IN 7
8
T1IN
MAX231
13 T1OUT
10 T1IN
N.C. 8
9
N.C.
DIP
SO
C1-
V+
V-
8
T1IN
C2
1.0µF
(13)
+5V
TTL/CMOS
INPUTS
RS-232
OUTPUTS
400k
(11)
7
T2IN
9
R1OUT
T2OUT 4
T2
R1IN 10
R1
TTL/CMOS
OUTPUTS
5k
6 R2OUT
R2IN 5
R2
(12)
RS-232
INPUTS
GND
12 (14)
Figure 10. MAX231 Pin Configurations and Typical Operating Circuit
20
(16)
3
T1OUT 11
T1
5k
PIN NUMBERS IN ( ) ARE FOR SO PACKAGE
14
400k
(10)
11 R1OUT
T2IN 7
C1+
+5V
12 R1IN
R2OUT 6
VCC
+12V TO -12V
VOLTAGE CONVERTER
______________________________________________________________________________________
+5V-Powered, Multichannel RS-232
Drivers/Receivers
MAX220–MAX249
+5V INPUT
1.0µF
TOP VIEW
7
VCC
+5V
400k
T2IN
20 R2OUT
1
T1IN 2
19 R2IN
R1OUT 3
GND 6
17 V-
MAX233
MAX233A
14 V+ (C1-)
(V+) C1+ 8
12 V- (C2+)
(V-) CS- 10
RS-232
OUTPUTS
400k
1
T2IN
3
R1OUT
T2OUT
18
R1IN 4
11 C2+ (C2-)
DIP/SO
5k
TTL/CMOS
OUTPUTS
20 R2OUT
13 C1- (C1+)
GND 9
+5V
16 C215 C2+
VCC 7
T1OUT 5
T1IN
TTL/CMOS
INPUTS
18 T2OUT
R1IN 4
T1OUT 5
2
8 (13)
DO NOT MAKE
CONNECTIONS TO 13 (14)
THESE PINS
12 (10)
INTERNAL -10
17
POWER SUPPLY
INTERNAL +10V
POWER SUPPLY
RS-232
OUTPUTS
R2IN 19
5k
C1+
C1-
C2+
V-
C2-
V14 (8) V+
11 (12)
C2+
15
16
10 (11)
C2GND
GND
6
9
( ) ARE FOR SO PACKAGE ONLY.
Figure 11. MAX233/MAX233A Pin Configuration and Typical Operating Circuit
+5V INPUT
1.0µF
TOP VIEW
7
1.0µF
9
10
T1OUT 1
16 T3OUT
T2OUT 2
15 T4OUT
T2IN 3
T1IN 4
1.0µF
C1C2+
11 C2-
6
VCC
+5V TO +10V
VOLTAGE DOUBLER
+10V TO -10V
VOLTAGE INVERTER
VCC 6
13 T3IN
10 C2+
9
V+ 8
C1-
V-
12
1.0µF
T1
T1OUT 1
+5V
400k
3 T2IN
11 C2-
C1+ 7
V+
400k
4 T1IN
12 V-
GND 5
1.0µF
8
+5V
14 T4IN
MAX234
C1+
T2
T2OUT 3
+5V
TTL/CMOS
INPUTS
RS-232
OUTPUTS
400k
13 T3IN
T3
T3OUT 16
+5V
DIP/SO
400k
14 T4IN
T4
T4OUT 15
GND
5
Figure 12. MAX234 Pin Configuration and Typical Operating Circuit
______________________________________________________________________________________
21
MAX220–MAX249
+5V-Powered, Multichannel RS-232
Drivers/Receivers
+5V INPUT
TOP VIEW
1.0µF
12
VCC
+5V
400k
8 T1IN
T1
T1OUT 3
T2
T2OUT 4
+5V
400k
7 T2IN
+5V
400k
TTL/CMOS
INPUTS
T4OUT 1
24 R3IN
T3OUT 2
23 R3OUT
T1OUT 3
22 T5IN
T2OUT 4
21 SHDN
R2IN 5
MAX235
R2OUT 6
15 T3IN
T3OUT 2
T3
RS-232
OUTPUTS
+5V
400k
16 T4IN
+5V
20 EN
22 T5IN
T4OUT 1
T4
400k
T5OUT 19
T5
19 T5OUT
T2IN 7
18 R4IN
T1IN 8
17 R4OUT
R1OUT 9
16 T4IN
R1IN 10
15 T3IN
GND 11
14 R5OUT
VCC 12
13 R5IN
DIP
9 R1OUT
R1IN 10
T1
5k
6 R2OUT
R2IN 5
R2
5k
TTL/CMOS
OUTPUTS
23 R3OUT
R3IN 24
R3
RS-232
INPUTS
5k
17 R4OUT
R4IN 18
R4
5k
14 R5OUT
R5IN 13
R5
5k
20 EN
SHDN
21
GND
11
Figure 13. MAX235 Pin Configuration and Typical Operating Circuit
22
______________________________________________________________________________________
+5V-Powered, Multichannel RS-232
Drivers/Receivers
MAX220–MAX249
TOP VIEW
+5V INPUT
1.0µF
9
10
1.0µF
12
13
1.0µF
1.0µF
VCC
+5V TO +10V
VOLTAGE DOUBLER
C1+
C1-
V+
C2+
V-
+10V TO -10V
VOLTAGE INVERTER
14 C2-
11
15
1.0µF
+5V
400k
7 T1IN
T3OUT 1
24 T4OUT
T1OUT 2
23 R2IN
R1IN 4
R1OUT 5
+5V
400k
6 T2IN
22 R2OUT
T2OUT 3
21 SHDN
MAX236
TTL/CMOS
INPUTS
19 T4IN
T1IN 7
18 T3IN
GND 8
17 R3OUT
VCC 9
16 R3IN
C1+ 10
15 V-
V+ 11
14 C2-
C1- 12
13 C2+
T2OUT
T2
3
RS-232
OUTPUTS
+5V
400k
20 EN
T2IN 6
T1OUT 2
T1
18 T3IN
T3OUT 1
T3
+5V
400k
19 T4IN
5 R1OUT
T4OUT 24
T4
R1IN 4
R1
5k
DIP/SO
TTL/CMOS
OUTPUTS
22 R2OUT
R2
R2IN
23
R3IN
16
RS-232
INPUTS
5k
17 R3OUT
R3
5k
20 EN
SHDN
21
GND
8
Figure 14. MAX236 Pin Configuration and Typical Operating Circuit
______________________________________________________________________________________
23
MAX220–MAX249
+5V-Powered, Multichannel RS-232
Drivers/Receivers
TOP VIEW
+5V INPUT
1.0µF
10
1.0µF
12
13
1.0µF
14
C1+
C1C2+
C2-
24 T4OUT
T1OUT 2
23 R2IN
T2OUT 3
22 R2OUT
R1IN 4
R1OUT 5
MAX237
T2IN 6
19 T4IN
T1IN 7
18 T3IN
GND 8
17 R3OUT
VCC 9
16 R3IN
C1+ 10
15 V-
V+ 11
14 C2-
C1- 12
13 C2+
400k
TTL/CMOS
INPUTS
T2OUT
T2
+5V
20 T5OUT
3
400k
18 T3IN
T3OUT 1
T3
+5V
1.0µF
T1OUT 2
T1
6 T2IN
21 T5IN
15
V-
400k
7 T1IN
+5V
11
V+
+10V TO -10V
VOLTAGE INVERTER
+5V
T3OUT 1
1.0µF
9
VCC
+5V TO +10V
VOLTAGE DOUBLER
RS-232
OUTPUTS
400k
19 T4IN
T4OUT 24
T4
+5V
400k
21 T5IN
DIP/SO
5 R1OUT
T5OUT 20
T5
R1IN 4
R1
5k
TTL/CMOS
OUTPUTS
22 R2OUT
R2
R2IN
23
R3IN
16
5k
17 R3OUT
R3
5k
GND
8
Figure 15. MAX237 Pin Configuration and Typical Operating Circuit
24
______________________________________________________________________________________
RS-232
INPUTS
+5V-Powered, Multichannel RS-232
Drivers/Receivers
MAX220–MAX249
TOP VIEW
+5V INPUT
1.0µF
1.0µF
9
10
1.0µF
12
13
1.0µF
14
VCC
+5V TO +10V
VOLTAGE DOUBLER
C1+
C1C2+
24 T3OUT
T1OUT 2
23 R3IN
R2IN 3
R2OUT 4
T1IN 5
MAX238
20 T4OUT
R1OUT 6
19 T3IN
R1IN 7
18 T2IN
GND 8
17 R4OUT
VCC 9
16 R4IN
C1+ 10
15 V-
V+ 11
14 C2-
C1- 12
13 C2+
6 R1OUT
RS-232
OUTPUTS
T3OUT 24
T3
+5V
1
400k
19 T3IN
21 T4IN
T2OUT
T2
+5V
TTL/CMOS
INPUTS
T1OUT 2
400k
18 T2IN
21 T4IN
1.0µF
T1
+5V
15
400k
5 T1IN
22 R3OUT
V-
+10V TO -10V
VOLTAGE INVERTER
C2+5V
T2OUT 1
V+
11
400k
T4OUT 20
T4
R1IN 7
R1
5k
DIP/SO
4 R2OUT
R2IN
R2
TTL/CMOS
OUTPUTS
3
RS-232
INPUTS
5k
22 R3OUT
R3
R3IN
23
R4IN
16
5k
17 R4OUT
R4
5k
GND
8
Figure 16. MAX238 Pin Configuration and Typical Operating Circuit
______________________________________________________________________________________
25
MAX220–MAX249
+5V-Powered, Multichannel RS-232
Drivers/Receivers
TOP VIEW
7.5V TO 13.2V
INPUT
+5V INPUT
1.0µF
4
6
1.0µF
7
5
VCC
C1+
V+
C1-
+5V
24 T1IN
R1IN 2
23 T2IN
GND 3
22 R2OUT
VCC 4
21 R2IN
V+ 5
MAX239
TTL/CMOS
INPUTS
C+ 6
19 T1OUT
C- 7
18 R3IN
V- 8
17 R3OUT
R5IN 9
16 T3IN
R5OUT 10
15 N.C.
R4OUT 11
14 EN
16 T3IN
1 R1OUT
T1OUT 19
400k
23 T2IN
T2OUT
T2
+5V
20 T2OUT
1.0µF
T1
+5V
8
400k
24 T1IN
R1OUT 1
V-
+10V TO -10V
VOLTAGE INVERTER
20
RS-232
OUTPUTS
400k
T3OUT 13
T3
R1IN 2
R1
5k
22 R2OUT
13 T3OUT
R4IN 12
R2IN 21
R2
5k
DIP/SO
TTL/CMOS
OUTPUTS
17 R3OUT
R3
R3IN
18
R4IN
12
R5IN
9
5k
11 R4OUT
R4
5k
10 R5OUT
R5
5k
14 EN
N.C.
GND
3
Figure 17. MAX239 Pin Configuration and Typical Operating Circuit
26
______________________________________________________________________________________
15
RS-232
INPUTS
+5V-Powered, Multichannel RS-232
Drivers/Receivers
1.0µF
25
19
VCC
+5V TO +10V
VOLTAGE DOUBLER
C1+
1.0µF
27
C128
C2+
1.0µF
29 C2-
400k
N.C.
R2IN
N.C.
T2OUT
T1OUT
T3OUT
T4OUT
R3IN
R3OUT
T5IN
N.C.
+5V
11
10
9
8
7
6
5
4
3
2
1
MAX240
N.C.
N.C.
C1+
V+
C1C2+
C2
VN.C.
N.C.
N.C.
T2OUT
T2
37 T3IN
T3OUT 6
T3
+5V
2 T5IN
16 R1OUT
RS-232
OUTPUTS
400k
38 T4IN
+5V
8
400k
T4OUT 5
T4
400k
T5OUT
T5
41
R1IN 17
R1
5k
13 R2OUT
R2IN 10
R2
23
24
25
26
27
28
29
30
31
32
33
12
13
14
15
16
17
18
19
20
21
22
T1OUT 7
T1
14 T2IN
N.C.
SHDN
EN
T5OUT
R4IN
R4OUT
T4IN
T3IN
R5OUT
R5IN
N.C.
30
1.0µF
+5V
44
43
42
41
40
39
38
37
36
35
34
V-
26
400k
15 T1IN
TTL/CMOS
INPUTS
1.0µF
V+
+5V TO -10V
VOLTAGE INVERTER
+5V
N.C.
R2OUT
T2IN
T1IN
R1OUT
R1IN
GND
VCC
N.C.
N.C.
N.C.
MAX220–MAX249
+5V INPUT
TOP VIEW
5k
TTL/CMOS
OUTPUTS
3 R3OUT
R3
R3IN
4
R4IN
40
R5IN
35
5k
RS-232
INPUTS
Plastic FP
39 R4OUT
R4
5k
36 R5OUT
R5
5k
42 EN
GND
SHDN
43
18
Figure 18. MAX240 Pin Configuration and Typical Operating Circuit
______________________________________________________________________________________
27
MAX220–MAX249
+5V-Powered, Multichannel RS-232
Drivers/Receivers
ALL CAPACITORS = 0.1µF
0.1µF
+5V INPUT
TOP VIEW
0.1µF
1
16 VCC
C1+ 1
V+ 2
0.1µF
3 C14
C2+
0.1µF
5 C2-
15 GND
C1- 3
C2+ 4
C1+
C2- 5
T2OUT 7
10 T2IN
R2IN 8
9
V-
+10V
6
-10V
0.1µF
T1OUT 14
11 T1IN
12 R1OUT
11 T1IN
+10V TO -10V
VOLTAGE INVERTER
2
400k
13 R1IN
V- 6
V+
+5V
14 T1OUT
MAX243
16
VCC
+5V TO +10V
VOLTAGE DOUBLER
+5V
TTL/CMOS
INPUTS
RS-232
OUTPUTS
400k
T2OUT 7
10 T2IN
R2OUT
DIP/SO
12 R1OUT
R1IN 13
TTL/CMOS
OUTPUTS
9 R2OUT
RECEIVER INPUT
≤ -3 V
OPEN
≥ +3V
R1 OUTPUT
HIGH
HIGH
LOW
R2 OUTPUT
HIGH
LOW
LOW
R2IN 8
5k
GND
15
Figure 19. MAX243 Pin Configuration and Typical Operating Circuit
28
RS-232
INPUTS
5k
______________________________________________________________________________________
+5V-Powered, Multichannel RS-232
Drivers/Receivers
MAX220–MAX249
+5V
TOP VIEW
1µF
1µF
20
VCC
+5V TO +10V VOLTAGE DOUBLER
TB4OUT
4
3
2
1
44 43 42 41 40
RB5IN
TB1OUT
TB3OUT
TA1OUT
TB2OUT
TA2OUT
5
TA4OUT
6
1µF
TA3OUT
RA4IN
RA5IN
21
1µF
C1+
23 C124
C2+
25 C2-
22
V+
26
V- 1µF
+10V TO -10V VOLTAGE INVERTER
2 TA1OUT
+5V
+5V
TB1OUT 44
400k
RA3IN
7
39 RB4IN
RA2IN
8
38 RB3IN
RA1IN
9
37 RB2IN
RA1OUT
10
36 RB1IN
RA2OUT
11
35 RB1OUT
RA3OUT
12
RA4OUT
13
33 RB3OUT
RA5OUT
14
32 RB4OUT
TA1IN
15
31 RB5OUT
TA2IN
16
30 TB1IN
TA3IN
17
29 TB2IN
MAX244
PLCC
TB1IN 30
+5V
+5V
2 TA2OUT
TB2OUT 43
400k
16 TA2IN
TB2IN 29
+5V
+5V
3 TA3OUT
TB3OUT 42
400k
17 TA3IN
TB3IN 28
+5V
+5V
4 TA4OUT
TB4OUT 41
400k
18 TA4IN
TB4IN 27
9 RA1IN
RB1IN 36
TB3IN
TB4IN
V-
C2-
C2+
V+
C1-
GND
VCC
19 20 21 22 23 24 25 26 27 28
C1+
18
TA4IN
34 RB2OUT
15 TA1IN
5k
5k
10 RA1OUT
RB1OUT 35
8 RA2IN
MAX249 FUNCTIONAL DESCRIPTION
10 RECEIVERS
5 A-SIDE RECEIVER
5 B-SIDE RECEIVER
8 TRANSMITTERS
4 A-SIDE TRANSMITTERS
4 B-SIDE TRANSMITTERS
NO CONTROL PINS
RB2IN 37
5k
5k
11 RA2OUT
RB2OUT 34
7 RA3IN
RB3IN 38
5k
5k
12 RA3OUT
RB3OUT 33
6 RA4IN
RB4IN 39
5k
5k
13 RA4OUT
RB4OUT 32
5 RA5IN
RB5IN 40
5k
5k
14 RA5OUT
GND
19
RB5OUT 31
Figure 20. MAX244 Pin Configuration and Typical Operating Circuit
______________________________________________________________________________________
29
MAX220–MAX249
+5V-Powered, Multichannel RS-232
Drivers/Receivers
+5V
TOP VIEW
1µF
40
VCC
ENR
40
1
VCC
TA1IN
2
39
ENT
TA2IN
3
38
TB1IN
TA3IN
4
37
TB2IN
TA4IN
5
36
TB3IN
RA5OUT
6
35
TB4IN
RA4OUT
7
34
RB5OUT
MAX245
RA3OUT
8
33
RB4OUT
RA2OUT
9
32
RB3OUT
RA1OUT
10
31
RB2OUT
RA1IN
11
30
RB1OUT
RA2IN
12
29
RB1IN
RA3IN
13
28
RB2IN
RA4IN
14
27
RB3IN
RA5IN
15
26
RB4IN
TA1OUT
16
25
RB5IN
TA2OUT
17
24
TB1OUT
TA3OUT
18
23
TB2OUT
TA4OUT
GND
19
22
TB3OUT
20
21
TB4OUT
+5V
+5V
16 TA1OUT
2 TA1IN
TB1IN 38
+5V
+5V
17 TA2OUT
3 TA2IN
TB2IN 37
+5V
+5V
18 TA3OUT
TB3OUT 22
400k
4 TA3IN
TB3IN 36
+5V
+5V
19 TA4OUT
TB4OUT 21
400k
5 TA4IN
TB4IN 35
1 ENR
ENT 39
11 RA1IN
RB1IN 29
5k
5k
10 RA1OUT
RB1OUT 30
12 RA2IN
RB2IN 28
5k
5k
RB2OUT 31
13 RA3IN
RB3IN 27
5k
5k
MAX245 FUNCTIONAL DESCRIPTION
10 RECEIVERS
5 A-SIDE RECEIVERS (RA5 ALWAYS ACTIVE)
5 B-SIDE RECEIVERS (RB5 ALWAYS ACTIVE)
8 TRANSMITTTERS
4 A-SIDE TRANSMITTERS
2 CONTROL PINS
1 RECEIVER ENABLE (ENR)
1 TRANSMITTER ENABLE (ENT)
TB2OUT 23
400k
9 RA2OUT
DIP
TB1OUT 24
400k
8 RA3OUT
RB3OUT 32
14 RA4IN
RB4IN 26
5k
5k
7 RA4OUT
RB4OUT 33
15 RA5IN
RB5IN 25
5k
5k
6 RA5OUT
RB5OUT 34
GND
20
Figure 21. MAX245 Pin Configuration and Typical Operating Circuit
30
______________________________________________________________________________________
+5V-Powered, Multichannel RS-232
Drivers/Receivers
MAX220–MAX249
+5V
TOP VIEW
1µF
ENA
1
40
VCC
TA1IN
2
39
ENB
TA2IN
3
38
TB1IN
TA3IN
4
37
TB2IN
TA4IN
5
36
TB3IN
RA5OUT
6
RA4OUT
7
RA3OUT
8
MAX246
35
TB4IN
34
RB5OUT
33
RB4OUT
RA2OUT
9
32
RB3OUT
RA1OUT
10
31
RB2OUT
RA1IN
11
30
RB1OUT
RA2IN
12
29
RB1IN
RA3IN
13
28
RB2IN
RA4IN
14
27
RB3IN
RA5IN
15
26
RB4IN
TA1OUT
16
25
RB5IN
TA2OUT
17
24
TB1OUT
TA3OUT
18
23
TB2OUT
TA4OUT
19
22
TB3OUT
GND
20
21
TB4OUT
DIP
40
VCC
+5V
+5V
TB1OUT 24
16 TA1OUT
400k
2 TA1IN
TB1IN 38
+5V
+5V
17 TA2OUT
TB2OUT 23
400k
3 TA2IN
TB2IN 37
+5V
+5V
18 TA3OUT
TB3OUT 22
400k
4 TA3IN
TB3IN 36
+5V
+5V
19 TA4OUT
TB4OUT 21
400k
5 TA4IN
TB4IN 35
1 ENA
ENB 39
11 RA1IN
RB1IN 29
5k
5k
RB1OUT 30
10 RA1OUT
RB2IN 28
12 RA2IN
5k
5k
9 RA2OUT
RB2OUT 31
13 RA3IN
MAX246 FUNCTIONAL DESCRIPTION
10 RECEIVERS
5 A-SIDE RECEIVERS (RA5 ALWAYS ACTIVE)
5 B-SIDE RECEIVERS (RB5 ALWAYS ACTIVE)
8 TRANSMITTERS
4 A-SIDE TRANSMITTERS
4 B-SIDE TRANSMITTERS
2 CONTROL PINS
ENABLE A-SIDE (ENA)
ENABLE B-SIDE (ENB)
RB3IN 27
5k
5k
8 RA3OUT
RB3OUT 32
14 RA4IN
RB4IN 26
5k
5k
7 RA4OUT
RB4OUT 33
RB5IN 25
15 RA5IN
5k
5k
6 RA5OUT
RB5OUT 34
GND
20
Figure 22. MAX246 Pin Configuration and Typical Operating Circuit
______________________________________________________________________________________
31
MAX220–MAX249
+5V-Powered, Multichannel RS-232
Drivers/Receivers
+5V
TOP VIEW
1µF
40
VCC
+5V
+5V
1 ENTA
ENTA
1
40
VCC
TA1IN
2
39
ENTB
TA2IN
3
38
TB1IN
TA3IN
4
37
TB2IN
TA4IN
5
36
TB3IN
RB5OUT
6
35
TB4IN
RA4OUT
7
34
RB4OUT
RA3OUT
8
33
RB3OUT
MAX247
RA2OUT
9
32
RB2OUT
RA1OUT
10
31
RB1OUT
ENRA
11
30
ENRB
RA1IN
12
29
RB1IN
RA2IN
13
28
RB2IN
RA3IN
14
27
RB3IN
RA4IN
15
26
RB4IN
TA1OUT
16
25
RB5IN
TA2OUT
17
24
TB1OUT
TA3OUT
18
23
TB2OUT
TA4OUT
19
22
TB3OUT
GND
20
21
TB4OUT
16 TA1OUT
ENTB 39
TB1OUT 24
400k
2 TA1IN
TB1IN 38
+5V
+5V
17 TA2OUT
TB2OUT 23
400k
3 TA2IN
TB2IN 37
+5V
+5V
18 TA3OUT
TB3OUT 22
400k
4 TA3IN
TB3IN 36
+5V
+5V
19 TA4OUT
TB4OUT 21
400k
5 TA4IN
TB4IN 35
6 RB5OUT
RB5IN 25
5k
12 RA1IN
RB1IN 29
5k
5k
10 RA1OUT
RB1OUT 31
13 RA2IN
RB2IN 28
DIP
5k
5k
MAX247 FUNCTIONAL DESCRIPTION
9 RECEIVERS
4 A-SIDE RECEIVERS
5 B-SIDE RECEIVERS (RB5 ALWAYS ACTIVE)
8 TRANSMITTERS
4 A-SIDE TRANSMITTERS
4 B-SIDE TRANSMITTERS
4 CONTROL PINS
ENABLE RECEIVER A-SIDE (ENRA)
ENABLE RECEIVER B-SIDE (ENRB)
ENABLE RECEIVER A-SIDE (ENTA)
ENABLE RECEIVERr B-SIDE (ENTB)
9 RA2OUT
RB2OUT 32
14 RA3IN
RB3IN 27
5k
5k
8 RA3OUT
RB3OUT 33
15 RA4IN
RB4IN 26
5k
5k
7 RA4OUT
RB4OUT 34
11 ENRA
ENRB 30
GND
20
Figure 23. MAX247 Pin Configuration and Typical Operating Circuit
32
______________________________________________________________________________________
+5V-Powered, Multichannel RS-232
Drivers/Receivers
MAX220–MAX249
TOP VIEW
+5V
1µF
1µF
20
5
3
2
1
1µF
RB4IN
TA4OUT
TB3OUT
TB2OUT
TB1OUT
TA1OUT
TA2OUT
TA4OUT
4
TA3OUT
RA3IN
6
RA4IN
21
1µF
44 43 42 41 40
C1+
23 C124
C2+
25 C2-
VCC
+5V TO +10V VOLTAGE DOUBLER
V+
V-
+5V
1 TA1OUT
39 RB3IN
RA1IN
8
38 RB2IN
ENRA
9
37 RB1IN
RA1OUT
10
36 ENRB
RA2OUT
11
35 RB1OUT
RA3OUT
12
RA4OUT
13
33 RB3OUT
TA1IN
14
32 RB4OUT
MAX248
34 RB2OUT
TA2IN
15
31 TB1IN
TA3IN
16
30 TB2IN
29 TB3IN
TB4IN
ENTB
V-
C2-
C2+
V+
C1-
VCC
19 20 21 22 23 24 25 26 27 28
C1+
18
GND
17
ENTA
TA4IN
PLCC
TB1OUT 44
400k
14 TA1IN
TB1IN 31
+5V
+5V
2 TA2OUT
TB2OUT 43
400k
15 TA2IN
TB2IN 30
+5V
+5V
3 TA3OUT
TB3OUT 42
400k
16 TA3IN
TB3IN 29
+5V
+5V
4 TA4OUT
TB4OUT 41
400k
17 TA4IN
TB4IN 28
8 RA1IN
RB1IN 37
5k
5k
MAX248 FUNCTIONAL DESCRIPTION
8 RECEIVERS
4 A-SIDE RECEIVERS
4 B-SIDE RECEIVERS
8 TRANSMITTERS
4 A-SIDE TRANSMITTERS
4 B-SIDE TRANSMITTERS
4 CONTROL PINS
ENABLE RECEIVER A-SIDE (ENRA)
ENABLE RECEIVER B-SIDE (ENRB)
ENABLE RECEIVER A-SIDE (ENTA)
ENABLE RECEIVER B-SIDE (ENTB)
1µF
ENTB 27
+5V
7
26
+10V TO -10V VOLTAGE INVERTER
18 ENTA
RA2IN
22
10 RA1OUT
RB1OUT 35
7 RA2IN
RB2IN 38
5k
5k
11 RA2OUT
RB2OUT 34
6 RA3IN
RB3IN 39
5k
5k
12 RA3OUT
RB3OUT 33
5 RA4IN
RB4IN 40
5k
5k
13 RA4OUT
9 ENRA
RB4OUT 32
ENRB 36
GND
19
Figure 24. MAX248 Pin Configuration and Typical Operating Circuit
______________________________________________________________________________________
33
MAX220–MAX249
+5V-Powered, Multichannel RS-232
Drivers/Receivers
+5V
TOP VIEW
1µF
1µF
20
2
1
44 43 42 41 40
1µF
RB4IN
TB3OUT
3
RB5IN
TB2OUT
TB1OUT
4
TA1OUT
5
TA3OUT
RA5IN
6
TA2OUT
RA3IN
RA4IN
21
1µF
VCC
+5V TO +10V VOLTAGE DOUBLER
C1+
23 C124
C2+
25 C2-
V+
V-
7
39 RB3IN
8
38 RB2IN
ENRA
9
37 RB1IN
RA1OUT
10
36 ENRB
RA2OUT
11
35 RB1OUT
RA3OUT
12
MAX249
34 RB2OUT
RA4OUT
13
33 RB3OUT
RA5OUT
14
32 RB4OUT
TA1IN
15
31 RB5OUT
TA2IN
16
30 TB1IN
29 TB2IN
TB3IN
ENTB
V-
C2-
C1-
C2+
V+
VCC
19 20 21 22 23 24 25 26 27 28
C1+
18
GND
17
ENTA
TA3IN
PLCC
+5V
TB1OUT 44
400k
15 TA1IN
TB1IN 30
+5V
+5V
TB2OUT 43
2 TA2OUT
400k
16 TA2IN
TB2IN 29
+5V
+5V
3 TA3OUT
TB3OUT 42
400k
17 TA3IN
TB3IN 28
8 RA1IN
RB1IN 37
5k
5k
10 RA1OUT
RB1OUT 35
7 RA2IN
RB2IN 38
5k
5k
MAX249 FUNCTIONAL DESCRIPTION
10 RECEIVERS
5 A-SIDE RECEIVERS
5 B-SIDE RECEIVERS
6 TRANSMITTERS
3 A-SIDE TRANSMITTERS
3 B-SIDE TRANSMITTERS
4 CONTROL PINS
ENABLE RECEIVER A-SIDE (ENRA)
ENABLE RECEIVER B-SIDE (ENRB)
ENABLE RECEIVER A-SIDE (ENTA)
ENABLE RECEIVER B-SIDE (ENTB)
11 RA2OUT
RB2OUT 34
6 RA3IN
RB3IN 39
5k
5k
12 RA3OUT
RB3OUT 33
5 RA4IN
RB4IN 40
5k
5k
13 RA4OUT
RB4OUT 32
4 RA5IN
RB5IN 41
5k
5k
14 RA5OUT
RB5OUT 31
9 ENRA
ENRB 36
GND
19
Figure 25. MAX249 Pin Configuration and Typical Operating Circuit
34
1µF
ENTB 27
+5V
1 TA1OUT
RA2IN
26
+10V TO -10V VOLTAGE INVERTER
18 ENTA
RA1IN
22
______________________________________________________________________________________
+5V-Powered, Multichannel RS-232
Drivers/Receivers
PIN-PACKAGE
MAX232AC/D
0°C to +70°C
MAX222CPN
PART
TEMP. RANGE
0°C to +70°C
18 Plastic DIP
MAX232AEPE
-40°C to +85°C
16 Plastic DIP
MAX222CWN
0°C to +70°C
18 Wide SO
MAX232AESE
-40°C to +85°C
16 Narrow SO
MAX222C/D
0°C to +70°C
Dice*
MAX232AEWE
-40°C to +85°C
16 Wide SO
MAX222EPN
-40°C to +85°C
18 Plastic DIP
MAX232AEJE
-40°C to +85°C
16 CERDIP
MAX222EWN
-40°C to +85°C
18 Wide SO
MAX232AMJE
-55°C to +125°C
16 CERDIP
MAX222EJN
-40°C to +85°C
18 CERDIP
MAX232AMLP
-55°C to +125°C
20 LCC
MAX222MJN
-55°C to +125°C
18 CERDIP
MAX233CPP
0°C to +70°C
20 Plastic DIP
MAX223CAI
0°C to +70°C
28 SSOP
MAX233EPP
-40°C to +85°C
20 Plastic DIP
MAX223CWI
0°C to +70°C
28 Wide SO
MAX233ACPP
0°C to +70°C
20 Plastic DIP
MAX223C/D
0°C to +70°C
Dice*
MAX233ACWP
0°C to +70°C
20 Wide SO
MAX223EAI
-40°C to +85°C
28 SSOP
MAX233AEPP
-40°C to +85°C
20 Plastic DIP
MAX223EWI
-40°C to +85°C
28 Wide SO
MAX233AEWP
-40°C to +85°C
20 Wide SO
MAX225CWI
0°C to +70°C
28 Wide SO
MAX234CPE
0°C to +70°C
16 Plastic DIP
MAX225EWI
-40°C to +85°C
28 Wide SO
MAX234CWE
0°C to +70°C
16 Wide SO
MAX230CPP
0°C to +70°C
20 Plastic DIP
MAX234C/D
0°C to +70°C
Dice*
MAX230CWP
0°C to +70°C
20 Wide SO
MAX234EPE
-40°C to +85°C
16 Plastic DIP
MAX230C/D
0°C to +70°C
Dice*
MAX234EWE
-40°C to +85°C
16 Wide SO
MAX230EPP
-40°C to +85°C
20 Plastic DIP
MAX234EJE
-40°C to +85°C
16 CERDIP
MAX230EWP
-40°C to +85°C
20 Wide SO
MAX234MJE
-55°C to +125°C
16 CERDIP
MAX230EJP
-40°C to +85°C
20 CERDIP
MAX235CPG
0°C to +70°C
24 Wide Plastic DIP
MAX230MJP
-55°C to +125°C
20 CERDIP
MAX235EPG
-40°C to +85°C
24 Wide Plastic DIP
MAX231CPD
0°C to +70°C
14 Plastic DIP
MAX235EDG
-40°C to +85°C
24 Ceramic SB
MAX231CWE
0°C to +70°C
16 Wide SO
MAX235MDG
-55°C to +125°C
24 Ceramic SB
MAX231CJD
0°C to +70°C
14 CERDIP
MAX236CNG
0°C to +70°C
24 Narrow Plastic DIP
MAX231C/D
0°C to +70°C
Dice*
MAX236CWG
0°C to +70°C
24 Wide SO
MAX231EPD
-40°C to +85°C
14 Plastic DIP
MAX236C/D
0°C to +70°C
Dice*
MAX231EWE
-40°C to +85°C
16 Wide SO
MAX236ENG
-40°C to +85°C
24 Narrow Plastic DIP
MAX231EJD
-40°C to +85°C
14 CERDIP
MAX236EWG
-40°C to +85°C
24 Wide SO
MAX231MJD
-55°C to +125°C
14 CERDIP
MAX236ERG
-40°C to +85°C
24 Narrow CERDIP
MAX232CPE
0°C to +70°C
16 Plastic DIP
MAX236MRG
-55°C to +125°C
24 Narrow CERDIP
MAX232CSE
0°C to +70°C
16 Narrow SO
MAX237CNG
0°C to +70°C
24 Narrow Plastic DIP
MAX232CWE
0°C to +70°C
16 Wide SO
MAX237CWG
0°C to +70°C
24 Wide SO
MAX232C/D
0°C to +70°C
Dice*
MAX237C/D
0°C to +70°C
Dice*
MAX232EPE
-40°C to +85°C
16 Plastic DIP
MAX237ENG
-40°C to +85°C
24 Narrow Plastic DIP
MAX232ESE
-40°C to +85°C
16 Narrow SO
MAX237EWG
-40°C to +85°C
24 Wide SO
MAX232EWE
-40°C to +85°C
16 Wide SO
MAX237ERG
-40°C to +85°C
24 Narrow CERDIP
MAX232EJE
-40°C to +85°C
16 CERDIP
MAX237MRG
-55°C to +125°C
24 Narrow CERDIP
MAX232MJE
-55°C to +125°C
16 CERDIP
MAX238CNG
0°C to +70°C
24 Narrow Plastic DIP
MAX232MLP
-55°C to +125°C
20 LCC
MAX238CWG
0°C to +70°C
24 Wide SO
0°C to +70°C
Dice*
MAX232ACPE
0°C to +70°C
16 Plastic DIP
MAX238C/D
MAX232ACSE
0°C to +70°C
16 Narrow SO
MAX238ENG
MAX232ACWE
0°C to +70°C
16 Wide SO
-40°C to +85°C
Dice*
24 Narrow Plastic DIP
* Contact factory for dice specifications.
______________________________________________________________________________________
35
MAX220–MAX249
___________________________________________Ordering Information (continued)
MAX220–MAX249
+5V-Powered, Multichannel RS-232
Drivers/Receivers
___________________________________________Ordering Information (continued)
PIN-PACKAGE
MAX243CPE
0°C to +70°C
16 Plastic DIP
MAX238EWG
PART
-40°C to +85°C
TEMP. RANGE
24 Wide SO
MAX243CSE
0°C to +70°C
16 Narrow SO
MAX238ERG
-40°C to +85°C
24 Narrow CERDIP
MAX243CWE
0°C to +70°C
16 Wide SO
MAX238MRG
-55°C to +125°C
24 Narrow CERDIP
MAX243C/D
0°C to +70°C
Dice*
MAX239CNG
0°C to +70°C
24 Narrow Plastic DIP
MAX243EPE
-40°C to +85°C
16 Plastic DIP
MAX239CWG
0°C to +70°C
24 Wide SO
MAX243ESE
-40°C to +85°C
16 Narrow SO
MAX239C/D
0°C to +70°C
Dice*
MAX243EWE
-40°C to +85°C
16 Wide SO
MAX239ENG
-40°C to +85°C
24 Narrow Plastic DIP
MAX243EJE
-40°C to +85°C
16 CERDIP
MAX239EWG
-40°C to +85°C
24 Wide SO
MAX243MJE
-55°C to +125°C
16 CERDIP
MAX239ERG
-40°C to +85°C
24 Narrow CERDIP
MAX244CQH
0°C to +70°C
44 PLCC
MAX239MRG
-55°C to +125°C
24 Narrow CERDIP
MAX244C/D
0°C to +70°C
Dice*
MAX240CMH
0°C to +70°C
44 Plastic FP
MAX244EQH
-40°C to +85°C
MAX240C/D
0°C to +70°C
Dice*
MAX245CPL
0°C to +70°C
40 Plastic DIP
MAX241CAI
0°C to +70°C
28 SSOP
MAX245C/D
0°C to +70°C
Dice*
MAX241CWI
0°C to +70°C
28 Wide SO
MAX245EPL
-40°C to +85°C
40 Plastic DIP
MAX241C/D
0°C to +70°C
Dice*
MAX246CPL
0°C to +70°C
40 Plastic DIP
MAX241EAI
-40°C to +85°C
28 SSOP
MAX246C/D
0°C to +70°C
Dice*
MAX241EWI
-40°C to +85°C
28 Wide SO
MAX246EPL
-40°C to +85°C
40 Plastic DIP
0°C to +70°C
40 Plastic DIP
Dice*
44 PLCC
MAX242CAP
0°C to +70°C
20 SSOP
MAX247CPL
MAX242CPN
0°C to +70°C
18 Plastic DIP
MAX247C/D
0°C to +70°C
MAX242CWN
0°C to +70°C
18 Wide SO
MAX247EPL
-40°C to +85°C
MAX242C/D
0°C to +70°C
Dice*
MAX248CQH
0°C to +70°C
44 PLCC
MAX242EPN
-40°C to +85°C
18 Plastic DIP
MAX248C/D
0°C to +70°C
Dice*
MAX242EWN
-40°C to +85°C
18 Wide SO
MAX248EQH
MAX242EJN
-40°C to +85°C
18 CERDIP
MAX242MJN
-55°C to +125°C
18 CERDIP
40 Plastic DIP
-40°C to +85°C
44 PLCC
MAX249CQH
0°C to +70°C
44 PLCC
MAX249EQH
-40°C to +85°C
44 PLCC
* Contact factory for dice specifications.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
36 __________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600
© 2001 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
ANEXOS 3 - Fichas Técnicas do Hardware desenvolvido
HEF4047
clxxiv
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
• The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4047B
MSI
Monostable/astable multivibrator
Product specification
File under Integrated Circuits, IC04
January 1995
Philips Semiconductors
Product specification
HEF4047B
MSI
Monostable/astable multivibrator
DESCRIPTION
The HEF4047B consists of a gatable astable multivibrator
with logic techniques incorporated to permit positive or
negative edge-triggered monostable multivibrator action
with retriggering and external counting options.
Inputs include + TRIGGER, − TRIGGER, ASTABLE,
ASTABLE, RETRIGGER and MR (Master Reset).
Buffered outputs are O, O and OSCILLATOR OUTPUT. In
all modes of operation an external capacitor (Ct) must be
connected between CTC and RCTC, and an external
resistor (Rt) must be connected between RTC and
RCTC (continued on next page).
Fig.1 Functional diagram.
FAMILY DATA, IDD LIMITS category MSI
See Family Specifications
January 1995
2
Philips Semiconductors
Product specification
HEF4047B
MSI
Monostable/astable multivibrator
An external count down option can be implemented by
coupling O to an external ‘N’ counter and resetting the
counter with the trigger pulse. The counter output pulse is
fed back to the ASTABLE input and has a duration equal
to N times the period of the multivibrator. A HIGH level on
the MR input assures no output pulse during an ON-power
condition. This input can also be activated to terminate the
output pulse at any time. In the monostable mode, a HIGH
level or power-ON reset pulse must be applied to MR,
whenever VDD is applied.
Astable operation is enabled by a HIGH level on the
ASTABLE input. The period of the square wave at O and
O outputs is a function of the external components
employed. ‘True’ input pulses on the ASTABLE or
‘complement’ pulses on the ASTABLE input, allow the
circuit to be used as a gatable multivibrator. The
OSCILLATOR OUTPUT period will be half of the O output
in the astable mode. However, a 50% duty factor is not
guaranteed at this output.
In the monostable mode, positive edge-triggering is
accomplished by applying a leading-edge pulse to the
+ TRIGGER input and a LOW level to the − TRIGGER
input. For negative edge-triggering, a trailing-edge pulse is
applied to the − TRIGGER and a HIGH level to the
+ TRIGGER. Input pulses may be of any duration relative
to the output pulse. The multivibrator can be retriggered
(on the leading-edge only) by applying a common pulse to
both the RETRIGGER and + TRIGGER inputs. In this
mode the output pulse remains HIGH as long as the input
pulse period is shorter than the period determined by the
RC components.
HEF4047BP(N):
14-lead DIL; plastic
(SOT27-1)
HEF4047BD(F):
14-lead DIL; ceramic (cerdip)
HEF4047BT(D):
14-lead SO; plastic
(SOT73)
(SOT108-1)
( ): Package Designator North America
Fig.2 Pinning diagram.
January 1995
3
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Philips Semiconductors
Monostable/astable multivibrator
January 1995
4
Product specification
Fig.3 Logic diagram.
HEF4047B
MSI
(1) Special input protection that allows operating input voltages
outside the supply voltage lines. Compared to the standard input
protection pin 3 is more sensitive to static discharge; extra
handling precautions are recommended.
Philips Semiconductors
Product specification
HEF4047B
MSI
Monostable/astable multivibrator
FUNCTIONAL CONNECTIONS
PINS CONNECTED TO
FUNCTION
VDD
VSS
OUTPUT
PULSE
INPUT
FROM
PULSE
PINS
OUTPUT
PERIOD
OR
PULSE WIDTH
astable multivibrator
free running
4, 5, 6, 14
7, 8, 9, 12
−
10, 11, 13
at pins 10, 11:
true gating
4, 6, 14
7, 8, 9, 12
5
10, 11, 13
complement gating
6, 14
5, 7, 8, 9, 12
4
10, 11, 13
tA = 4,40 RtCt
at pin 13:
tA = 2,20 RtCt
pos. edge-triggering
4, 14
5, 6, 7, 9, 12
8
10, 11
neg. edge-triggering
4, 8, 14
5, 7, 9, 12
6
10, 11
at pins 10, 11:
retriggerable
4, 14
5, 6, 7, 9
8, 12
10, 11
tM = 2,48 RtCt
14
5, 6, 7, 8, 9, 12
−
10, 11
monostable multivibrator
external count
down(1)
Notes
1. Input pulse to RESET of external counting chip; external counting chip output to pin 4.
2. In all cases, external resistor between pins 2 and 3, external capacitor between pins 1 and 3.
DC CHARACTERISTICS
VSS = 0 V; inputs at VSS or VDD
Tamb (°C)
VDD
V
SYMBOL
−40
+ 25
+ 85
MAX.
MIN.
MAX.
MAX.
0,3
−
0,3
1
Leakage current
pin 3; output
15
I3
transistor OFF
January 1995
5
µA
pin 3 at
VDD or VSS
Philips Semiconductors
Product specification
HEF4047B
MSI
Monostable/astable multivibrator
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
SYMBOL MIN. TYP. MAX.
TYPICAL EXTRAPOLATION
FORMULA
Propagation delays
ASTABLE, ASTABLE → OSC. OUTPUT
HIGH to LOW
95
190
68 ns + (0,55 ns/pF) CL
45
90
43 ns + (0,23 ns/pF) CL
30
60
22 ns + (0,16 ns/pF) CL
85
170
58 ns + (0,55 ns/pF) CL
40
80
29 ns + (0,23 ns/pF) CL
30
60
22 ns + (0,16 ns/pF) CL
150
300
123 ns + (0,55 ns/pF) CL
65
130
54 ns + (0,23 ns/pF) CL
50
100
42 ns + (0,16 ns/pF) CL
130
260
103 ns + (0,55 ns/pF) CL
60
120
49 ns + (0,23 ns/pF) CL
45
90
37 ns + (0,16 ns/pF) CL
160
320
133 ns + (0,55 ns/pF) CL
65
130
54 ns + (0,23 ns/pF) CL
15
50
100
42 ns + (0,16 ns/pF) CL
5
155
310
128 ns + (0,55 ns/pF) CL
5
10
tPHL
15
5
LOW to HIGH
10
tPLH
15
ASTABLE, ASTABLE → O, O
HIGH to LOW
5
10
tPHL
15
5
LOW to HIGH
10
tPLH
15
+/− TRIGGER → O, O
HIGH to LOW
LOW to HIGH
+ TRIGGER, RETRIGGER → O
HIGH to LOW
+ TRIGGER, RETRIGGER → O
LOW to HIGH
MR → O
HIGH to LOW
MR → O
LOW to HIGH
Output transition times
HIGH to LOW
LOW to HIGH
5
10
tPHL
65
130
54 ns + (0,23 ns/pF) CL
15
50
100
42 ns + (0,16 ns/pF) CL
5
65
130
38 ns + (0,55 ns/pF) CL
10
tPLH
30
60
19 ns + (0,23 ns/pF) CL
15
25
50
17 ns + (0,16 ns/pF) CL
5
95
190
68 ns + (0,55 ns/pF) CL
10
tPHL
40
80
29 ns + (0,23 ns/pF) CL
15
30
60
22 ns + (0,16 ns/pF) CL
5
100
200
83 ns + (0,55 ns/pF) CL
10
tPLH
45
90
34 ns + (0,23 ns/pF) CL
15
35
70
27 ns + (0,16 ns/pF) CL
5
100
200
83 ns + (0,55 ns/pF) CL
10
tPHL
45
90
34 ns + (0,23 ns/pF) CL
15
35
70
27 ns + (0,16 ns/pF) CL
5
60
120
10 ns + (1,0 ns/pF) CL
30
60
10
10
tPLH
tTHL
6 ns + (0,28 ns/pF) CL
15
20
40
5
60
120
30
60
9 ns + (0,42 ns/pF) CL
20
40
6 ns + (0,28 ns/pF) CL
10
tTLH
15
January 1995
9 ns + (0,42 ns/pF) CL
6
10 ns + (1,0 ns/pF) CL
Philips Semiconductors
Product specification
HEF4047B
MSI
Monostable/astable multivibrator
VDD
V
Minimum MR pulse
5
width; HIGH
10
SYMBOL MIN. TYP. MAX.
tWMRH
15
60
30
30
15
20
10
Minimum input
pulse width; any
5
input exept MR
10
tW
15
APPLICATION INFORMATION
General features:
• Monostable (one-shot) or astable (free-running)
operation
• True and complemented buffered outputs
• Only one external R and C required
Monostable multivibrator features:
• Positive- or negative-edge triggering
• Output pulse width independent of trigger pulse duration
• Retriggerable option for pulse-width expansion
• Long pulse width possible using small RC components
by means of external counter provision
• Fast recovery time essentially independent of pulse
width
• Pulse-width accuracy maintained at duty cycles
approaching 100%
Astable multivibrator features:
• Free-running or gatable operating modes
• 50% duty cycle
• Oscillator output available
January 1995
7
220
110
100
50
70
35
TYPICAL EXTRAPOLATION
FORMULA
Philips Semiconductors
Product specification
HEF4047B
MSI
Monostable/astable multivibrator
1. Astable mode design information
a. Unit-to-unit transfer-voltage variations
The following analysis presents worst-case variations from unit-to-unit as a function of transfer-voltage (VTR) shift for free
running (astable) operation.
Fig.4 Astable mode waveforms.
V TR
t 1 = – R t C t In ---------------------------V DD + V TR
V DD – V TR
t 2 = – R t C t In ------------------------------2V DD – V TR
( V TR ) ( V DD – V TR )
t A = 2 ( t 1 + t 2 ) = – 2R t C t In ------------------------------------------------------------------------- , where t A = Astable mode pulse width.
( V DD + V TR ) ( 2V DD – V TR )
Values for tA are:
VDD = 5 or 10 V
VDD = 15 V
typ. : VTR = 0,5 VDD;
tA = 4,40 RtCt
min. : VTR = 0,3 VDD;
tA = 4,71 RtCt
max.: VTR = 0,7 VDD;
tA = 4,71 RtCt
min. : VTR = 4 V;
tA = 4,84 RtCt
max.: VTR = 11 V;
tA = 4,84 RtCt
thus if tA = 4,40 RtCt is used, the maximum variation will be (+ 7,0%; −0,0%) at 10 V.
January 1995
8
Philips Semiconductors
Product specification
HEF4047B
MSI
Monostable/astable multivibrator
b. Variations due to changes in VDD
In addition to variations from unit-to-unit, the astable period may vary as a function of frequency with respect to VDD.
Typical variations are presented graphically in Figs 5 and 6 with 10 V as a reference.
Fig.5 Typical O and O period accuracy as a function of supply voltage; astable mode; Tamb = 25 °C.
CURVE
A
fO
kHz
10
Ct
pF
Rt
kΩ
100
220
B
5
100
470
C
1
1000
220
January 1995
9
Philips Semiconductors
Product specification
HEF4047B
MSI
Monostable/astable multivibrator
Fig.6 Typical O and O period accuracy as a function of supply voltage; astable mode; Tamb = 25 °C.
CURVE
fO
kHz
Ct
pF
Rt
kΩ
A
500
10
47
B
225
100
10
C
100
100
22
D
50
100
47
January 1995
10
Philips Semiconductors
Product specification
HEF4047B
MSI
Monostable/astable multivibrator
2. Monostable mode design information
The following analysis presents worst case variations from unit-to-unit as a function of transfer-voltage (VTR) shift for
one-shot (monostalbe) operation.
Fig.7 Monostable waveforms.
V TR
t 1 ‘ = – R t C t In -------------2V DD
t M = ( t 1' + t 2 )
( V TR ) ( V DD – V TR )
t M = – R t C t In ------------------------------------------------------------ , where t M = Monostable mode pulse width.
( 2V DD – V TR ) ( 2V DD )
Values for tM are:
typ. : VTR = 0,5 VDD; tM = 2,48 RtCt
VDD = 5 to10 V
VDD = 15 V
min. : VTR = 0,3 VDD; tM = 2,78 RtCt
max.: VTR = 0,7 VDD; tM = 2,52 RtCt
min. : VTR = 4 V;
tM = 2,88 RtCt
max.: VTR = 11 V;
tM = 2,56 RtCt
Note
1. In the astable mode, the first positive half cycle has a duration of tM; succeeding durations are 1⁄2 tA.
thus if tM = 2,48 RtCt is used, the maximum variation will be (+ 12%; −0,0%) at 10 V.
January 1995
11
Philips Semiconductors
Product specification
HEF4047B
MSI
Monostable/astable multivibrator
3. Retrigger mode operation
The HEF4047B can be used in the retrigger mode to extend the output pulse duration, or to compare the frequency of
an input signal with that of the internal oscillator. In the retrigger mode the input pulse is applied to pins 8 and 12, and
the output is taken from pin 10 or 11. Normal monostable action is obtained when one retrigger pulse is applied (Fig.8).
Extended pulse duration is obtained when more than one pulse is applied. For two input pulses, tRE = t1’ + t1 + 2t2.
For more than two pulses, tRE (output O), terminates at some variable time, tD, after the termination of the last retrigger
pulse; tD is variable because tRE (output O) terminates after the second positive edge of the oscillator output appears at
flip-flop 4.
Fig.8 Retrigger mode waveforms.
4. External counter option
Time tM can be extended by any amount with the use of external counting circuitry. Advantages include digitally
controlled pulse duration, small timing capacitors for long time periods, and extremely fast recovery time. A typical
implementation is shown in Fig.9.
The pulse duration at the output is: t ext = ( N – 1 ) ( t A ) + ( t M + 1 ⁄ 2 t A )
Where text = pulse duration of the circuitry, and N is the number of counts used.
Fig.9 Implementation of external counter option.
January 1995
12
Philips Semiconductors
Product specification
HEF4047B
MSI
Monostable/astable multivibrator
5. Timing component limitations
The capacitor used in the circuit should be non-polarized and have low leakage (i.e. the parallel resistance of the
capacitor should be an order of magnitude greater than the external resistor used).
There is no upper or lower limit for either Rt or Ct value to maintain oscillation.
However, in consideration of accuracy, Ct must be much larger than the inherent stray capacitance in the system (unless
this capacitance can be measured and taken into account).
Rt must be much larger than the LOCMOS ‘ON’ resistance in series with it, which typically is hundreds of ohms.
The recommended values for Rt and Ct to maintain agreement with previously calculated formulae without trimming
should be:
Ct ≥ 100 pF, up to any practical value,
10 kΩ ≤ Rt ≤ 1 MΩ.
6. Power consumption
In the standby mode (monostable or astable), power dissipation will be a function of leakage current in the circuit.
For dynamic operation, the power needed to charge the external timing capacitor Ct is given by the following formulae:
Astable mode:
P = 2 Ct V2 f (f at output pin 13)
P = 4 Ct V2 f (f at output pins 10 and 11)
Monostable mode:
2

 2, 9 C t V  ( duty cycle )
P = --------------------------------------------------------------------- ( f at output pins 10 and 11 )
T
Because the power dissipation does not depend on Rt, a design for minimum power dissipation would be a small value
of Ct. The value of R would depend on the desired period (within the limitations discussed previously).
Typical power consumption in astable mode is shown in Figs 10, 11 and 12.
January 1995
13
Philips Semiconductors
Product specification
HEF4047B
MSI
Monostable/astable multivibrator
Fig.10 Power consumption as a function of the output frequency at O or O; VDD = 5 V; astable mode.
Fig.11 Power consumption as a function of the output frequency at O or O; VDD = 10 V; astable mode.
January 1995
14
Philips Semiconductors
Product specification
HEF4047B
MSI
Monostable/astable multivibrator
Fig.12 Power consumption as a function of the output frequency at O or O; VDD = 15 V; astable mode.
January 1995
15
ANEXOS 3 - Fichas Técnicas do Hardware desenvolvido
AT89C51
cxc
Features
• Compatible with MCS-51™ Products
• 4K Bytes of In-System Reprogrammable Flash Memory
•
•
•
•
•
•
•
•
– Endurance: 1,000 Write/Erase Cycles
Fully Static Operation: 0 Hz to 24 MHz
Three-level Program Memory Lock
128 x 8-bit Internal RAM
32 Programmable I/O Lines
Two 16-bit Timer/Counters
Six Interrupt Sources
Programmable Serial Channel
Low-power Idle and Power-down Modes
Description
The AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4K
bytes of Flash programmable and erasable read only memory (PEROM). The device
is manufactured using Atmel’s high-density nonvolatile memory technology and is
compatible with the industry-standard MCS-51 instruction set and pinout. The on-chip
Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash
on a monolithic chip, the Atmel AT89C51 is a powerful microcomputer which provides
a highly-flexible and cost-effective solution to many embedded control applications.
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
(RXD) P3.0
(TXD) P3.1
(INT0) P3.2
(INT1) P3.3
(T0) P3.4
(T1) P3.5
(WR) P3.6
(RD) P3.7
XTAL2
XTAL1
GND
44
43
42
41
40
39
38
37
36
35
34
P1.4
P1.3
P1.2
P1.1 (T2 EX)
P1.0 (T2)
NC
VCC
P0.0 (AD0)
P0.1 (AD1)
P0.2 (AD2)
P0.3 (AD3)
PQFP/TQFP
VCC
P0.0 (AD0)
P0.1 (AD1)
P0.2 (AD2)
P0.3 (AD3)
P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
EA/VPP
ALE/PROG
PSEN
P2.7 (A15)
P2.6 (A14)
P2.5 (A13)
P2.4 (A12)
P2.3 (A11)
P2.2 (A10)
P2.1 (A9)
P2.0 (A8)
P1.5
P1.6
P1.7
RST
(RXD) P3.0
NC
(TXD) P3.1
(INT0) P3.2
(INT1) P3.3
(T0) P3.4
(T1) P3.5
6
5
4
3
2
1
44
43
42
41
40
P1.4
P1.3
P1.2
P1.1
P1.0
NC
VCC
P0.0 (AD0)
P0.1 (AD1)
P0.2 (AD2)
P0.3 (AD3)
PLCC
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
18
19
20
21
22
23
24
25
26
27
28
12
13
14
15
16
17
18
19
20
21
22
PO.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
EA/VPP
NC
ALE/PROG
PSEN
P2.7 (A15)
P2.6 (A14)
P2.5 (A13)
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
(WR)P3.6
(RD) P3.7
XTAL2
XTAL1
GND
NC
(A8) P2.0
(A9) P2.1
(A10) P2.2
(A11) P2.3
(A12) P2.4
33
32
31
30
29
28
27
26
25
24
23
1
2
3
4
5
6
7
8
9
10
11
(WR)P3.6
(RD) P3.7
XTAL2
XTAL1
GND
GND
(A8) P2.0
(A9) P2.1
(A10) P2.2
(A11) P2.3
(A12) P2.4
P1.5
P1.6
P1.7
RST
(RXD) P3.0
NC
(TXD) P3.1
(INT0) P3.2
(INT1) P3.3
(T0) P3.4
(T1) P3.5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
AT89C51
Not Recommended
for New Designs.
Use AT89S51.
PDIP
Pin Configurations
8-bit
Microcontroller
with 4K Bytes
Flash
PO.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
EA/VPP
NC
ALE/PROG
PSEN
P2.7 (A15)
P2.6 (A14)
P2.5 (A13)
Rev. 0265G–02/00
1
Block Diagram
P0.0 - P0.7
P2.0 - P2.7
PORT 0 DRIVERS
PORT 2 DRIVERS
VCC
GND
RAM ADDR.
REGISTER
B
REGISTER
PORT 0
LATCH
RAM
PORT 2
LATCH
FLASH
STACK
POINTER
ACC
BUFFER
TMP1
TMP2
PROGRAM
ADDRESS
REGISTER
PC
INCREMENTER
ALU
INTERRUPT, SERIAL PORT,
AND TIMER BLOCKS
PROGRAM
COUNTER
PSW
PSEN
ALE/PROG
EA / VPP
TIMING
AND
CONTROL
INSTRUCTION
REGISTER
DPTR
RST
PORT 1
LATCH
PORT 3
LATCH
PORT 1 DRIVERS
PORT 3 DRIVERS
OSC
P1.0 - P1.7
2
AT89C51
P3.0 - P3.7
AT89C51
The AT89C51 provides the following standard features: 4K
bytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bit
timer/counters, a five vector two-level interrupt architecture,
a full duplex serial port, on-chip oscillator and clock circuitry. In addition, the AT89C51 is designed with static logic
for operation down to zero frequency and supports two
software selectable power saving modes. The Idle Mode
stops the CPU while allowing the RAM, timer/counters,
serial port and interrupt system to continue functioning. The
Power-down Mode saves the RAM contents but freezes
the oscillator disabling all other chip functions until the next
hardware reset.
Port 2 pins that are externally being pulled low will source
current (IIL) because of the internal pullups.
Port 2 emits the high-order address byte during fetches
from external program memory and during accesses to
external data memory that use 16-bit addresses (MOVX @
DPTR). In this application, it uses strong internal pullups
when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the
contents of the P2 Special Function Register.
Port 2 also receives the high-order address bits and some
control signals during Flash programming and verification.
Port 3
Pin Description
VCC
Supply voltage.
GND
Ground.
Port 3 is an 8-bit bi-directional I/O port with internal pullups.
The Port 3 output buffers can sink/source four TTL inputs.
When 1s are written to Port 3 pins they are pulled high by
the internal pullups and can be used as inputs. As inputs,
Port 3 pins that are externally being pulled low will source
current (IIL) because of the pullups.
Port 3 also serves the functions of various special features
of the AT89C51 as listed below:
Port 0
Port 0 is an 8-bit open-drain bi-directional I/O port. As an
output port, each pin can sink eight TTL inputs. When 1s
are written to port 0 pins, the pins can be used as highimpedance inputs.
Port Pin
Alternate Functions
P3.0
RXD (serial input port)
P3.1
TXD (serial output port)
Port 0 may also be configured to be the multiplexed loworder address/data bus during accesses to external program and data memory. In this mode P0 has internal
pullups.
P3.2
INT0 (external interrupt 0)
P3.3
INT1 (external interrupt 1)
P3.4
T0 (timer 0 external input)
Port 0 also receives the code bytes during Flash programming, and outputs the code bytes during program
verification. External pullups are required during program
verification.
P3.5
T1 (timer 1 external input)
P3.6
WR (external data memory write strobe)
P3.7
RD (external data memory read strobe)
Port 1
Port 1 is an 8-bit bi-directional I/O port with internal pullups.
The Port 1 output buffers can sink/source four TTL inputs.
When 1s are written to Port 1 pins they are pulled high by
the internal pullups and can be used as inputs. As inputs,
Port 1 pins that are externally being pulled low will source
current (IIL) because of the internal pullups.
Port 1 also receives the low-order address bytes during
Flash programming and verification.
Port 2
Port 2 is an 8-bit bi-directional I/O port with internal pullups.
The Port 2 output buffers can sink/source four TTL inputs.
When 1s are written to Port 2 pins they are pulled high by
the internal pullups and can be used as inputs. As inputs,
Port 3 also receives some control signals for Flash programming and verification.
RST
Reset input. A high on this pin for two machine cycles while
the oscillator is running resets the device.
ALE/PROG
Address Latch Enable output pulse for latching the low byte
of the address during accesses to external memory. This
pin is also the program pulse input (PROG) during Flash
programming.
In normal operation ALE is emitted at a constant rate of 1/6
the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE
3
pulse is skipped during each access to external Data
Memory.
unconnected while XTAL1 is driven as shown in Figure 2.
There are no requirements on the duty cycle of the external
clock signal, since the input to the internal clocking circuitry
is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be
observed.
If desired, ALE operation can be disabled by setting bit 0 of
SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is
weakly pulled high. Setting the ALE-disable bit has no
effect if the microcontroller is in external execution mode.
Idle Mode
PSEN
In idle mode, the CPU puts itself to sleep while all the onchip peripherals remain active. The mode is invoked by
software. The content of the on-chip RAM and all the special functions registers remain unchanged during this
mode. The idle mode can be terminated by any enabled
interrupt or by a hardware reset.
Program Store Enable is the read strobe to external program memory.
When the AT89C51 is executing code from external program memory, PSEN is activated twice each machine
cycle, except that two PSEN activations are skipped during
each access to external data memory.
It should be noted that when idle is terminated by a hard
ware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before
the internal reset algorithm takes control. On-chip hardware
inhibits access to internal RAM in this event, but access to
the port pins is not inhibited. To eliminate the possibility of
an unexpected write to a port pin when Idle is terminated by
reset, the instruction following the one that invokes Idle
should not be one that writes to a port pin or to external
memory.
EA/VPP
External Access Enable. EA must be strapped to GND in
order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH.
Note, however, that if lock bit 1 is programmed, EA will be
internally latched on reset.
EA should be strapped to V C C for internal program
executions.
This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming, for parts that require
12-volt VPP.
Figure 1. Oscillator Connections
C2
XTAL2
XTAL1
Input to the inverting oscillator amplifier and input to the
internal clock operating circuit.
C1
XTAL1
XTAL2
Output from the inverting oscillator amplifier.
GND
Oscillator Characteristics
XTAL1 and XTAL2 are the input and output, respectively,
of an inverting amplifier which can be configured for use as
an on-chip oscillator, as shown in Figure 1. Either a quartz
crystal or ceramic resonator may be used. To drive the
device from an external clock source, XTAL2 should be left
Note:
C1, C2 = 30 pF ± 10 pF for Crystals
= 40 pF ± 10 pF for Ceramic Resonators
Status of External Pins During Idle and Power-down Modes
Mode
Program Memory
ALE
PSEN
PORT0
PORT1
PORT2
PORT3
Idle
Internal
1
1
Data
Data
Data
Data
Idle
External
1
1
Float
Data
Address
Data
Power-down
Internal
0
0
Data
Data
Data
Data
Power-down
External
0
0
Float
Data
Data
Data
4
AT89C51
AT89C51
Figure 2. External Clock Drive Configuration
ters retain their values until the power-down mode is
terminated. The only exit from power-down is a hardware
reset. Reset redefines the SFRs but does not change the
on-chip RAM. The reset should not be activated before VCC
is restored to its normal operating level and must be held
active long enough to allow the oscillator to restart and
stabilize.
Program Memory Lock Bits
On the chip are three lock bits which can be left unprogrammed (U) or can be programmed (P) to obtain the
additional features listed in the table below.
Power-down Mode
In the power-down mode, the oscillator is stopped, and the
instruction that invokes power-down is the last instruction
executed. The on-chip RAM and Special Function Regis-
When lock bit 1 is programmed, the logic level at the EA pin
is sampled and latched during reset. If the device is powered up without a reset, the latch initializes to a random
value, and holds that value until reset is activated. It is necessary that the latched value of EA be in agreement with
the current logic level at that pin in order for the device to
function properly.
Lock Bit Protection Modes
Program Lock Bits
LB1
LB2
LB3
Protection Type
1
U
U
U
No program lock features
2
P
U
U
MOVC instructions executed from external program memory are disabled from
fetching code bytes from internal memory, EA is sampled and latched on reset,
and further programming of the Flash is disabled
3
P
P
U
Same as mode 2, also verify is disabled
4
P
P
P
Same as mode 3, also external execution is disabled
5
Programming the Flash
The AT89C51 is normally shipped with the on-chip Flash
memory array in the erased state (that is, contents = FFH)
and ready to be programmed. The programming interface
accepts either a high-voltage (12-volt) or a low-voltage
(V CC ) program enable signal. The low-voltage programming mode provides a convenient way to program the
AT89C51 inside the user’s system, while the high-voltage
programming mode is compatible with conventional thirdparty Flash or EPROM programmers.
The AT89C51 is shipped with either the high-voltage or
low-voltage programming mode enabled. The respective
top-side marking and device signature codes are listed in
the following table.
VPP = 12V
VPP = 5V
Top-side Mark
AT89C51
xxxx
yyww
AT89C51
xxxx-5
yyww
Signature
(030H) = 1EH
(031H) = 51H
(032H) =F FH
(030H) = 1EH
(031H) = 51H
(032H) = 05H
The AT89C51 code memory array is programmed byte-bybyte in either programming mode. To program any nonblank byte in the on-chip Flash Memory, the entire memory
must be erased using the Chip Erase Mode.
Programming Algorithm: Before programming the
AT89C51, the address, data and control signals should be
set up according to the Flash programming mode table and
Figure 3 and Figure 4. To program the AT89C51, take the
following steps.
1. Input the desired memory location on the address
lines.
2. Input the appropriate data byte on the data lines.
3. Activate the correct combination of control signals.
4. Raise EA/VPP to 12V for the high-voltage programming mode.
5. Pulse ALE/PROG once to program a byte in the
Flash array or the lock bits. The byte-write cycle is
self-timed and typically takes no more than 1.5 ms.
Repeat steps 1 through 5, changing the address
6
AT89C51
and data for the entire array or until the end of the
object file is reached.
Data Polling: The AT89C51 features Data Polling to indicate the end of a write cycle. During a write cycle, an
attempted read of the last byte written will result in the complement of the written datum on PO.7. Once the write cycle
has been completed, true data are valid on all outputs, and
the next cycle may begin. Data Polling may begin any time
after a write cycle has been initiated.
Ready/Busy: The progress of byte programming can also
be monitored by the RDY/BSY output signal. P3.4 is pulled
low after ALE goes high during programming to indicate
BUSY. P3.4 is pulled high again when programming is
done to indicate READY.
Program Verify: If lock bits LB1 and LB2 have not been
programmed, the programmed code data can be read back
via the address and data lines for verification. The lock bits
cannot be verified directly. Verification of the lock bits is
achieved by observing that their features are enabled.
Chip Erase: The entire Flash array is erased electrically
by using the proper combination of control signals and by
holding ALE/PROG low for 10 ms. The code array is written
with all “1”s. The chip erase operation must be executed
before the code memory can be re-programmed.
Reading the Signature Bytes: The signature bytes are
read by the same procedure as a normal verification of
locations 030H, 031H, and 032H, except that P3.6 and
P3.7 must be pulled to a logic low. The values returned are
as follows.
(030H) = 1EH indicates manufactured by Atmel
(031H) = 51H indicates 89C51
(032H) = FFH indicates 12V programming
(032H) = 05H indicates 5V programming
Programming Interface
Every code byte in the Flash array can be written and the
entire array can be erased by using the appropriate combination of control signals. The write operation cycle is selftimed and once initiated, will automatically time itself to
completion.
All major programming vendors offer worldwide support for
the Atmel microcontroller series. Please contact your local
programming vendor for the appropriate software revision.
AT89C51
Flash Programming Modes
RST
PSEN
EA/VPP
P2.6
P2.7
P3.6
P3.7
Write Code Data
H
L
H/12V
L
H
H
H
Read Code Data
H
L
H
L
L
H
H
Bit - 1
H
L
H/12V
H
H
H
H
Bit - 2
H
L
H/12V
H
H
L
L
Bit - 3
H
L
H/12V
H
L
H
L
Chip Erase
H
L
H/12V
H
L
L
L
Read Signature Byte
H
L
H
L
L
L
L
Mode
Write Lock
Note:
ALE/PROG
H
(1)
H
1. Chip Erase requires a 10 ms PROG pulse.
Figure 3. Programming the Flash
Figure 4. Verifying the Flash
+5V
+5V
AT89C51
A0 - A7
ADDR.
OOOOH/OFFFH
A8 - A11
P1
P2.0 - P2.3
AT89C51
VCC
P0
PGM
DATA
A0 - A7
ADDR.
OOOOH/0FFFH
P2.7
P2.0 - P2.3
P0
P2.6
ALE
PROG
P3.6
SEE FLASH
PROGRAMMING
MODES TABLE
P2.7
EA
VIH/VPP
3-24 MHz
PGM DATA
(USE 10K
PULLUPS)
ALE
P3.6
VIH
P3.7
P3.7
XTAL2
VCC
A8 - A11
P2.6
SEE FLASH
PROGRAMMING
MODES TABLE
P1
XTAL2
EA
XTAL1
RST
3-24 MHz
XTAL1
GND
RST
PSEN
VIH
GND
VIH
PSEN
7
Flash Programming and Verification Waveforms - High-voltage Mode (VPP = 12V)
PROGRAMMING
ADDRESS
P1.0 - P1.7
P2.0 - P2.3
VERIFICATION
ADDRESS
tAVQV
PORT 0
DATA IN
tDVGL
tAVGL
tGHDX
DATA OUT
tGHAX
ALE/PROG
tSHGL
tGLGH
VPP
tGHSL
LOGIC 1
LOGIC 0
EA/VPP
tEHSH
tEHQZ
tELQV
P2.7
(ENABLE)
tGHBL
P3.4
(RDY/BSY)
BUSY
READY
tWC
Flash Programming and Verification Waveforms - Low-voltage Mode (VPP = 5V)
PROGRAMMING
ADDRESS
P1.0 - P1.7
P2.0 - P2.3
VERIFICATION
ADDRESS
tAVQV
PORT 0
DATA IN
tDVGL
tAVGL
tGHDX
DATA OUT
tGHAX
ALE/PROG
tSHGL
tGLGH
LOGIC 1
LOGIC 0
EA/VPP
tEHSH
tEHQZ
tELQV
P2.7
(ENABLE)
tGHBL
P3.4
(RDY/BSY)
BUSY
tWC
8
AT89C51
READY
AT89C51
Flash Programming and Verification Characteristics
TA = 0°C to 70°C, VCC = 5.0 ± 10%
Symbol
VPP
(1)
Parameter
Min
Max
Units
Programming Enable Voltage
11.5
12.5
V
1.0
mA
24
MHz
IPP(1)
Programming Enable Current
1/tCLCL
Oscillator Frequency
tAVGL
Address Setup to PROG Low
48tCLCL
tGHAX
Address Hold after PROG
48tCLCL
tDVGL
Data Setup to PROG Low
48tCLCL
tGHDX
Data Hold after PROG
48tCLCL
tEHSH
P2.7 (ENABLE) High to VPP
48tCLCL
tSHGL
VPP Setup to PROG Low
10
µs
tGHSL(1)
VPP Hold after PROG
10
µs
tGLGH
PROG Width
tAVQV
Address to Data Valid
48tCLCL
tELQV
ENABLE Low to Data Valid
48tCLCL
tEHQZ
Data Float after ENABLE
tGHBL
PROG High to BUSY Low
tWC
Note:
Byte Write Cycle Time
1. Only used in 12-volt programming mode.
3
1
0
110
µs
48tCLCL
1.0
µs
2.0
ms
9
Absolute Maximum Ratings*
Operating Temperature.................................. -55°C to +125°C
*NOTICE:
Storage Temperature ..................................... -65°C to +150°C
Voltage on Any Pin
with Respect to Ground .....................................-1.0V to +7.0V
Maximum Operating Voltage ............................................ 6.6V
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
DC Output Current...................................................... 15.0 mA
DC Characteristics
TA = -40°C to 85°C, VCC = 5.0V ± 20% (unless otherwise noted)
Symbol
Parameter
Condition
Min
Max
Units
VIL
Input Low-voltage
(Except EA)
-0.5
0.2 VCC - 0.1
V
VIL1
Input Low-voltage (EA)
-0.5
0.2 VCC - 0.3
V
VIH
Input High-voltage
0.2 VCC + 0.9
VCC + 0.5
V
VIH1
Input High-voltage
0.7 VCC
VCC + 0.5
V
IOL = 1.6 mA
0.45
V
IOL = 3.2 mA
0.45
V
VOL
Output Low-voltage
(Except XTAL1, RST)
(XTAL1, RST)
(1)
(Ports 1,2,3)
(1)
VOL1
Output Low-voltage
(Port 0, ALE, PSEN)
VOH
Output High-voltage
(Ports 1,2,3, ALE, PSEN)
IOH = -60 µA, VCC = 5V ± 10%
2.4
V
IOH = -25 µA
0.75 VCC
V
IOH = -10 µA
0.9 VCC
V
2.4
V
IOH = -300 µA
0.75 VCC
V
IOH = -80 µA
0.9 VCC
V
IOH = -800 µA, VCC = 5V ± 10%
VOH1
Output High-voltage
(Port 0 in External Bus Mode)
IIL
Logical 0 Input Current (Ports 1,2,3)
VIN = 0.45V
-50
µA
ITL
Logical 1 to 0 Transition Current
(Ports 1,2,3)
VIN = 2V, VCC = 5V ± 10%
-650
µA
ILI
Input Leakage Current (Port 0, EA)
0.45 < VIN < VCC
±10
µA
RRST
Reset Pull-down Resistor
300
KΩ
CIO
Pin Capacitance
Test Freq. = 1 MHz, TA = 25°C
10
pF
Active Mode, 12 MHz
20
mA
Idle Mode, 12 MHz
5
mA
VCC = 6V
100
µA
VCC = 3V
40
µA
50
Power Supply Current
ICC
Power-down Mode(2)
Notes:
10
1. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin: 10 mA
Maximum IOL per 8-bit port: Port 0: 26 mA
Ports 1, 2, 3: 15 mA
Maximum total IOL for all output pins: 71 mA
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater
than the listed test conditions.
2. Minimum VCC for Power-down is 2V.
AT89C51
AT89C51
AC Characteristics
Under operating conditions, load capacitance for Port 0, ALE/PROG, and PSEN = 100 pF; load capacitance for all other
outputs = 80 pF.
External Program and Data Memory Characteristics
12 MHz Oscillator
Min
Max
16 to 24 MHz Oscillator
Symbol
Parameter
Min
Max
Units
1/tCLCL
Oscillator Frequency
0
24
MHz
tLHLL
ALE Pulse Width
127
2tCLCL-40
ns
tAVLL
Address Valid to ALE Low
43
tCLCL-13
ns
tLLAX
Address Hold after ALE Low
48
tCLCL-20
ns
tLLIV
ALE Low to Valid Instruction In
tLLPL
ALE Low to PSEN Low
43
tCLCL-13
ns
tPLPH
PSEN Pulse Width
205
3tCLCL-20
ns
tPLIV
PSEN Low to Valid Instruction In
tPXIX
Input Instruction Hold after PSEN
tPXIZ
Input Instruction Float after PSEN
tPXAV
PSEN to Address Valid
tAVIV
Address to Valid Instruction In
312
5tCLCL-55
ns
tPLAZ
PSEN Low to Address Float
10
10
ns
tRLRH
RD Pulse Width
400
6tCLCL-100
ns
tWLWH
WR Pulse Width
400
6tCLCL-100
ns
tRLDV
RD Low to Valid Data In
tRHDX
Data Hold after RD
tRHDZ
Data Float after RD
97
2tCLCL-28
ns
tLLDV
ALE Low to Valid Data In
517
8tCLCL-150
ns
tAVDV
Address to Valid Data In
585
9tCLCL-165
ns
tLLWL
ALE Low to RD or WR Low
200
3tCLCL+50
ns
tAVWL
Address to RD or WR Low
203
4tCLCL-75
ns
tQVWX
Data Valid to WR Transition
23
tCLCL-20
ns
tQVWH
Data Valid to WR High
433
7tCLCL-120
ns
tWHQX
Data Hold after WR
33
tCLCL-20
ns
tRLAZ
RD Low to Address Float
tWHLH
RD or WR High to ALE High
233
4tCLCL-65
145
0
3tCLCL-45
0
59
75
tCLCL-8
0
5tCLCL-90
3tCLCL-50
0
43
123
tCLCL-20
ns
ns
0
300
ns
ns
tCLCL-10
252
ns
ns
ns
0
ns
tCLCL+25
ns
11
External Program Memory Read Cycle
tLHLL
ALE
tAVLL
tLLIV
tLLPL
tPLIV
PSEN
tPXAV
tPLAZ
tPXIZ
tLLAX
tPXIX
A0 - A7
PORT 0
tPLPH
INSTR IN
A0 - A7
tAVIV
PORT 2
A8 - A15
A8 - A15
External Data Memory Read Cycle
tLHLL
ALE
tWHLH
PSEN
tLLDV
tRLRH
tLLWL
RD
tLLAX
tAVLL
PORT 0
tRLDV
tRLAZ
A0 - A7 FROM RI OR DPL
tRHDZ
tRHDX
DATA IN
A0 - A7 FROM PCL
INSTR IN
tAVWL
tAVDV
PORT 2
12
P2.0 - P2.7 OR A8 - A15 FROM DPH
AT89C51
A8 - A15 FROM PCH
AT89C51
External Data Memory Write Cycle
tLHLL
ALE
tWHLH
PSEN
tLLWL
WR
tAVLL
tLLAX
tQVWX
A0 - A7 FROM RI OR DPL
PORT 0
tWLWH
tQVWH
DATA OUT
tWHQX
A0 - A7 FROM PCL
INSTR IN
tAVWL
PORT 2
P2.0 - P2.7 OR A8 - A15 FROM DPH
A8 - A15 FROM PCH
External Clock Drive Waveforms
tCHCX
VCC - 0.5V
tCHCX
tCLCH
tCHCL
0.7 VCC
0.2 VCC - 0.1V
0.45V
tCLCX
tCLCL
External Clock Drive
Symbol
Parameter
1/tCLCL
Oscillator Frequency
tCLCL
Clock Period
tCHCX
Min
Max
Units
0
24
MHz
41.6
ns
High Time
15
ns
tCLCX
Low Time
15
ns
tCLCH
Rise Time
20
ns
tCHCL
Fall Time
20
ns
13
Serial Port Timing: Shift Register Mode Test Conditions
(VCC = 5.0 V ± 20%; Load Capacitance = 80 pF)
12 MHz Osc
Variable Oscillator
Max
Min
Units
Symbol
Parameter
Min
Max
tXLXL
Serial Port Clock Cycle Time
1.0
12tCLCL
µs
tQVXH
Output Data Setup to Clock Rising Edge
700
10tCLCL-133
ns
tXHQX
Output Data Hold after Clock Rising Edge
50
2tCLCL-117
ns
tXHDX
Input Data Hold after Clock Rising Edge
0
0
ns
tXHDV
Clock Rising Edge to Input Data Valid
700
10tCLCL-133
ns
Shift Register Mode Timing Waveforms
INSTRUCTION
ALE
0
1
2
3
4
5
6
7
8
tXLXL
CLOCK
tQVXH
WRITE TO SBUF
tXHQX
0
1
tXHDV
OUTPUT DATA
CLEAR RI
VALID
2
3
4
5
6
tXHDX
VALID
SET TI
VALID
VALID
VALID
VALID
VALID
AC Testing Input/Output Waveforms(1)
Note:
14
Float Waveforms(1)
V LOAD+
0.2 VCC + 0.9V
TEST POINTS
0.45V
VALID
SET RI
INPUT DATA
VCC - 0.5V
7
AT89C51
V LOAD -
Note:
V OL -
0.1V
V OL +
0.1V
Timing Reference
Points
V LOAD
0.2 VCC - 0.1V
1. AC Inputs during testing are driven at VCC - 0.5V for a
logic 1 and 0.45V for a logic 0. Timing measurements
are made at VIH min. for a logic 1 and VIL max. for a
logic 0.
0.1V
0.1V
1. For timing purposes, a port pin is no longer floating
when a 100 mV change from load voltage occurs. A
port pin begins to float when 100 mV change from
the loaded VOH/VOL level occurs.
AT89C51
Ordering Information
Speed
(MHz)
Power
Supply
Ordering Code
Package
12
5V ± 20%
AT89C51-12AC
44A
Commercial
AT89C51-12JC
44J
(0° C to 70° C)
AT89C51-12PC
40P6
AT89C51-12QC
44Q
AT89C51-12AI
44A
Industrial
AT89C51-12JI
44J
(-40° C to 85° C)
AT89C51-12PI
40P6
AT89C51-12QI
44Q
AT89C51-16AC
44A
Commercial
AT89C51-16JC
44J
(0° C to 70° C)
AT89C51-16PC
40P6
AT89C51-16QC
44Q
AT89C51-16AI
44A
Industrial
AT89C51-16JI
44J
(-40° C to 85° C)
AT89C51-16PI
40P6
AT89C51-16QI
44Q
AT89C51-20AC
44A
Commercial
AT89C51-20JC
44J
(0° C to 70° C)
AT89C51-20PC
40P6
AT89C51-20QC
44Q
AT89C51-20AI
44A
Industrial
AT89C51-20JI
44J
(-40° C to 85° C)
AT89C51-20PI
40P6
AT89C51-20QI
44Q
AT89C51-24AC
44A
Commercial
AT89C51-24JC
44J
(0° C to 70° C)
AT89C51-24PC
40P6
AT89C51-24QC
44Q
AT89C51-24AI
44A
Industrial
AT89C51-24JI
44J
(-40° C to 85° C)
AT89C51-24PI
40P6
AT89C51-24QI
44Q
16
20
24
5V ± 20%
5V ± 20%
5V ± 20%
Operation Range
Package Type
44A
44-lead, Thin Plastic Gull Wing Quad Flatpack (TQFP)
44J
44-lead, Plastic J-leaded Chip Carrier (PLCC)
40P6
40-lead, 0.600” Wide, Plastic Dual Inline Package (PDIP)
44Q
44-lead, Plastic Gull Wing Quad Flatpack (PQFP)
15
Packaging Information
44A, 44-lead, Thin (1.0 mm) Plastic Gull Wing Quad
Flatpack (TQFP)
Dimensions in Millimeters and (Inches)*
44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC)
Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-018 AC
JEDEC STANDARD MS-026 ACB
12.21(0.478)
SQ
11.75(0.458)
PIN 1 ID
0.45(0.018)
0.30(0.012)
0.80(0.031) BSC
.045(1.14) X 45°
.045(1.14) X 30° - 45°
PIN NO. 1
IDENTIFY
.630(16.0)
.590(15.0)
.656(16.7)
SQ
.650(16.5)
.032(.813)
.026(.660)
.695(17.7)
SQ
.685(17.4)
.050(1.27) TYP
.500(12.7) REF SQ
10.10(0.394)
SQ
9.90(0.386)
.021(.533)
.013(.330)
.043(1.09)
.020(.508)
.120(3.05)
.090(2.29)
.180(4.57)
.165(4.19)
1.20(0.047) MAX
0
7
0.20(.008)
0.09(.003)
.012(.305)
.008(.203)
.022(.559) X 45° MAX (3X)
0.75(0.030)
0.45(0.018)
0.15(0.006)
0.05(0.002)
Controlling dimension: millimeters
40P6, 40-lead, 0.600" Wide, Plastic Dual Inline
Package (PDIP)
Dimensions in Inches and (Millimeters)
2.07(52.6)
2.04(51.8)
44Q, 44-lead, Plastic Quad Flat Package (PQFP)
Dimensions in Millimeters and (Inches)*
JEDEC STANDARD MS-022 AB
13.45 (0.525)
SQ
12.95 (0.506)
PIN
1
PIN 1 ID
.566(14.4)
.530(13.5)
0.50 (0.020)
0.35 (0.014)
0.80 (0.031) BSC
.090(2.29)
MAX
1.900(48.26) REF
.220(5.59)
MAX
.005(.127)
MIN
SEATING
PLANE
.065(1.65)
.015(.381)
.022(.559)
.014(.356)
.161(4.09)
.125(3.18)
.110(2.79)
.090(2.29)
.012(.305)
.008(.203)
.065(1.65)
.041(1.04)
10.10 (0.394)
SQ
9.90 (0.386)
.630(16.0)
.590(15.0)
2.45 (0.096) MAX
0 REF
15
.690(17.5)
.610(15.5)
0.17 (0.007)
0.13 (0.005)
0
7
1.03 (0.041)
0.78 (0.030)
Controlling dimension: millimeters
16
AT89C51
0.25 (0.010) MAX
Atmel Headquarters
Atmel Operations
Corporate Headquarters
Atmel Colorado Springs
2325 Orchard Parkway
San Jose, CA 95131
TEL (408) 441-0311
FAX (408) 487-2600
Europe
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TEL (719) 576-3300
FAX (719) 540-1759
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Atmel U.K., Ltd.
Coliseum Business Centre
Riverside Way
Camberley, Surrey GU15 3YL
England
TEL (44) 1276-686-677
FAX (44) 1276-686-697
Zone Industrielle
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France
TEL (33) 4-4253-6000
FAX (33) 4-4253-6001
Asia
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Hong Kong
TEL (852) 2721-9778
FAX (852) 2722-1369
Japan
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Japan
TEL (81) 3-3523-3551
FAX (81) 3-3523-7581
Fax-on-Demand
North America:
1-(800) 292-8635
International:
1-(408) 441-0732
e-mail
[email protected]
Web Site
http://www.atmel.com
BBS
1-(408) 436-4309
© Atmel Corporation 2000.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for
any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without
notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are
not authorized for use as critical components in life suppor t devices or systems.
Marks bearing
®
and/or
™
are registered trademarks and trademarks of Atmel Corporation.
Terms and product names in this document may be trademarks of others.
Printed on recycled paper.
0265G–02/00/xM
ANEXOS 3 - Fichas Técnicas do Hardware desenvolvido
XC9536PC
ccviii
9
1
XC9536 In-System Programmable
CPLD

December 4, 1998 (Version 5.0)
1
1*
Product Specification
Features
Power Management
•
•
5 ns pin-to-pin logic delays on all pins
fCNT to 100 MHz
•
•
•
36 macrocells with 800 usable gates
Up to 34 user I/O pins
5 V in-system programmable (ISP)
- Endurance of 10,000 program/erase cycles
- Program/erase over full commercial voltage and
temperature range
Enhanced pin-locking architecture
Flexible 36V18 Function Block
- 90 product terms drive any or all of 18 macrocells
within Function Block
- Global and product term clocks, output enables, set
and reset signals
Extensive IEEE Std 1149.1 boundary-scan (JTAG)
support
Programmable power reduction mode in each
macrocell
Slew rate control on individual outputs
User programmable ground pin capability
Extended pattern security features for design protection
High-drive 24 mA outputs
3.3 V or 5 V I/O capability
Advanced CMOS 5V FastFLASH technology
Supports parallel programming of more than one
XC9500 concurrently
Available in 44-pin PLCC, 44-pin VQFP, and 48-pin
CSP packages
Power dissipation can be reduced in the XC9536 by configuring macrocells to standard or low-power modes of operation. Unused macrocells are turned off to minimize power
dissipation.
•
•
•
•
•
•
•
•
•
•
ICC (mA) =
MCHP (1.7) + MCLP (0.9) + MC (0.006 mA/MHz) f
Where:
MCHP = Macrocells in high-performance mode
MCLP = Macrocells in low-power mode
MC = Total number of macrocells used
f = Clock frequency (MHz)
Figure 1 shows a typical calculation for the XC9536 device.
(83)
ance
erform
High P
Typical ICC (mA)
•
•
Operating current for each design can be approximated for
specific operating conditions using the following equation:
(50)
(50)
ower
Low P
(30)
Description
The XC9536 is a high-performance CPLD providing
advanced in-system programming and test capabilities for
general purpose logic integration. It is comprised of two
36V18 Function Blocks, providing 800 usable gates with
propagation delays of 5 ns. See Figure 2 for the architecture overview.
December 4, 1998 (Version 5.0)
0
50
Clock Frequency (MHz)
100
X5920
Figure 1: Typical ICC vs. Frequency For XC9536
1
XC9536 In-System Programmable CPLD
3
JTAG Port
1
JTAG
Controller
In-System Programming Controller
36
18
I/O
Function
Block 1
Macrocells
1 to 18
I/O
I/O
I/O
Blocks
I/O
I/O
I/O
FastCONNECT Switch Matrix
I/O
36
18
Function
Block 2
Macrocells
1 to 18
I/O
3
I/O/GCK
1
I/O/GSR
I/O/GTS
2
X5919
Figure 2: XC9536 Architecture
Note: Function Block outputs (indicated by the bold line) drive the I/O Blocks directly
2
December 4, 1998 (Version 5.0)
XC9536 In-System Programmable CPLD
Absolute Maximum Ratings
Symbol
VCC
VIN
VTS
TSTG
TSOL
Warning:
Parameter
Supply voltage relative to GND
DC input voltage relative to GND
Voltage applied to 3-state output with respect to GND
Storage temperature
Max soldering temperature (10 s @ 1/16 in = 1.5 mm)
Value
Units
-0.5 to 7.0
-0.5 to VCC + 0.5
-0.5 to VCC + 0.5
-65 to +150
+260
V
V
V
°C
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under
Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Rating conditions for extended periods
of time may affect device reliability.
Recommended Operating Conditions
Symbol
1
Parameter
VCCINT
Supply voltage for internal logic and input buffer
VCCIO
Supply voltage for output drivers for 5 V operation
Supply voltage for output drivers for 3.3 V operation
Low-level input voltage
High-level input voltage
Output voltage
VIL
VIH
VO
Min
Max
Units
4.75
(4.5)
4.75 (4.5)
3.0
0
2.0
0
5.25
(5.5)
5.25 (5.5)
3.6
0.80
VCCINT +0.5
VCCIO
V
V
V
V
V
V
Note 1. Numbers in parenthesis are for industrial-temperature range versions.
Endurance Characteristics
Symbol
Parameter
tDR
Data Retention
NPE
Program/Erase Cycles
December 4, 1998 (Version 5.0)
Min
Max
Units
20
-
Years
10,000
-
Cycles
3
XC9536 In-System Programmable CPLD
DC Characteristics Over Recommended Operating Conditions
Symbol
VOH
Parameter
Test Conditions
Min
Output high voltage for 5 V operation
IOH = -4.0 mA
VCC = Min
Output high voltage for 3.3 V operation IOH = -3.2 mA
VCC = Min
Output low voltage for 5 V operation
IOL = 24 mA
VCC = Min
Output low voltage for 3.3 V operation IOL = 10 mA
VCC = Min
Input leakage current
VCC = Max
VIN = GND or VCC
I/O high-Z leakage current
VCC = Max
VIN = GND or VCC
I/O capacitance
VIN = GND
f = 1.0 MHz
Operating Supply Current
VI = GND, No load
(low power mode, active)
f = 1.0 MHz
VOL
IIL
IIH
CIN
ICC
Max
Units
2.4
V
2.4
V
0.5
V
0.4
V
±10.0
µA
±10.0
µA
10.0
pF
mA
30 (Typ)
AC Characteristics
Symbol
Parameter
tPD
tSU
tH
tCO
fCNT1
fSYSTEM 2
tPSU
tPH
tPCO
tOE
tOD
tPOE
tPOD
tWLH
I/O to output valid
I/O setup time before GCK
I/O hold time after GCK
GCK to output valid
16-bit counter frequency
Multiple FB internal operating frequency
I/O setup time before p-term clock input
I/O hold time after p-term clock input
P-term clock to output valid
GTS to output valid
GTS to output disable
Product term OE to output enabled
Product term OE to output disabled
GCK pulse width (High or Low)
XC9536-5
XC9536-6
XC9536-7 XC9536-10 XC9536-15
Min Max Min Max Min Max Min Max Min Max
5.0
3.5
0.0
6.0
3.5
0.0
4.0
100.0
100.0
0.5
3.0
4.0
100.0
100.0
0.5
3.0
7.0
5.0
5.0
9.0
9.0
4.0
7.5
4.5
0.0
4.5
83.3
83.3
0.5
4.0
7.0
5.0
5.0
9.0
9.0
4.0
10.0
6.0
0.0
6.0
66.7
66.7
2.0
4.0
8.5
5.5
5.5
9.5
9.5
4.0
15.0
8.0
0.0
8.0
55.6
55.6
4.0
4.0
10.0
6.0
6.0
10.0
10.0
4.5
12.0
11.0
11.0
14.0
14.0
5.5
Units
ns
ns
ns
ns
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
Note: 1. fCNT is the fastest 16-bit counter frequency available.
fCNT is also the Export Control Maximum flip-flop toggle rate, fTOG.
2. fSYSTEM is the internal operating frequency for general purpose system designs spanning multiple FBs.
4
December 4, 1998 (Version 5.0)
XC9536 In-System Programmable CPLD
VTEST
R1
Output Type
Device Output
R2
VCCIO
VTEST
R1
R2
CL
5.0 V
5.0 V
160 Ω
120 Ω
35 pF
3.3 V
3.3 V
260 Ω
360 Ω
35 pF
CL
X5906
Figure 3: AC Load Circuit
Internal Timing Parameters
Symbol
Parameter
Buffer Delays
tIN
Input buffer delay
tGCK
GCK buffer delay
tGSR
GSR buffer delay
tGTS
GTS buffer delay
tOUT
Output buffer delay
tEN
Output buffer enable/disable delay
Product Term Control Delays
tPTCK Product term clock delay
tPTSR Product term set/reset delay
tPTTS Product term 3-state delay
Internal Register and Combinatorial delays
tPDI
Combinatorial logic propagation delay
tSUI
Register setup time
tHI
Register hold time
tCOI
Register clock to output valid time
tAOI
Register async. S/R to output delay
tRAI
Register async. S/R recovery before clock
tLOGI
Internal logic delay
tLOGILP Internal low power logic delay
Feedback Delays
tF
FastCONNECT matrix feeback delay
Time Adders
tPTA3
Incremental Product Term Allocator delay
tSLEW Slew-rate limited delay
XC9536-5 XC9536-6 XC9536-7 XC9536-10 XC9536-15
Min Max Min Max Min Max Min Max Min Max
Units
1.5
1.5
4.0
5.0
2.0
0.0
1.5
1.5
4.0
5.0
2.0
0.0
2.5
1.5
4.5
5.5
2.5
0.0
3.5
2.5
6.0
6.0
3.0
0.0
4.5
3.0
7.5
11.0
4.5
0.0
ns
ns
ns
ns
ns
ns
3.0
1.0
5.5
3.0
1.0
5.5
3.0
2.0
4.5
3.0
2.5
3.5
2.5
3.0
5.0
ns
ns
ns
0.5
1.5
0.5
1.0
3.0
1.0
9.0
1.0
9.0
2.0
10.0
2.5
11.0
3.0
11.5
ns
ns
ns
ns
ns
ns
ns
ns
6.0
6.0
8.0
9.5
11.0
ns
0.8
3.5
0.8
3.5
1.0
4.0
1.0
4.5
1.0
5.0
ns
ns
2.5
1.0
2.5
1.0
0.5
6.0
5.0
1.5
3.0
0.5
6.0
5.0
2.5
3.5
0.5
6.5
7.5
3.5
4.5
0.5
7.0
10.0
0.5
8.0
10.0
Note: 3. tPTA is multiplied by the span of the function as defined in the family data sheet.
December 4, 1998 (Version 5.0)
5
XC9536 In-System Programmable CPLD
XC9536 I/O Pins
Function
Macrocell
Block
PC44
1
1
2
1
2
3
1
3
5
1
4
4
1
5
6
1
6
8
1
7
7
1
8
9
1
9
11
1
10
12
1
11
13
1
12
14
1
13
18
1
14
19
1
15
20
1
16
22
1
17
24
1
18
–
Note: [1] Global control pin
VQ44
CS48
40
41
43
42
44
2
1
3
5
6
7
8
12
13
14
16
18
–
D6
C7
B7
C6
B6
A6
A7
C5
B5
A4
B4
A3
B2
B1
C2
C3
D2
-
BScan
Notes
Order
105
102
99
96
93
90
87
84
81
78
75
72
69
66
63
60
57
54
[1]
[1]
[1]
Function
Macrocell
Block
PC44
2
1
1
2
2
44
2
3
42
2
4
43
2
5
40
2
6
39
2
7
38
2
8
37
2
9
36
2
10
35
2
11
34
2
12
33
2
13
29
2
14
28
2
15
27
2
16
26
2
17
25
2
18
Note: [1] Global control pin
VQ44
CS48
39
38
36
37
34
33
32
31
30
29
28
27
23
22
21
20
19
-
D7
E5
E6
E7
F6
G7
G6
F5
G5
F4
G4
E3
F2
G1
F1
E2
E1
-
BScan
Notes
Order
51
48
45
42
39
36
33
30
27
24
21
18
15
12
9
6
3
0
[1]
[1]
[1]
XC9536 Global, JTAG and Power Pins
6
Pin Type
PC44
VQ44
CS48
I/O/GCK1
I/O/GCK2
I/O/GCK3
I/O/GTS1
I/O/GTS2
I/O/GSR
TCK
TDI
TDO
TMS
VCCINT 5 V
VCCIO 3.3 V/5 V
GND
No Connects
5
6
7
42
40
39
17
15
30
16
21,41
32
23,10,31
—
43
44
1
36
34
33
11
9
24
10
15,35
26
17,4,25
—
B7
B6
A7
E6
F6
G7
A1
B3
G2
A2
C1,F7
G3
A5, D1, F3
C4, D3, D4, E4
December 4, 1998 (Version 5.0)
XC9536 In-System Programmable CPLD
Ordering Information
XC9536 -5 PC 44 C
Device Type
Temperature Range
Number of Pins
Speed
Package Type
Packaging Options
Speed Options
-15
-10
-7
-6
-5
PC44 44-Pin Plastic Leaded Chip Carrier (PLCC)
VQ44 44-Pin Thin Quad Pack (VQFP)
CS48 48-Pin Chip Scale Package (CSP)
15 ns pin-to-pin delay
10 ns pin-to-pin delay
7.5 ns pin-to-pin delay
6 ns pin-to-pin delay
5 ns pin-to-pin delay
Temperature Options
C = Commercial (0°C to +70°C)
I = Industrial (–40°C to +85°C)
Component Availability
Pins
44
Type
Code
XC9536
–15
–10
–7
–6
–5
Plastic
PLCC
PC44
C,I
C,I
C,I
C
C
Plastic
VQFP
VQ44
C,I
C,I
C,I
C
C
48
Plastic
CSP
CS48
C
C
C
C = Commercial (0°C to +70°C), I = Industrial (–40°C to +85°C)
Revision Control
Date
6/3/98
11/2/98
12/04/98
Reason
Revise datasheet to reflect new CSP package pinouts & ordering code.
Revise datasheet to reflect new AC characteristics and Internal Timing Parameters.
Revise datasheet to remove PCI compliancy statement and remove tLF.
December 4, 1998 (Version 5.0)
7
ANEXOS 4 – Lista de Material
ANEXOS 4
ccxvii
ANEXOS 4 – Lista de Material
Lista do material
implementado
ccxviii
Trabalho Nº 1
Descrição do Material
7805
Díodo 1N4001
Resistência de 150 Ω
Resistência de 1 KΩ
Condensador de 0.01 µF
Condensador de 0.1 µF
Condensador de 1 µF
Condensador de 4.7 µF
Condensador de 10 µF
Condensador de 33 µF
Condensador de 22 pF
Condensador de 33 pF
Cristal de 11.0592 MHz
MAX233
MAX1112
L293
HEF4047
AT89C51
XC9536
Adaptador PLCC44 – DIP40
Botão de Pressão
Conector DB9 (Porta Série)
Cabo porta Série
Breadboard
Placa PCB
Quantidade
1X
4X
1X
1X
6X
1X
3X
2X
1X
1X
1X
2X
1X
1X
1X
2X
1X
1X
1X
1X
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Trabalho Nº 2
Descrição do Material
LDR
Fototransistor
Potenciómetro de 5 KΩ
Díodo 1N4001
Resistência de 10 KΩ
Resistência de 150 Ω
Resistência de 4,7 KΩ
Condensador de 0.01 µF
GL494
L293
Breadboard
Placa PCB
Quantidade
2X
1X
2X
1X
2X
2X
1X
2X
2X
1X
1X
1X