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CHAPTER 3-3 MEMORY CIRCUITS Latches To create a 1-bit memory, we need a circuit that somehow "remembers" previous input values. o Such a circuit can be constructed from 2 NOR gates, as illustrated in Figure 3-21(a). o Analogous circuits can be built from NAND gates. ----------------------------------------------------------------------------------------------------------------------------- --- ------------------------------------------------------------------------------------------------------------ -------------------Figure 3-21. (a) NOR latch in state 0. (b) NOR latch in state 1. (c) Truth table for NOR. The circuit of Figure 3-21(a) is called an SR latch. o It has 2 inputs, S for setting the latch, and R for resetting (clearing) it. o It also has 2 outputs, Q and Q , which are complementary. Let us assume that S=0, R=0. o It can easily be seen from the circuit that Q=0 and Q =1 is a consistent state. This state is depicted in Figure 3-21(a). o It can easily be seen from the circuit that Q=1 and Q =0 is also a consistent state. This state is depicted in Figure 3-21(b). o It can easily be seen from the circuit that Q=0 and Q =0 is impossible. o It can easily be seen from the circuit that Q=1 and Q =1 is also impossible. When R=S=0, the latch has exactly 2 stable states, which we will refer to as 0 and 1, depending on Q. Suppose the latch is in the stable state 0 (i.e. input S=0, input R=0, output Q=0). o setting S (making it 1) when the latch is in state 0 switches the latch to state 1. o setting R when the latch is in state 0 has no effect. Suppose the latch is in the stable state 1 (i.e. input S=0, input R=0, output Q=1). o Setting S to 1 when the latch is in state 1 has no effect. o Setting R switches the latch state from 1 to 0. Thus, the output of a latch depends not only on the input, but also the current state of the latch. In summary: o When S is set to 1, the latch ends up in state 1. o When R is set to 1, the latch ends up in state 0. o If S or R subsequently changes to 0, it has no effect on the latch. Clocked SR latches It is often convenient to prevent the latch from changing state except at certain specified times. -------------------------------------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------------------------- --Figure 3-22. A clocked SR latch. This circuit has an additional input, the clock, which is normally 0. o With the clock 0, both AND gates output 0, independent of S and R, and the latch does not change state. o When the clock is 1, the effect of the AND gates vanishes and the latch becomes sensitive to S and R. o Despite its name, the clock signal need not be driven by a clock. o The terms enable and strobe are also widely used to mean that the clock input is 1, i.e., the circuit is sensitive to the state of S and R. Up until now we have carefully swept the problem of what happens when both S and R are 1 under the rug. And for good reason: the circuit becomes non-deterministic when both R and S finally return to 0. o The only consistent state for S=R=1 is _____________, but as soon as both inputs return to 0, the latch must jump to 1 of its 2 stable states. o If either input drops back to 0 before the other, the one remaining 1 longest wins, because when just one input is 1, it forces the state. o If both inputs return to 0 simultaneously (which is very unlikely), the latch jumps to one of its stable states at random. Clocked D latches A good way to resolve the SR latch's ambiguity (caused when S=R=1) is to prevent it from occurring. Figure 3-23 gives a latch circuit with only 1 input, D. o Because the input to the lower AND gate is always the complement of the input to the upper one, the problem of both inputs being 1 never arises. o When D =1 and the clock is 1, the latch is driven into state ________. o When D=0 and the clock is 1, the latch is driven into state _________. o In other words, when the clock is 1, the current value of D is sampled and stored in the latch. -------------------------------------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------------------------- --Figure 3-23. A clocked D latch. This circuit, called a clocked D latch, is a true 1-bit memory. The value stored is always available at Q. o To load the current value of D into the memory at a particular instant in time, a positive pulse is put on the clock line. o Note that this circuit requires 11 transistors. More sophisticated (but less obvious) circuits can store 1 bit with as few as 6 transistors. In practice, such designs are normally used. Flip-flops In many circuits it is necessary to sample the value on a certain line at a particular instant in time and store it. o In practice, generating very short pulses can be difficult. o Thus, a variation on the clocked D latch, called a flip-flop, has been developed. In a flip-flop, the state transition does not occur when the clock is 1 but during the clock transition from 0 to 1 (rising edge) or from 1 to 0 (falling edge) instead. o Thus the length of the clock pulse is unimportant, as long as the transitions occur fast. Thus, the difference between a flip-flop and a latch is that a flip-flop is edge-triggered, whereas a latch is level-triggered. There are various approaches to designing a flip-flop. o For example, if there were some way to generate a very short pulse on the rising edge of the clock signal, that pulse could be fed into a D latch. -------------------------------------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------------------------- --Figure 3-24. (a) A pulse generator. (b) Timing at 4 points in the circuit. Suppose that we measure the voltage at the 4 measuring points a, b, c, and d (shown in Figure 3-24a). o The input signal, measured at a, is a long clock pulse, as shown in Figure 3-24(b) on the bottom. o The signal at b is shown above it, and it is both inverted and delayed slightly, typically hundreds of picoseconds, depending on the kind of inverter used. o The signal at c is delayed too, but only by the signal propagation time (at the speed of light). Thus for all intents and purposes, the signal at c is as good as identical to the signal at a. o When the inputs to the AND gate, b and c, are ANDed together, the result is a short pulse, as shown in Figure 3-24(b), where the width of the pulse, Δ, is equal to the gate delay of the inverter. o The output of the AND gate is just this pulse shifted by the delay of the AND gate, as shown at the top of Figure 3-24(b). This time shifting just means that the D latch will be activated at a fixed delay after the rising edge of the clock, but it has no effect on the pulse width. ----------------------------------------------------------------------------------------------------------------------------- --- -------------------------------------------------------------------------------------------------------------------------------Figure 3-25. A D flip-flop. The standard symbols for latches and flip-flops are shown in Figure 3-26. o Figure 3-26(a) is a latch whose state is loaded when the clock CK is 1, in contrast to Figure 326(b) which is a latch whose clock is normally 1 but which drops to 0 momentarily to load the state from D. o Figure 3-26(c) and (d) are flip-flops rather than latches, which is indicated by the pointy symbol on the clock inputs. o Figure 3-26(c) changes state on the rising edge of the clock pulse (0 to 1 transition), whereas Figure 3-26(d) changes state on the falling edge (1 to 0 transition). o Many, but not all, latches and flip-flops also have Q as an output, and some have 2 additional inputs Set or Preset (force state to Q=1) and Reset or Clear (force state to Q=0). The 4 latches and flip-flops in Figure 3-26 are all 1-bit memory. o To read from this memory, sample the value at Q. o To write to this memory, set D to the value to be stored and then assert CK. o To set this memory, assert Set and then assert CK. o To clear this memory, assert Reset and then assert CK. --------------------------------------------------------------------------------------------- ----------------------------------- ----------------------------------------------------------------------------------------------------------------------------- --Figure 3-26. D latches and flip-flops. Registers The register in Figure 3-27 shows how 8 flip-flops can be ganged together to form an 8-bit register. o The register accepts an 8-bit input value (I0 to I7) when the clock CK transitions. o To implement a register, all the clock lines are connected to the same input signal CK, such that when the clock transitions, each register will accept the new 8-bit data value on the input bus. o The flip-flops themselves are of the Figure 3-26(d) type, but the inversion bubbles on the flipflops are canceled by the inverter tied to the clock signal CK, such that the flip-flops are loaded on the rising transition of the clock. An input signal may not have enough current to drive all 8 flip-flops; the input inverter is really being used as an amplifier. o All 8 clear signals are also ganged, so when the clear signal CLR goes to 0, all the flip-flops are forced to their 0 state. ----------------------------------------------------------------------------------------------------------------------------- --- -------------------------------------------------------------------------------------------------------------------------------Figure 3-27. An 8-bit register constructed from single-bit flip-flops. Memory organization A widely used memory organization is shown in Figure 3-28. o This example illustrates a memory with 4 3-bit words. o Each operation reads or writes a full 3-bit word. o The design extends easily to large memories. o Note the number of words is always a power of 2. -------------------------------------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------------------------- --Figure 3-28. Logic diagram for a 4x3 memory. Each row is one of the 4 3-bit words. A read or write operation always reads or writes a complete word. While the memory of Figure 3-28 may look complicated at first, it is really quite simple due to its regular structure. o It has 8 input lines and 3 output lines. 3 inputs are data: I0, I1, I2; 2 are for the address: A0 and A1; and 3 are for control: CS for ChipSelect, RD for distinguishing between read and write, and OE for OutputEnable. The 3 outputs are for data: O0, O1, and O2. o It is interesting to note that this 12-bit memory requires fewer signals than the previous 8-bit register. The 8-bit register requires ___ signals including power and ground, while the 12-bit memory requires only ___ signals. To select this memory chip, external logic must set CS high (1) and also set RD high for read and low (0) for write. o The 2 address lines must be set to indicate which of the 4 3-bit words is to be read or written. o Although we could have designed a circuit in which the 3 OR gates were just fed into the 3 output data lines, doing so sometimes causes problems. In particular, we have shown the data input lines and the data output lines as being different, but in actual memories the same lines are used. If we had tied the OR gates to the data output lines, the chip would try to output data, i.e., force each line to a specific value, even on writes, thus interfering with the input data. For this reason, it is desirable to have a way to connect the OR gates to the data output lines on reads but disconnect them completely on writes. What we need is an electronic switch that can make or break a connection in a fraction of a nsec. Fortunately, such switches exist. --------------------------------------------------------------------------------------------------------- ----------------------- ----------------------------------------------------------------------------------------------------------------------------- --- Figure 3-29. (a) A non-inverting buffer. (b) Effect of (a) when control is high. (c) Effect of (a) when control is low. (d) An inverting buffer. Memory chips The nice thing about the memory of Figure 3-28 is that it extends easily to larger sizes. o To extend it to 4x8 we must add o To go from 4x3 to 8x3 we must add o With this kind of structure, the number of words in the memory should be __________________ for max efficiency, but the number of bits in a word can be _________________. For any given memory size, there are various ways of organizing the chip. -------------------------------------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------------------------- --Figure 3-30. 2 ways of organizing a 4-Mbit memory chip. In Figure 3-30(a), 19 address lines are needed to address 1 of the 512K bytes, and 8 data lines are needed for loading or storing the byte selected. o A note on terminology is in order here. On some pins, the high voltage causes an action to happen. On others, the low voltage causes the action. To avoid confusion, we will consistently say that a signal is asserted (rather than saying it goes high or it goes low) to mean that it is set to cause some action. Thus for some pins, asserting it means setting it high. For others, it means setting the pin low. Pins that are asserted low are given signal names containing an overbar. Thus a signal named CS is asserted high, but one named CS is asserted low. The opposite of asserted is negated. When nothing special is happening, pins are negated. o Since a computer normally has many memory chips, a signal is needed to select the chip that is currently needed so that it responds and all the others do not. The CS (ChipSelect) signal is provided for this purpose. It is asserted to enable the chip. o Also, a way is needed to distinguish reads from writes. The WE signal (WriteEnable) is used to indicate that data are being written rather than being read. o Finally, the OE (OutputEnable) signal is asserted to drive the output signal. When it is not asserted, the chip output is disconnected from the circuit. In Figure 3-30(b), a different addressing scheme is used. o Internally, this chip is organized as a 2048x2048 matrix of 1-bit cells, which gives 4 Mbits. o To address the chip: First a row is selected by putting its 11-bit number on the address pins and the RAS (RowAddressStrobe) is asserted. After that, an 11-bit column number is put on the address pins and CAS (ColumnAddressStrobe) is asserted. The chip responds by accepting or outputting one data bit. Large memory chips are often constructed as nXn matrices that are addressed by row and column. o This organization reduces the number of pins required but also makes addressing the chip slower. Years ago, the largest memory chips were often organized like Figure 3-30(b). o As memory words have grown from 8 bits to 32 bits and beyond, 1-bit wide chips began to be inconvenient. To build a memory with a 32-bit word from 4096Kx1 chips requires 32 chips in parallel. To avoid having 32 chips for memory, most chip manufacturers now have chip families with 4-, 8-, and 16-bit widths. 2 examples of modern 512-Mbit chips are given in Figure 3-31. o These chips have 4 internal memory banks of 128 Mbit each, requiring 2 bank select lines to choose a bank. o The design of Figure 3-31(a) is a 32Mx16 design (each bank is 8Mx16). Each bank is organized as an 8Kx1K matrix of 16-bit words. So the design uses 2 lines for the bank select, 13 lines for the RAS signal, 10 lines for the CAS signal. Together, these 25 signals allow each of the 225 =32M internal 16-bit cells to be addressed. o The design of Figure 3-31(b) is a 128Mx4 design (each bank is 32Mx4). Each bank is organized as an 8Kx4K matrix of 4-bit words. So the design uses 2 lines for the bank select, 13 lines for the RAS signal, 12 lines for the CAS signal. Together, these 27 signals allow each of the 227 =128M internal 4-bit cells to be addressed. ------------------------------------------------------------------------------------- ------------------------------------------- ----------------------------------------------------------------------------------------------------------------------------- --Figure 3-31. 2 ways of organizing a 512-Mbit memory chip. These examples demonstrate 2 separate and independent issues for memory chip design. o First is the output width: does the chip deliver 1, 4, 8, 16, or some other number of bits at once? o Second, are all the address bits presented on separate pins at once or are the row and columns presented sequentially as in the examples of Figure 3-31? RAMs The memories we have studied so far can all be read and written. o Such memories are called RAMs (Random Access Memories), which is a misnomer because all memory chips are randomly accessible, but the term is well established. o RAMs come in 2 varieties, static (SRAMs) and dynamic (DRAMs). SRAMs are constructed internally using circuits similar to our basic D flip-flop. o These memories have the property that their contents are retained as long as the power is kept on, seconds, minutes, hours, even days. o SRAMs are very fast. A typical access times is on the order of a nsec or less. For this reason, SRAMs are popular as cache memory. DRAMs, in contrast, do not use flip-flops. o Instead, a DRAM is an array of cells, each cell containing 1 transistor and a tiny capacitor. o The capacitors can be charged or discharged, allowing 0 and 1 to be stored. o Because the electric charge tends to leak out, each bit in a DRAM must be refreshed (reloaded) every few msecs to prevent the data from leaking away. o Because external logic must take care of the refreshing, DRAMs require more complex interfacing than static ones, although in many applications this disadvantage is compensated by their larger capacities. o Since DRAMs need only 1 transistor and 1 capacitor per bit (vs 6 transistors/bit for the best SRAM), DRAMs have a very high density (many bits for chip). For this reason, main memories are nearly always built out of DRAMs. o However, this large capacity has a price: DRAMs are slow (tens of nsec). o Thus the combination of a SRAM cache and a DRAM main memory attempts to combine the good properties of each. Several types of DRAM chips exist: o FPM (Fast Page Mode) DRAM. o EDO (Extended Data Output) DRAM. o When processors got so fast that faster memories were really needed, FPM and EDO were replaced by SDRAM (Synchronized DRAM). o The next improvement over SDRAM was DDR SDRAM (Double data rate). With this kind of memory, the memory chip produces output on both the rising edge of the clock and the falling edge, doubling the data rate. Thus an 8-bit wide DDR chip running at 200 MHz outputs 2 8-bit values 200 million times a second, giving a theoretical burst rate of _____ Gbps. The DDR2 and DDR3 memory interfaces provide additional performance over DDR by increasing the memory-bus speeds to 533 MHz and 1067 MHz, respectively. Nonvolatile memory chips In many applications such as toys and appliances, the program and some of the data must remain stored even when the power is turned off. Furthermore, once installed, neither the program nor the data are ever changed. These requirements have led to the development of ROM (Read-Only memory), which cannot be changed or erased, intentionally or otherwise. o The data in a ROM are inserted during its manufacture, essentially by exposing a photosensitive material through a mask containing the desired bit pattern and then etching away the exposed (or unexposed) surface. The only way to change the program in a ROM is to replace the entire chip. o However, they are inflexible because they cannot be changed after manufacture, and the turnaround time between placing an order and receiving the ROMs may be weeks. To make it easier for companies to develop new ROM-based products, the PROM (Programmable ROM) was invented. o A PROM is like a ROM, except that it can be programmed once in the field, eliminating the turnaround time. The next generation in this line was the EPROM (Erasable PROM), which can be field programmed and also field erased. Even better than the EPROM is the EEPROM (Electrically Erasable PROM), which can be erased by applying pulses to it instead of requiring it to be put in a special chamber for exposure to ultraviolet light. o In addition, an EEPROM can be reprogrammed in place whereas an EPROM has to be inserted in a special EPROM programming device to be programmed. A more recent kind of EEPROM is flash memory. o Flash memory is now starting to replace disks. As a disk, flash memory provides faster access times at lower power, but with a much higher cost per bit. Problems 1. The circuit of Figure 3-25 is a flip-flop that is triggered on the rising edge of the clock. Let us replace the AND gate in the pulse generator (see Figure 3-24) by a NOR gate. a. b. Redraw Figure 3-24(a) and Figure 3.24(b). Now, let us modify the flip-flop in Figure 3-25 to using this modified pulse generator. How is this flip-flop different from the original? 2. The 4x3 memory of Figure 3-28 uses 22 AND gates and 3 OR gates. If the circuit were to be expanded to 256x8, how many of each would be needed? 3. A computer with a 32-bit wide data bus uses 1Mx1 dynamic RAM memory chips. What is the smallest memory (in bytes) that this computer can have?
