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The Devices: Diode [Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.] EE415 VLSI Design Goal of this chapter •Present intuitive understanding of device operation •Introduction of basic device equations •Introduction of models for manual analysis •Introduction of models for SPICE simulation •Analysis of secondary deep-sub-micron effects •Future trends EE415 VLSI Design Outline Motivation and Goals Semiconductor Basics Diode Structure Operation » Static model – Depletion capacitance – Carrier density profiles Diffusion capacitance » Dynamic response – Switching speed Spice model EE415 VLSI Design next session Semiconductor Basics I Electrons in intrinsic (pure) Silicon » » » » » covalently bonded to atoms “juggled” between neighbors thermally activated: density eT move around the lattice, if free leave a positively charged `hole’ behind EE415 VLSI Design http://www.masstech.org/cleanenergy/solar_info/images/crystal.gif Semiconductor Basics II Two types of intrinsic carriers » » » » Electrons (ni) and holes (pi) In an intrinsic (no doping) material, ni=pi At 300K, ni=pi is low (1010cm-3) Use doping to improve conductivity EE415 VLSI Design Semiconductor Basics III Extrinsic carriers » Also two types of dopants (donors or acceptors) – Donors bring electron (n-type) and become ive ions – Acceptors bring holes (p-type) and become ive ions » Substantially higher densities (1015cm-3) » Majority and minority carriers – if n>>p (n-type) electrons majority and holes minority – Random recombination and thermal generation EE415 VLSI Design The Diode B A Al SiO 2 p n Cross section of pn-junction in an IC process EE415 VLSI Design N-type region P-type region doped with donor impurities (phosphorus, arsenic) doped with acceptor impurities (boron) The Diode Simplified structure A p Al A n The pn region is assumed to be thin (step or abrupt junction) EE415 VLSI Design B One-dimensional representation B diode symbol Different concentrations of electrons (and holes) of the p and ntype regions cause a concentration gradient at the boundary Depletion Region •Concentration Gradient causes electrons to diffuse from n to p, and holes to diffuse from p to n •This produces immobile ions in the vicinity of the boundary •Region at the junction with the charged ions is called the depletion region or space-charge region •Charges create electric field that attracts the minority carriers, causing them to drift •Drift counteracts diffusion causing equilibrium ( Idrift = -Idiffusion ) hole diffusion electron diffusion p n hole drift electron drift EE415 VLSI Design Depletion Region •Zero bias conditions hole diffusion electron diffusion p •p more heavily doped than n (NA > NB) •Electric field gives rise to potential difference in the junction, known as the built-in potential (a) Current flow. n hole drift electron drift Charge Density + x Distance - Electrical Field (b) Charge density. x (c) Electric field. V Potential -W 1 EE415 VLSI Design W2 x (d) Electrostatic potential. Built-in Potential N A ND 0 T ln 2 n i Where T is the thermal voltage kT T 26mV (at 300 K ) q ni is the intrinsic carrier concentration for pure Si (1.5 X 1010 cm-3 at 300K), so for 1 1 N A 1015 3 , N B 1016 3 , cm cm 10151016 0 26 ln 1.5 *1010 EE415 VLSI Design mV 638mV 2 Forward Bias hole diffusion electron diffusion p n hole drift electron drift + - •Applied potential lowers the potential barrier, Idiffusion > I drift •Mobile carriers drift through the dep. region into neutral regions •become excess minority carriers and diffuse towards terminals •Read about drift and diffusion currents at: •http://ece-www.colorado.edu/~bart/book/book/chapter2/ch2_10.htm EE415 VLSI Design Forward Bias n p (x) pn (x) Lp pn0 np0 -Wp p-region -W1 0 W2 Metal contact to n-region pn (W2) minority carrier concentration Wn n-region diffusion Typically avoided in Digital ICs EE415 VLSI Design x Reverse Bias hole diffusion electron diffusion p n hole drift electron drift - + •Applied potential increases the potential barrier •Diffusion current is reduced •Diode works in the reverse bias with a very small drift current EE415 VLSI Design pn0 np0 n p0 -Wp p-region -W1 0 Wn W2 n-region diffusion The Dominant Operation Mode EE415 VLSI Design Metal contact to n-region Reverse Bias x Models for Manual Analysis + ID = IS(eV D/T – 1) VD ID + + VD – (a) Ideal diode model •Accurate •Strongly non-linear •Prevents fast DC bias calculations EE415 VLSI Design – VDon – (b) First-order diode model •Conducting diode replaced by voltage source VDon=0.7V •Good for first order approximation Typical Diode Parameters Geometry, doping and material constants lumped in Is Diffusion coefficient minority carrier concentration + VD ID = IS(eV D/T – 1) – •Dn=25 cm2/sec •Dp=10cm2/sec •Wn=5 mm •Wp=0.7 mm •W2=0.15 mm •W1=0.03 mm EE415 VLSI Design I S qAD ( WnpWn 02 W pn Wp 01 ) D p typical value I S 10 17 A / mm 2 D n Diode Current VDon 0.7V VDon 0.7V Ideal diode equation: EE415 VLSI Design Depletion Capacitance Due to depletion charges » VD changes space charge » Forms a capacitor Cj – Charge modulated by voltage Ideality factor (m) depends on junction gradient EE415 VLSI Design Equivalent Capacitances I Linearize diode capacitances » Cj is a non-linear function of VD – When bias changes then Cj also changes – Hard to use in manual analyses » Instead use equivalent capacitance – Gives the same total charge for a given VD transition » Equivalent depletion capacitance – Must be worked out for a given V1V2 transition Q j Q j (V2 ) Q j (V1 ) Ceq K eqC j 0 VD V2 V1 0m (0 V2 )1m (0 V1 )1m K eq (V2 V1 )(1 m) EE415 VLSI Design Equivalent Capacitances II » Equivalent diffusion capacitance – Must be worked out for currents at given V1V2 transition Q j I D (V2 ) I D (V1 ) Cd (V2 ) Cd (V1 ) Ceq T T VD V2 V1 V2 V1 Ceq depends on process constants and {V1,V2} » Example: – for AD=0.5 mm2 Cj0=2 fF/mm2, 0=0.64 V and m=0.5 EE415 VLSI Design then Keq0.622 and Ceq1.24 fF/mm2 if switched between 0 and -2.5 V So unit capacitance Cj 0.9 fF/mm2 or Cj 0.45 fF for the total diode area Secondary Effects: Breakdown Cannot bear too large reverse biases » Drift field in depletion region will get extremely large » Minority carriers caught in this large field will get very energetic – Energetic carriers can knock atoms and create a new n-p pair – These carriers will get energetic, too, and so on: thus large currents! 0.1 Two types » Avalanche breakdown ID (A) – Above mechanism » Zener breakdown – More complicated 0 –0.1 –25.0 EE415 VLSI Design –15.0 –5.0 VD (V) 0 5.0 Can damage diode Diode SPICE Model Required for circuit simulations » Must capture important characteristics but also remain efficient » Extra parameter in the model: n (emission coefficient, 1 n 2) – Fixes non-ideal behavior due to broken assumptions Additional series resistance accounts for body+contact Nonlinear capacitance includes both CD and Cj I D I S (eVD /nT 1) RS + VD - EE415 VLSI Design ID CD SPICE Parameters Often supplied by the fab to the designer » If not must be measured and fit the parameters Assumes default values, if not explicitly defined Pay attention to the units and spelling EE415 VLSI Design