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Proposal of CSP based Network Design and Construction Kazuto Tanaka ,Satoshi Iwanami ,Takeshi Yamakawa, Chikara Fukunaga(Tokyo Metropolitan University) Kazuto Matsui(Prominent Network inc.) Takashi Yoshida(Smart Scape inc.) 5.nov.2008 k.tanaka SpW Conf. at Nara 1 SpaceWire Network as a parallel system Parallel system with many processors and front-end devices Extremely strict care to avoid resource conflicts and deadlocks for system design sensor1 processor1 sensor3 sensor2 processor2 5.nov.2008 k.tanaka SpW Conf. at Nara 2 CSP(Communicating Sequential Processes) A formal design method for parallel processing systems Parallel processing with channel communications Synchronization of processes Data sharing through channels between processes No shared memory between processes sensor1 processor1 sensor3 sensor2 :channel communication :process processor2 Refinement with mathematical deduction Check possible failures (livelock, deadlock) 5.nov.2008 k.tanaka SpW Conf. at Nara 3 Router Network System(IEEE1355) Network on an FPGA chip Components TPCORE (processor) OD convertor (protocol convertor) Router (link switch unit) FPGA ・ ・ ・ OD convertor TPCORE 0 Router ・ ・ ・ OD convertor TPCORE 1 OD convertor TPCORE 2 IEEE1355 ・ ・ ・ * We regard SpW and IEEE1355 are almost identical for the moment 5.nov.2008 k.tanaka SpW Conf. at Nara 4 TPCORE Processor (homemade 2003) Clock frequency : 24MHz Instruction set compatible with Rtransputer (Inmos ltd., UK) Parallel processing with Occam (language) without Operating System Flexible networks (on a FPGA chip) with four external I/Fs (OS-Link) OS-Link is a simple bit serial link No destination address in OS-Link Host PC Host PC Host PC TP0 :process 5.nov.2008 TP2 TP0 TP3 TP1 mesh k.tanaka TP0 OS-Link SpW Conf. at Nara TP3 TP2 TP1 tree 5 OS-Link and IEEE1355(DS)-Link OS-Link Simple protocol No destination address IEEE1355(DS)-Link Complex protocol, layered structure (packet , character (= token )) Header contains destination address IEEE1355(DS)-Link OS-Link ・・・・・・・・・・ ・・・・・・ end of message data ・・ header 2 start-bit data end of packet 1 end-bit 1parity-bit 5.nov.2008 ・・ k.tanaka 1 control or data select bit SpW Conf. at Nara 6 OD-convertor OS to DS and DS to OS conversion Main components FCC (Flow Control Character) –rx ,FCC-tx Flow control for communication character transmission of DS-Link protocol DS selector Selection of FCC or other character (both directional) OD convertor(DO convertor) DS DS-Linkout DS-Linkin DS tx DS rx selector FCC FCC-rx character Parity check FCC-tx FCC 5.nov.2008 FIFO character k.tanaka OS rx FIFO SpW Conf. at Nara OS tx OS-Linkin OS-Linkout 7 Router Components DS-analyzer Pick up the destination address from header of input packet FCC and character transmission and DS selector Crossbar (Xbar) Connection to the destination channel (bidirectional) Router Xbar control Xbar TPCORE 0 OD DS analyzer DS analyzer OD TPCORE 1 DS analyzer OD TPCORE 2 : destination address 5.nov.2008 k.tanaka SpW Conf. at Nara 8 Time Sequence of the Network Packet transmitted by TPCORE0 (OS-Link) Converted to DS-Link by OD convertor Router switch Reverted to OS-Link Data accepted by TPCORE2(OS-Link) TP0 OS OD DS Router OD OS TP2 DS example of packet transfer:address=2,data=FF OS DS DS 3.32 μs 5.nov.2008 k.tanaka SpW Conf. at Nara OS 9 Summary Network-Router and OD convertor (IEEE1355) have been designed based on CSP. By refinement checking ,We find no deadlock , no livelock in these devices as a parallel system. Detailed discussion of CSP will be found in our another presentation (Poster). Correct data communication has been confirmed using TPCOREs. We measured DS-Link transfer rate . It is 20.29Mbps. Theoretical value is 20.28Mbps . The difference is less than a clock width (48MHz). The good agreement has been achieved. From this study, we found CSP as a good design method for parallel systems. Thank you for your attention !! 5.nov.2008 k.tanaka SpW Conf. at Nara 10