Download Figure 8: Diagram of how the MitySOM Module

Flight Computer for IlliniSat-2
DESIGN REVIEW
ECE445 – Senior Design Laboratory
Daniel Brackmann
Mark Mahowald
Anuj Pasricha
Team 12
TA: Kevin Bassett
October 6, 2014
Table of Contents
1.
2.
INTRODUCTION ..................................................................................................................................... 3
1.1
Statement of Purpose ................................................................................................................... 3
1.2
Objectives...................................................................................................................................... 4
1.2.1
Goals...................................................................................................................................... 4
1.2.2
Functions ............................................................................................................................... 4
1.2.3
Benefits ................................................................................................................................. 4
1.2.4
Features ................................................................................................................................ 4
DESIGN .................................................................................................................................................. 5
2.1
Block Diagrams .............................................................................................................................. 5
2.2
Individual Block Descriptions ........................................................................................................ 8
2.2.1
USB to UART .......................................................................................................................... 8
2.2.2
TTL to RS485 .......................................................................................................................... 8
2.2.3
TTL to RS422.......................................................................................................................... 9
2.2.4
NAND Flash ........................................................................................................................... 9
2.2.5
Power Circuitry.................................................................................................................... 10
2.3
2.3.1
Hirose DF11_6DP Connector............................................................................................... 11
2.3.2
Backbone Connector ........................................................................................................... 11
2.3.3
MitySOM Module Connector .............................................................................................. 12
2.4
Reserved Circuit Descriptions ..................................................................................................... 13
2.4.1
UART_0................................................................................................................................ 13
2.4.2
SPI_0, I2C_1......................................................................................................................... 13
2.5
3.
Connector Descriptions............................................................................................................... 11
Schematics .................................................................................................................................. 14
REQUIREMENTS AND VERIFICATION .................................................................................................. 17
3.1
Requirements Summary ............................................................................................................. 17
3.2
Verification Summary ................................................................................................................. 18
3.3
Outer Space................................................................................................................................. 19
3.4
Board Dimensions ....................................................................................................................... 20
3.5
MitySOM Module Keep-Out Areas ............................................................................................. 21
3.6
Communications ......................................................................................................................... 22
3.7
Power .......................................................................................................................................... 24
1
4.
5.
3.8
Possible Simulation ..................................................................................................................... 26
3.9
Tolerance Analysis....................................................................................................................... 27
COST ANALYSIS.................................................................................................................................... 29
4.1
Labor ........................................................................................................................................... 29
4.2
Parts ............................................................................................................................................ 29
4.3
Grand Total ................................................................................................................................. 30
4.4
Schedule ...................................................................................................................................... 30
ETHICS AND SAFETY ............................................................................................................................ 32
5.1
Ethics ........................................................................................................................................... 32
5.2
Safety .......................................................................................................................................... 34
6.
APPENDICES ........................................................................................................................................ 35
7.
CITATIONS ........................................................................................................................................... 44
2
1. INTRODUCTION
1.1 Statement of Purpose
The Illini CubeSat group needs to create an interface board (known as a Control and Data
Handling board, or C&DH for short) for the MitySOM ARM chip that would meet very
specific physical constraints because a board does not currently exist that meets these
requirements. Those constraints include a height of no more than 8 millimeters, no more than
700 milliamp current, as well as a number of UART connections to communicate with two
radios, two payload and two other peripherals not specified. There are additional physical
requirements that are discussed in a later section. Furthermore, test runs to be performed on
the board to make sure the MitySOM and the C&DH board communicate with each other in
the same manner as the current development board that is provided by the Critical Link
company.
The end result of this work will be integrated into the CubeSat that will then be launched into
space for data acquisition. A picture of how this board will physically fit into the CubeSat is
shown in the Appendix pages.
3
1.2 Objectives
1.2.1
Goals
● Develop a board that has only the necessary peripherals for the MitySOM
● Develop a board that has the proper heat sinking features for use in space
● Develop a board that has the correct physical characteristics for items such as
connectors and IC’s
● Develop a board that will function in space
1.2.2
Functions
● Board allows access to UART connections for various payloads
● Board allows access to the power circuitry of the CubeSat
● Board efficiently heat sinks the MitySOM to prevent overheating
1.2.3
Benefits
● Allows the MitySOM to go into space
● Allows easy access to other components of the satellite
● Fulfills a needed solution for the CubeSat project
1.2.4
Features
● 2 USB to UART adaptors
● 5 UART to RS422 transceivers
● 1 UART to RS485 transceiver
● 1 additional UART in reserve
● Backbone connector that links all transceivers to peripherals
● 1 GB of additional NAND Flash
4
2. DESIGN
2.1 Block Diagrams
Block diagrams begin on the following page. A brief description of the overall block
diagrams is provided below. More detailed explanations of individual blocks can be found in
Section 2.2 Block Descriptions.
Block Diagram 1 is the Communication diagram for the C&DH board. The MitySOM335x
Module connects into the C&DH board through a connector. This connector provides access
to all of the pins on the MitySOM335x, allowing the C&DH board to route all of the signal
communications as shown below.
Block Diagram 2 is the Power Flow diagram. The Backbone connector provides the
connection between the Power Board on the CubeSat and the rest of the boards. The
connector provides the C&DH board with a voltage between 6 to 9 volts depending on how
much charge is in the batteries; the C&DH board regulates this voltage down to the required
3.3 volts.
5
Figure 2.1: Communication Diagram for C&DH board
6
Figure 2.2: Power Diagram
7
2.2 Individual Block Descriptions
2.2.1
USB to UART
INPUTS: The incoming inputs will be from the MittySOM module board, as well as a RE
and R lines that comes from the ADM3488 chip. The pins for these are the ones
corresponding to each USB’s D-, D+, and VBUS pins. For the MittySOM module, this
corresponds to pins 115, 131, and 133 for USB_0, and pins 119, 121, and 123 for USB_1.
These connect to pins 16, 15, and 4 respectively for the FT232RL USB to UART chip. The R
line is from the ADM3488 chip’s pin 1, and connects to the FT232RL pin 5.
OUTPUTS: The output of the FT232RL chip includes one signal wire for the ADM3488
chip. This wire is the TXD line, which corresponds to pin number 1.
DESCRIPTION: This block provides the necessary conversion between the USB to the
UART outputs needed for the ADM3488 chip. The IC requires an input voltage somewhere
between 3 to 3.6 volts, but ideally 3.3V. The provided power from the power circuitry of the
CubeSat will provide 3.3V, so this fills the requirements of the IC. The max supply current is
also fairly low (only around 26 milliamps as seen from the chart listed below), so overall this
IC does not draw much power.
2.2.2
TTL to RS485
Attached in the Appendix Pages is the chart listing the pins and their associated functionality
for this chip (figure 3). This figure was taken from the Analog Devices website.
INPUTS: The Analog Devices ADM3483 (half duplex) has 5 inputs, 2 of which that are
bidirectional. The A and B pins on the ADM3483 are bidirectional and connect to the
TX/RX+ and TX/RX- pins on the backbone connector, receiving information from other
boards in the tower.
OUTPUTS: There are 3 outputs in addition to the inputs. Again A and B are bidirectional
and connect to the TX/RX+ and - pins on the backbone connector. The final output is the DI
which goes to the processor RX.
DESCRIPTION: The ADM3483 provides appropriate conversion from UART to RS485.
The transceiver operates very similar to ADM3488 except that it is required to operate in half
duplex versus full duplex. This is required because the backbone connections that the
ADM3483 connects to are simultaneous TX and RX and therefore need half duplex. Like the
ADM3488 the transceiver has an impedance matched resistor between A and B but unlike
the ADM3488 the transceiver also has a pull-up resistor on pin A and a pull down resistor on
pin B.
8
2.2.3
TTL to RS422
Attached in the Appendix Pages is the chart listing the pins and their associated functionality
for this chip (figure 3). This figure was taken from the Analog Devices website.
INPUTS: The ADM3488 (Full Duplex) is a fairly straightforward IC. It accepts 1 input from
the CP2101: a DI line. The DI is the UART transmission output from the CP2101 chip,
which is pin 26 on the CP2101, and that connects to the ADM3488’s pin 3. DE connects to
pin 3 on the ADM3488 IC. Other inputs include VCC (pin 1), which can range from 3 to 3.6
volts (for the purposes of this project it is 3.3 volts), and GND (pin 4) which is tied to a
common ground. Two other inputs come from the attached peripherals Hirose DF11
connector (described in section 2.2.3); these lines come into the A and B inputs of the
ADM3488 (pins 8 and 7 respectively).
OUTPUTS: There is one output that goes back to the CP2101 chip, and that is the R0 line
(pin 2). There are also two other output lines, which are Driver Output Non-inverting and
Driver Output Inverting (Y and Z on the diagram shown below respectively). These are
located on pins 5 and 6, and go to the peripheral connectors (which are the Hirose DF11
connectors described in the Peripheral Connectors section of this technical document).
DESCRIPTION: This block provides the necessary conversion from the incoming UART
signal to the RS422 signal required by the payload peripherals. It implements this by using a
single IC called the ADM3488. This should be all the necessary components to do the
conversion and allow for full duplex communication between the MitySOM module and the
connecting peripherals that use this circuitry (those peripherals include the two payloads, a
Future Expansions peripheral, and the Cadet Radio).
2.2.4
NAND Flash
INPUTS: The NAND flash chip has incoming connections from the MitySOM Module.
These connections are the SPI_0 pins (SPISCLK, SPI0DI, SPI0CS0), which allows the user
to easily write to the 1 GB flash memory through SPI protocol.
OUTPUTS: Outputs will be just the one SPI0DO connection, which has the accessed data
memory. This connects back to the MitySOM module allowing easy reading from memory.
DESCRIPTION: The NAND flash circuitry objective is meant to emulate the same
capabilities that an SD card. NAND flash is better suited to hold gathered data versus NOR
flash, a comparable product. Used in place of an SD card, the user need only use SPI protocol
to simply read and write to and from the memory. Currently, this portion of the circuit is still
under design review by the IlliniSat team, so the specifics of what this will be used for are a
little unclear but may be used to hold the data gathered by the peripherals.
9
2.2.5
Power Circuitry
The incoming power for the C&DH board is through the Backbone connector. As currently
designed, one port on the Backbone connector will provide the C&DH board with 3.3 volts
plus or minus 0.033V and 2 amps. Since all of the IC’s chosen for the other circuitry run off
of 3.3 volts, this should be plenty for our purposes. The 2 amps should also be more than
enough because our design is meant to run at a maximum current draw of around 700
milliamps.
The current design uses the topmost trace layer of the four that is allowed for the C&DH
board to route all of the power to the correct locations. In this case that means routing the
power to each block listed above; all of these blocks require the same VCC input between 3.0
and 3.6 volts, so the top layer will mainly comprise of taking the 3.3 volts from pin M1
(labeled 3V3_CNDH; see attached data sheet) and routing this power throughout the C&DH
board to the VCC inputs of each of the blocks.
Right now the Backbone Connector does not provide the C&DH board with access to the two
Lithium Ion batteries that are powering the rest of the CubeSat. Most likely there will need to
be a way to access that voltage since some components on the C&DH board will require a
regulated 5 volts. This is currently being requested of the Power Systems group for the
CubeSat team.
10
2.3 Connector Descriptions
2.3.1
Hirose DF11_6DP_2DS Connector
Attached in the Appendix section is a sketch of what this connector looks like (figure 5). This
page was taken from the DigiKey website, which had an attached pdf for the part with the
outlines drawn.
The connector has three inputs coming to it from the C&DH board. These wires include the
RS422 output lines (Y and Z on the diagram) as well as a power line. The connector has 2
output lines that go back to the transceiver block on the C&DH board; these are the receiver
side input lines (A and B). This is the type of connector that the RS422 Payload, Future
Expansions, and Cadet Radio peripherals connects with and allows the communication
between the external sensors and the C&DH board.
The connector is a simple straight pin header that the peripherals will snap into. The socket is
notched in such a way that it will prevent reverse wiring and damaging the circuitry. See the
attached diagram below to see what the connector looks like. Each connector will have four
incoming RS422/RS485 wires for the full duplex signals (the inverting and non-inverting that
is outputted by the ADM3488, see above section for description of the ADM3488), as well as
a power and ground connection. One of the six pins is unconnected and not needed for the
purposes of this project.
2.3.2
Backbone Connector
The Samtec ERF8-030-05.0-L-DV-TR Backbone Connector is the connection piece that will
join the C&DH board with the Power Board below and the Payload Expansion board above.
This connector currently has the following pins shown in Figure 6 listed in the Appendix;
however this connector is currently undergoing a new design so this chart is most likely out
of date (a more recent one was not provided to the C&DH team at the time of this writing).
The pins that are important for the C&DH board are the 3.3 volt and the Peripheral RS485
positive and negative pins. The Backbone connector also provides the connections for the
Hardware Bus UART circuitry; however at this time those details have not been provided to
the C&DH team, so the specific pin layouts are not currently readily available. There also is a
need for pins that provide power via the two Lithium Ion batteries that the C&DH board will
then regulate down to 5 volts.
The rest of these pins will be ignored by the C&DH board and passed on through via the
connector on the other side of the C&DH board. These signals include the Debug Ports and
the Expansion Board RS422 communications. A list of the pins on the connector at the time
of this writing is located in the Appendix pages (Figure 6).
11
2.3.3
MitySOM Module Connector
The C&DH board utilizes a JAE MM80-204B1-1 SODIMM Connector for connecting the
MitySOM module and the C&DH board. This connector breaks out all of the pins of the
MitySOM processor itself; it has 204 pins, which are labeled and shown in figure blah below.
The main ones that the C&DH team needs to focus on is the UART and USB connections, as
well as the VCC and GND pins. However, most of these pins are not needed for the purposes
of this project.
This connector comes in two sizes: 5.2 mm and 9.2 mm. In order to meet the height
constraints set on the C&DH board as well as the connected MitySOM Module board, it is
necessary to use the 5.2 mm height for the connector.
12
2.4 Reserved Circuit Descriptions
2.4.1
UART_0
This UART port will be used for general debugging purposes. The reserved UART circuit is
the connections that lead to UART_0 on the MitySOM module. The pins are traced out to a
simple four pin male connector that the user can plug a UART compatible device and then
attempt to do any necessary form of debugging that is required (one example could be
echoing bytes back and forth between the user and the MitySOM module).
2.4.2
SPI_0, I2C_1
These two are a reserved connection that can be used for future expansion of a memory
blocks. Currently, the memory will either be a set of NOR memory or EEPROM, but this has
not been finalized yet. SPI_1 and I2C_1 will be traced out in a similar fashion as UART_0,
except that rather than tracing them out to pins that can be plugged into, the traces will end at
soldering holes on the board itself. The rest of this circuit will be designed at a later time and
added to this design review when the larger CubeSat team agrees on what will be connected
at that location.
13
2.5 Schematics
Schematic 1: NAND Flash Memory MT29F4G01AAADD
Schematic 2: USB to UART FT230
14
Schematic 3: TTL to RS422 ADM3488
Schematic 4: TTL to RS485 ADM3483
15
Schematic 5: Power to Board Schematic G9333, Backbone Connector, REG1117, SO-DIMM
Connector
16
3. REQUIREMENTS AND VERIFICATION
3.1 Requirements Summary
Since the C&DH board is not easily broken down into separate modules, writing a set of
Requirements and Verification steps for individual modules of the project did not seem very
reasonable. The Requirements can be broken down into different categories that the board
must pass in order to be fully operational for the IlliniSat team. These categories are Space
Requirements, Board Dimension Requirements, Communication Requirements, and Power
Requirements.
Outer Space: These refer to any requirement that must be met such that the board does not
fail due to the extreme conditions of space. These requirements include using whiskering
resistant solder, fabrication using outgassing resistant materials, efficient conduction of heat
away from the board, and shake resistance.
Board Dimensions: These requirements refer to the shape of the board, as well as the
placement of the external connectors. These are found directly on the mechanical drawing of
the C&DH board1.
MitySOM Module Keep-out Areas: The MitySOM Module when mounted to the
SODIMM connector comes with recommended keep-out areas on both the top side and the
bottom side of the board. Therefore the design of this board requires that these keep-out
zones are respected.
Communications: These requirements refer to all communications that take place on the
board. Included in this category is the testing of all communication types (examples are
UART, USB, and SPI) and protocol conversion chips (TTL to RS422/RS485 level
conversions and USB to UART bridges).
Power: These refer to all power related requirements that this board must provide. This
board has to draw at most 700 milliamps, with a voltage input between 6 to 9 volts.
1
See figure 2 in Appendix A
17
3.2 Verification Summary
Outer Space: The majority of the space requirements can be verified by placing the
fabricated board into a vacuum chamber and seeing how various components behave. Such
changes that need to be monitored include temperature across the ICs as well as making sure
the solder and traces do not succumb to outgassing effects.
Board Dimensions: Verification of these design requirements requires the use of precise and
highly accurate measuring tools to make sure the dimensions are correct. A final verification
step is to connect the C&DH board in with all of the rest of the backbone boards and see if it
fits within the constraints of the satellite.
MitySOM Module Keep-out Areas: This comes directly from the design guide that Critical
Links (the manufacturer of the board) provides for the connecting MitySOM Development
board. These Keep-outs refer to the space above and underneath the MitySOM Module
board. Precise measurements must be made to verify that these constraints are met.
Communications: This will involve writing two scripts that communicate between the
MitySOM Module and a computer through the UARTs, USBs, and SPI connections. Once
these are verified and communication with the MitySOM is working, the scripts will be run
once more, only through the transceiver chips (ADM3483 and ADM3488) and the USB to
UART bridge chips (FT230).
Power: Verification of this will involve measuring voltages and currents through the circuit.
The main constraint is the circuit can draw at a maximum 700 milliamps.
18
3.3 Outer Space
Requirements
1. Solder that is solder whiskering resistant2
Verification
1. Verify no solder whiskering can occur
a. Place board in a vacuum chamber
b. Leave the board in for 24 hours
c. Inspect board the next day
d. Passes inspection if no shorts occurred
i. Take a voltmeter
ii. Set it to connectivity test
iii. Check each trace that is near to
each other for connectivity; should not
be any of them
2. Board must not outgas3
2. Verify that board cannot outgas in space
a. Place board in a vacuum chamber
b. Leave the board in for 24 hours
c. Inspect board the next day, checking for
outgassing issues (pockmarks in the traces,
PCB itself, or the solder joints)
3. Board must conduct heat efficiently through 3. Verify that the board is conducting heat
the attachment screws
a. Place board in vacuum chamber
b. Provide power to the board
c. Verify the regulators do not overheat
d. Run test scripts (see Communications
section) and measure the heat of the IC’s
e. Verify that none of the components are
overheating while communicating
4. MitySOM Module connection must be shake 4. Verify that under extreme vibration,
resistant
MitySOM module stays connected to the
C&DH board
a. Place the board on a shaker table
b. Run the shaker test for 10 minutes
c. Vary the severity of the vibration, and
repeat step b
d. Verify that the circuit still works by
running Test Script C (see Appendix B for
description of the scripts, code not
available)
5. Board must be conformal coated
5. Verification of the conformal coat will
follow similar steps as requirement 1 listed in
this table since its main purpose is to prevent
2
3
See figure 9 in Appendix A that shows a picture of solder whiskering.
See figure 10 in Appendix A that shows a picture of outgassing
19
solder whiskering. A picture of this
phenomenon is in Appendix A
3.4 Board Dimensions
Requirements
1. Height less than 8 mm but greater than 5
mm
Verification
1. Verify that the board fits within those limits
a. Connect the MitySOM Module to the
C&DH board
b. Take calipers
c. Measure the height from top of
MitySOM Module to bottom of C&DH
board; should be between 5 and 8 mm
d. As a further test, assemble the C&DH
board with boards that are on top and on
bottom and make sure the boards connects
together
2. 90x90 mm board dimensions
2. Verify that the board width and length are
both 90 mm by measuring the fabricated board
a. Acquire the fabricated board
b. Measure the width of the board with
calipers; should be 90 mm ± 0.01 mm
c. Measure the length of the board with
calipers; should be 90 mm ± 0.01 mm
3. Verify that the cutout is 70x8 mm by
measuring the fabricated board
a. Acquire the fabricated board
b. Measure the length with calipers; should
be 70 mm ± 0.01 mm
c. Measure the width with calipers; should
be 8 mm ± 0.01 mm
4. Verify the top screw center hole locations
are in the correct location by measuring the
center holes on the fabricated board
a. Acquire fabricated board
b. measure the center hole top/down
location; should be within 0.01 mm of 5.5
mm
c. Measure the center hole right/left
location; should be within 0.01 mm of 5.0
mm
5. Verify that the Backbone Connector is in the
right location by measuring the center location
3. Cutout on one side is 70x8 mm
4. Screw center hole locations are 5.5x5.04 mm
± 0.01 mm on the board
5. Backbone Connector center location should
be 33mmx11mm5 ±0.01 mm for each
4
See Figure 2 in Appendix A; 5.5 refers to the up/down position on the drawing, 5.0 refers to the left/right
position on the Top View drawing
20
dimension
6. Hirose DF11 Connectors are between two
marks labeled6
a. Acquire fabricated board
b. Measure the center point top/down
location; should be 11 mm ± 0.01 mm
c. Measure the right/left position of the
center point; should be 33 mm ± 0.01 mm
6. Verify that they are between the marks on
the fabricated board
a. Acquire fabricated board
b. Measure to make sure the outermost
connectors are not within 12 mm of the
edges of the board
c. Measure to make sure the connectors
are within 9.70 mm ± 0.01 mm of the
bottom edge of the board (as viewed from
the top)
3.5 MitySOM Module Keep-Out Areas
Requirements
1. Recommended that there is at least 2 mm of
space between the bottom of the MitySOM
module board and anything beneath it
2. Recommended that there is at least 3mm of
Keep-out above the MitySOM Module
Verification
1. Verify bottom Keep-out is met by measuring
the highest point on the C&DH board to the
MitySOM Module7
a. Obtain the fabricated board
b. Use calipers to measure the height
between the MitySOM Module and the
C&DH board
c. Height should be no more than 2mm,
preferably less than 2 mm
1. Verify the top Keep-out is met by measuring
from the MitySOM Module to the board above
a. Obtain the fabricated Board
b. Connect the C&DH board with the
Expansion board above it
c. Measure the height from the tallest point
on the MitySOM Module to the lowest
point on the Expansion board above
d. There should be at least 3mm of space,
preferably more
5
See Figure 2 in Appendix A; 33mm refers to right/left positioning, 11mm refers to the top/down
positioning with respect to the Top View
6
Marks are on the top view of the Mechanical Drawing in Appendix A (see note A on the drawing)
7
Note: Based on Figure 2 and Figure 7 (Appendix A), an IC that sits underneath the MitySOM Module
should be no more than 0.8 mm. Therefore extreme care must be taken for designing the board since only
the smallest of IC’s can go underneath the MitySOM module.
21
3.6 Communications
Requirements
Verification
1. Can communicate to the MitySOM via USB 1. Verify USB Communications are working
by running Test Script A
a. Obtain the fabricated board
b. Power on the board
c. Boot up the MitySOM module
d. Boot up a computer
e. Connect the Computer to the USB port
on the MitySOM by using a USB to
USB cable
f. Run Test Script A9
2. USB to UART bridge communication works 2. Verify USB to UART conversion works by
running Test Script A
a. Obtain the fabricated board
b. Power on the board
c. Boot up the MitySOM module
d. Boot up a computer
e. Connect the computer by using a USB
to UART connector
f. Run Test Script A8
3. TTL to RS422/RS485 conversion works
3. Verify TTL to RS422/RS485 Level
Conversion works by running Test Script A
a. Obtain the fabricated board
b. Power on the board
c. Boot up the MitySOM module
d. Boot up a computer
e. Connect the computer by using a USB
to RS422 /RS485 connector
f. Run Test Script A9
4. UART communication to the MitySOM
works
4. Verify UART communications to the
MitySOM works by running Test Script A
a. Obtain the fabricated board
b. Power on the board
c. Boot up the MitySOM module
d. Boot up a computer
e. Connect the computer by using a USB
to UART connector
f. Run Test Script A9
5. SPI Communication to the MitySOM works 5. Verify SPI works for communicating to the
8
See Appendix B for description, code not available
22
MitySOM by sending data via Test Script A
a. Obtain the fabricated board
b. Power on the board
c. Boot up the MitySOM module
d. Boot up a computer
e. Connect the computer using a USB to
SPI connector
f. Run Test Script A9
6. NAND Flash Communication works
9
6. Verify that the MitySOM can communicate
with the NAND Flash by writing data and
then readin data
a. Obtain the fabricated board
b. Power on the board
c. Boot up the MitySOM module
d. Boot up a computer
e. Connect the computer to MitySOM
UART_0 via a USB to UART connector
f. Run Test Script B10 on the MitySOM
to verify that the NAND Flash is
working
See Appendix B for description, code not available
23
3.7 Power
Requirements
1. Backbone Connector provides 3.3 ± 0.1
volts
2. Backbone Connector provides 6.3 to 9.6 ±
0.5 volts10
3. Voltage Regulator AP2112 provides 3.3 ±
0.1 volts
Verification
1. Verify the voltage coming in is 3.3 volts ±
0.1 using a voltmeter
a. Acquire the fabricated board
b. Acquire a power supply
c. Connect the positive end of the power
supply to the 6.3-9.6 volts pin on the
Backbone Connector
d. Connect the negative end of the power
supply to the GND pin on the Backbone
Connector
e. Measure the voltage between the GND
pin and the 3.3 volt pin; should be within
0.1 volts of 3.3 volts
2. Verify the voltage coming in is 6.3 volts ±
0.5 using a voltmeter
a. Acquire the fabricated board
b. Acquire the Power board
d. Connect the Power Board to the C&DH
board via the Backbone Connector
e. Measure the voltage between the GND
pin and the 6.3 to 9.6 volt pin; should be
within 0.5 volts of 6.3 to 9.6 volts
3. Verify the voltage coming out of regulator is
3.3 volts ± 0.1 using a voltmeter
a. Acquire the fabricated board
b. Acquire a power supply
c. Connect the positive end of the power
supply to the 6.3-9.6 volts pin on the
Backbone Connector
d. Connect the negative end of the power
supply to the GND pin on the Backbone
Connector
e. Measure the voltage between GND on
the Backbone Connector and the VOUT
on the regulator; voltage should be within
0.1 volts of 3.3 volts
10
Ranges vary depending on the charge of the batteries. When fully charged, should be around 9.6 to 10.2
volts; when starting to become depleted, the voltage should be around 5.8 to 6.3 volts
24
4. Current draw is at most 700 milliamps
11
4. Verify the current draw by using a power
generator, setting it to 7.5 volts, and measuring
the current draw
a. Acquire the fabricated board
b. Acquire a power generator (something
like a signal generator or any power
supply in the lab will do)
c. Plug in the positive terminal of the
power supply to the 6.3-9.6 volt pin
location for the Backbone connector
d. Plug in the negative terminal to the
GND pin on the Backbone Connector
e. Turn on the power generator; measure
the current draw. Should be less than 700
milliamps
f. Run Test Scripts C11, and measure the
current draw; should be less than 700
milliamps
See Appendix B for description, code not available
25
3.8 Possible Simulation
Since the C&DH board is not manufactured yet, data for the simulation described below
could not be obtained. However, the following estimates are based on datasheets and
knowledge of how memory operates.
One possible way to test the USB to UART module is to run a simple Python-based script on
a Linux-based computer which transmits a byte of random data through the USB port to the
UART input on the C&DH board. Another program running on the C&DH board then reads
this data and stores it in a .txt files with a timestamp. A byte of random data is transmitted
every second over the course of 24 hours and at the end of the 24 hour period, some simple
data analysis can be done to check how many bytes were received by the C&DH board and
how many of those received bytes actually match the transmitted ones. According to the
datasheet for the USB to UART converter, the chip can support baud rates in the range 183.1
baud to 3,000,000 baud. Depending on the rate at which data is stored in the NAND memory
limits the rate at which data can be transmitted from USB to UART. A valid conclusion
would be that as the baud rate increases, it will become more and more difficult for the
NAND memory to keep up with the baud rate, hence it may result in more transmission
errors as opposed to when using lower baud rates. These transmission error rates would range
from 3-10%, based on previously conducted tests by other users of similar ICs.
26
3.9 Tolerance Analysis
Even though the documentation states that the MitySOM-335x processor does not have any
specific requirements regarding thermal management, it recommends users do testing in the
final enclosure and in the environment where the board will be used. The group believes the
processor might have thermal management issues in outer space because it is a completely
different environment than the board was built to operate in. The following is a rough
thermal tolerance analysis of the processor board.
According to processor specifications, it must operate within the 0°C and 70°C range. The
average temperature on the inside of an operational CubeSat is approximately 9±19°C12. The
2°C variation is small enough that the components inside the satellite will not notice massive
changes in temperature, hence hindering its operational ability, yet big enough to encompass
any major temperature swings that may be caused due to processor overload and other
conditions. To keep the processor operational in outer space, it must conduct all its heat
towards the screws that will keep the board in place during liftoff. These screws will serve as
heat sinks and will conduct extraneous heat away from the board. In order to test this, the
group must simulate these temperatures to find the right level of heat transfer for the board.
Since the limiting factor to conducting the heat will be the traces through the board, we will
do the analysis on those to find the correct level of heat transfer. One can represent the heat
transfer via conduction using the standard equation:
q=
κ∗A∗T
𝑠
, where
q → heat transfer
A → heat transfer area
κ → thermal conductivity of the material
ΔT → temperature difference across the material
s → material thickness (average length of trace to the heat sink)
The width and height of the traces to the heat sinks from the processor board are 10mil and 2
mil respectively. Therefore, the heat transfer area A = wh = 20mil = 0.000508m
κ for copper (material for trace) is 398 W/m/°C
ΔT = max processor operational temperature - average ambient temperature = 70 - 9(±19) =
61±19°C
s = 10in = 0.254m
q=
398∗0.000508∗(61±19)
0.254
12
= 48.556±15.124 Watts
http://digitalcommons.calpoly.edu/cgi/viewcontent.cgi?article=1054&context=aerosp
27
At one extreme, say if there is a leakage in the satellite enclosure and the processor board is
exposed to the external temperature, the processor will fail to functional as the average
temperature of outer space (~ -100°C) is much less than that of the operational temperature
of the processor. On the other extreme, if the processor heats up too much, it should still be
functional because it conducts an adequate amount of heat to the screws to keep itself
functional.
28
4. COST ANALYSIS
4.1 Labor
Name
Hourly
Rate
Total Hours Invested Total = Hourly Rate x 2.5 x Total
Hours Invested
Mark Mahowald
$40.00
150
$15,000
Daniel Brackmann
$40.00
150
$15,000
Anuj Pasricha
$40.00
150
$15,000
Total
$120
450
$45,000
4.2 Parts
Item
Quantity
Cost ($)
Passive Devices (Capacitors, Resistors etc.)
100
50
MitySOM335x
1
153.00
JAE MM80-204B1-1 (SO-DIMM connector)
1
6.89
TI Reg 1117 (voltage regulator)
1
0.88
TI Reg G933
1
2.50
AMD3488 (Transceiver)
6
20.10
AMD3483 (Transceiver)
1
1.25
Hirose DF11_6DP_2DS Connector
4
12.56
FT232RL (USB to UART)
2
9.76
USB to RS422 Cable
1
57.74
29
MCP2210 (USB to SPI)
1
2.10
Total
---
316.78
4.3 Grand Total
Section
Total
Labor
$45,000
Parts
$256.94
Total
$45,316.78
4.4 Schedule
Week
10/5
Mark
Make necessary IC’s
in Cadence
Dan
Learn Cadence, start
board layout
10/1213
Finish board layout
Start and finish
routing
10/1914
If board design is
completed, submit
board design for
review with
supervisor; else finish
board layout
Finish off issues
revealed from design
review with
supervisor, Send board
If board design is
completed, fix design
flaws based on review
with supervisor; else
finish routing
10/27
13
14
Work on individual
progress report, Finish
off issues revealed
from design review
Anuj
Order parts; learn how
to configure
MitySOM; if time
permits, begin writing
test scripts
Continue writing
scripts if not finished,
begin prototyping
demo circuit if parts
are in
Begin testing, report
any bugs found with
wiring
Work on individual
report, continue
testing
Mark gone Oct 13th, 14th, and 17th
Dan gone Oct 17th to the 22nd
30
11/3
for fabrication, work
on individual progress
report
If board in, begin
power testing; else
review power testing
procedures
11/1015
finish power testing
11/17
Begin Demo plan
11/24
12/1
Thanksgiving break
Finish Demo plan
12/8
Present
15
with supervisor
If board in, begin
board dimensions and
space testing; else
review board
dimensions testing
and space testing
procedures
finish space testing
Begin working on
presentation slides
Thanksgiving break
Finish presentation
slides
Present
If board in, begin
communication
testing; else review
communication testing
procedures
finish communication
testing
Start final report
Thanksgiving break
Begin polishing the
final report
Present
Mark gone November 13th-16th
31
5. ETHICS AND SAFETY
5.1 Ethics
Despite the fact that the C&DH board will be operating in outer space and that there may not
be any direct ethical considerations in relation to human use, certain aspects of the IEEE
Code of Ethics must still be taken into account during the design process.
The following points from the IEEE Code of Ethics apply to this project:
Certain calculations in this paper may seem somewhat hand-wavy. However, for future
versions of the document, these calculations will be made more concrete as better and more
precise data is collected based on actually testing the board. As a result, more realistic and
honest claims about how the circuit board behaves will be made possible, as cited in point 3
of the IEEE Code of Ethics:
1. to be honest and realistic in stating claims or estimates based on available data;
Given that the C&DH board will be operating in outer space, the team must learn how
materials and electronics behave in outer space. Outer space, unlike the Earth’s environment,
presents a lot more technical challenges that need to be overcome (some of which are stated
in the Requirements & Verification section). Over the span of this project, team members
will gain an understanding on technology from a different perspective, in accordance with
point 5 of the IEEE Code of Ethics:
5. to improve the understanding of technology; its appropriate application, and potential
consequences;
As a continuation of the previous point, team members will learn how to design a circuit
board from scratch, especially one that takes an incredible amount of precision. The stakes of
failing being very high in outer space force team members to adapt new skills very quickly
and understand the implications of their work on other modules on board the satellite. Team
members will thus gain immense technical competence over the course of the design process,
as is codified by point 6 in the IEEE Code of Ethics.
6. to maintain and improve our technical competence and to undertake technological
tasks for others only if qualified by training or experience, or after full disclosure of
pertinent limitations;
While working on the project, we need to ensure that our work environment fosters
professionalism, as required in engineering projects - this includes being open to new ideas,
32
acknowledging one’s own mistakes, assisting peers with their parts of the project, accepting
and giving criticism in a healthy manner. Moreover, proper credit must be given to whose
work we borrow from. These points are cited in the 7th code of the IEEE Code of Ethics.
7. to seek, accept, and offer honest criticism of technical work, to acknowledge and
correct errors, and to credit properly the contributions of others;
Knowing that the project is based in a multidisciplinary setting, which includes teams from
various backgrounds, cultural and academic, respect must be given to all team members and
honesty and fairness should be of utmost importance. Tying in with the previous code,
individuals must not be taken undue advantage of, which will be in direct violation of code 8.
8. to treat fairly all persons and to not engage in acts of discrimination based on race,
religion, gender, disability, age, national origin, sexual orientation, gender identity, or
gender expression;
Team members will do their best to abide by the IEEE Code of Ethics, especially bearing in
mind the particular points stated above.
33
5.2 Safety
There are not that many inherent safety concerns while designing the PCB on the Cadence
software. However, after the 4-layer board is professionally manufactured, specific port
connections on the board will need to be tested. In doing so, it is possible accidentally supply
a voltage above the port’s threshold. Care will have to be taken when hooking power supplies
to the testing apparatus.
34
6. APPENDICES
APPENDIX A: Supplementary Diagrams
Figure 1: Picture of the boards in the CubeSat, with the locations marked. This diagram was taken from
the IlliniSat C&DH Carrlier Board Document.
35
Figure 2: Layout of the C&DH Board with specifics noted. Important things to note are the location of
the Backbone Connector, location of the Hirose DF11 connectors, and the shape of the board. This
diagram was provided to us by the IlliniSat team.
36
Figure 3: ADM348x Pin layout. In our design there are two different chips being used, the 3488 and the
3483. The difference between the 3488 and the 3483 is the 3488 is full duplex communication (can both
receive and transmit at the same time), whereas the 3483 is only half duplex (can only transmit or
receive one at a time). This table was taken from the ADM348x data sheet found at Analog Devices
website.
37
Figure 4: General high level block diagram of the flow of the signal circuitry. Carrier Board represents
the C&DH board; Backbone Connector signifies that the Power Board and the Bus Hardware
communication will go through the Backbone Connector and not through a Hirose DF11 connector. This
diagram was taken from the IlliniSat C&DH Board document.
38
Figure 5: Hirose DF11 connector with dimensions labeled. Important things to note are the notches that
prevent reverse wiring, thus protecting the peripherals. This diagram was taken from the digikey
website.
39
Figure 6: This is the list of Pins and their corresponding functionality for the Backbone Connector. For
our purposes, we will need to request two new pins to access the 6 to 9 volt Lithium Ion batteries. This
table was taken from the IlliniSat C&DH Design document.
40
Figure 7: Diagram outlining the Keep-out areas for the MitySOM Module. Note that the connector
shown is not the one is used; a smaller height (5.2 mm) connector is used instead.
Figure 8: Diagram of how the MitySOM Module will be secured to the C&DH board. Note that the socket
connector used is not 9.2 mm high; instead it is 5.2 mm.
41
Figure 9: This is what tin whiskering looks like. This is a problem because it shorts circuits if one is not
careful. A way to prevent this is to use conformal coating, which coats all of the circuit in a coat of
Parylene. This helps prevent the effects of solder whiskering.
Figure 10: This is what an outgassed circuit looks like. This outgassing occurs in space because tiny
molecules that managed to implant themselves in the circuit start to bubble out of the circuit due to the
extreme conditions of space.
42
APPENDIX B: Explanation of Test Scripts
There will be two scripts that are implemented in order to verify that the communication from
peripherals to the MitySOM Module is working correctly. These scripts shall be referred to as
Test Script A and Test Script B.
Test Script A: use for all communication tests except for the NAND Flash. That test will be
done via an entirely separate script known as Test Script B. The flow diagram for Test Script A
shows the logic behind it. The basic concept is to use a USB port on a computer and send data
through that port to the MitySOM Module, have the MitySOM Module echo that data back, and
verify that it is the same data that was sent initially. This logic can be used for the USB, UART,
and the RS422/RS485 transceivers. In theory, the only thing that changes is the type of converter
that the computer uses to send the data. For example, testing the UART will require a small USB
to UART adapter.
Test Script B: use for testing the NAND Flash circuitry. This script will be run on the MitySOM
module itself, and its flow diagram is provided below. The idea with this script is it first writes
data to the NAND Flash circuitry, then reads from that same location. After it accomplishes this,
it verifies that the initial and final data is the same as the one that was initially sent.
Test Script C: use for full functional test of the C&DH board. This will run through reading
from attached peripherals, storing the data in the NAND Flash, and then reading the data from
the NAND Flash. If the board passes this scripts test, then the full functionality of the
communication layer of the board is fully functional.
43
7. CITATIONS
ADM3483_3485_3488_3490_3491, Rev. E, Analog Devices, Norwood, MA, 2011 [Online].
Available: http://www.analog.com/static/importedfiles/data_sheets/ADM3483_3485_3488_3490_3491.pdf
Basic Information Regarding Tin Whiskering, NASA, 2009. [Online].
Available: http://nepp.nasa.gov/Whisker/background/index.htm
C&DH Board Mechanical Layout, A. Ghosh, K. Basset, IL 2011.
DDR SDRAM SODIMM Connector MM80 Series, JAE PMK Div., 2010. [Online].
Available: http://jae-connector.com/en/pdf/MB-0213-1E_MM80.pdf
FTDI FT2232H (USB < - > UART) baud rates, Electrical Engineering Stack Exchange.
[Online]. Available: http://electronics.stackexchange.com/questions/958/ftdi-ft2232h-usbuart-baud-rates
HRS Drawing for Reference, M. Matsud, Hirose Electronic Co. [Online]. Available:
http://www.hirose.co.jp/cataloge_hp/2d/EDC3-020834-02.pdf
IlliniSat C&DH Carrier Board Document, Wang, Shimeng, IL 2014.
MitySOM-335x Carrier Board Design Guide, Rev. 1.7, MitySOM. [Online].
Available: http://www.criticallink.com/wp-content/uploads/MitySOM-335x-Carrier-BoardDesign-Guide.pdf
Parylene and Tin Whiskering, Diamond-MT. [Online].
Available: http://www.paryleneconformalcoating.com/parylene-and-tin-whiskers
QSE-XXX-01-X-D-XX-FOOTPRINT, Rev. N, Samtec, New Albany, IN, 2013. [Online].
Available: http://www.samtec.com/documents/webfiles/cpdf/QSE-XXX-01-X-D-XXFOOTPRINT.pdf
Wave Soldering Defects, epec, 2014. [Online].
Available: http://www.epectec.com/pcb/defects/sunken_joints.html
Thermal Analysis of the CubeSat CP3 Satellite, Friedel, McKibbon, California Polytechnic
State Univeristy, 2011. [Online]. Available: http://www.hirose.co.jp/cataloge_hp/2d/EDC3020834-02.pdf
44