Download REVIEW FOR ELEC 105 MIDTERM EXAM #1 (FALL 2001)

ELEC 350
Electronics I
Fall 2012
Review Topics for Exam #1
The following is a list of topics that could appear in one form or another on the exam. Not all of
these topics will be covered, and it is possible that an exam problem could cover a detail not
specifically listed here. However, this list has been made as comprehensive as possible.
General amplifier concepts
- “analog” vs. “digital” electronics
- linear vs. nonlinear regions of operation
- Thévenin and Norton equivalent circuit representations of input and output ports
- concept of a signal; voltage and current signals
- concept of a circuit “port” (pair of terminals)
- input and output resistances of amplifiers, sources, and loads
- distinguishing characteristics of “good” voltage amplifiers (very high input resistance
and very low output resistance)
Operational amplifiers
- ideal op-amp characteristics
o infinite open-loop gain
o infinite input resistance between input terminals
o zero output resistance
o zero current flow into the inverting and noninverting inputs
- closed-loop voltage gain vs. open-loop voltage gain
- virtual short if neg. feedback is present and op-amp operates in linear region
- non-ideal characteristics
o finite open-loop gain, non-zero voltage across op-amp’s input terminals
o finite input resistance between input terminals
o non-zero output resistance
- op-amp equivalent circuit model (for both ideal and non-ideal cases)
- output voltage limited by power supply voltages (clipping)
- output voltage limited if maximum output current is exceeded
- lack of virtual short when clipping occurs or output current limit is exceeded
- inverting amplifier
- noninverting amplifier; voltage follower
- effects of negative feedback
o causes output impedance of amplifier circuit to be far less than Rout
o causes input impedance of op-amp to be far greater than Rin
o effect of RL (load resistance) on input resistance is minimized, but not zero
o effect of Rg (source resistance) on output resistance is minimized, but not zero
Difference amplifier
- has “floating” inputs
- differential (balanced) vs. single-ended (unbalanced) input/output ports
- purpose/advantage of differential amplifier
- differential-mode vs. common-mode signals
v v
v Id  v2  v1
and
v Icm  2 1 ,
2
where vId = differential-mode input voltage; vIcm = common-mode input voltage
1 of 3
-
-
decomposition of single-ended input voltages (v1 and v2) into differential and
common-mode voltages
and
v1  v Icm  0.5v Id
v2  v Icm  0.5v Id
total output voltage

R  R4  R2 
R  R4
R 
1 
   v Id  1  2 
vo  1  2 
 2  v Icm
2 
R1  R3  R4  R1 
R1  R3  R4 R1 

R2  R4  R2 
R4  R2 R3 
1 
   v Id 

1 
v Icm (alternative)
1 
2 
R1  R3  R4  R1 
R3  R4 
R1 R4 
- differential-mode gain vs. common-mode gain
v
R  R4  R2 
1 
 
Ad  od  1  2 
v Id 2 
R1  R3  R4  R1 
 R  R4
v
R
R4  R2 R3 
1 

Acm  ocm  1  2 
 2 
v Icm 
R1  R3  R4 R1 R3  R4 
R1 R4 
- input resistance between ports (differential-mode)
- common mode rejection ratio (CMRR)
A
CMRR  d ,
Acm
where Ad = differential-mode gain; Acm = common-mode gain
- performance degradation due to resistor tolerance; worst-case CMRR
1  Ad
,
CMRR min 
4
where  = fractional tolerance of resistors (e.g., for 5% resistors,  = 0.05)
- problems encountered with physically separated local grounds
Instrumentation amplifier
- differential-mode gain can be controlled by varying a single resistor value
- common-mode signals are not amplified by first stage (input amplifiers); overall
CMRR is greatly improved [added 10/4/12: by the differential-mode gain of the first
stage]
- [added 10/4/12: worst-case CMRR for instrumentation amp:]
1  Ad 2
, where Ad1 = diff-mode gain of 1st stage, and Ad2 = diffCMRR min  Ad1
4
mode gain of 2nd stage
vo 
R6
, where R5 = half
R5
value of the resistor connected between inverting terminals of 1st-stage op-amps (R1
in Fig. 2.20b of textbook), and R6 = value of feedback resistors connected to 1st-stage
op-amps (R2 in Fig. 2.20b)]
- differential-mode input resistance is very high (much higher than for basic diff amp)
- resistor values do not have to be matched carefully for circuit to operate effectively in
many applications
More non-ideal properties of op-amps
- input offset voltage (and output offset voltage)
-
[added 10/4/12: differential-mode gain of first stage: Ad 1  1 
2 of 3
-
-
-
-
o model using voltage source VOS in series with non-inverting input or inverting
input
o polarity of VOS varies from op-amp to op-amp (unpredictable)
o determination of component of output voltage due to VOS (use superposition)
o use offset null potentiometer to mitigate effects (if available on chip)
input bias currents
o model using current sources IB1 and IB2 at inverting and non-inverting terminals,
respectively
o currents IB1 and IB2 always flow into op-amp terminals
o average input bias current spec on datasheet
IB = 0.5(IB1 + IB2), that is, it is the average of IB1 and IB2
o input offset current defined as IOS = |IB1 – IB2|
o unequal bias currents can be expressed as I B1  I B  0.5I OS and I B 2  I B  0.5I OS
(add IOS in one expression and subtract it in the other; either IB1 or IB2 could be the
larger current)
o mitigate effects of average bias current (IB) using resistor in series with one of the
inputs (R3 in Fig. 2.34 of textbook)
o mitigate effects of offset current using offset null potentiometer, as with VOS (also,
IOS and VOS might partially counteract each other in some cases)
o determination of component of output voltage due to IB1 and IB2 (can use
superposition)
slew rate limit (max. slope of output voltage vs. time)
o slope of output voltage = dvo/dt
o slope of some parts of waveform might be less than slew rate, but output might
need to “catch up” from earlier time interval when slew rate was exceeded
o virtual short disappears when slew rate is exceeded
output current limit
o due to internal protection circuitry (a good thing!)
o can cause virtual short at op-amp’s inputs to disappear, as with clipping
output voltage saturation levels
o output voltage can’t actually reach VPOS and VNEG in a real op-amp
o virtual short disappears when saturation occurs
o how to find voltage across inputs when saturation occurs
Relevant course material:
HW:
Labs:
Textbook:
Lecture notes:
Web Links:
Mathcad:
Matlab:
#1-#2
#1-#3
Sections 2.1-2.8 (light on Secs. 2.5 and 2.7)
“Voltage Gain of Inverting Amplifier Using a Real (Non-Ideal) Op-Amp”
“Negative Feedback in the Op-Amp Inverter”
“Real-World Performance of Difference Amplifiers”
Burr-Brown INA 105 Differential Amplifier Module
(none)
(none)
3 of 3