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BTN-2005-1-027
Industrial Experience: 4 Years and 6 months (July 2000 till Date).
 Worked onsite for 3months in Japan.
 One week of Technical Discussion in Japan.
 Two week of Technical Discussion in Singapore for Client review.
 One week of Technical Discussion in Singapore for project proposal.
 One week of Technical Discussion in Germany.
Technologies Worked:
90nm / 1.2V, 2.5V, 3.3V CMOS Toshiba Technology.
0.18U, 0.35U / 1.5V, 1.8V, 3.3V CMOS TSMC / UMC Technology.
0.25U / 2.5V, 3.3V CMOS UMC Technology.
0.5U / 3.3V CMOS UMC Technology.
EDA Tools Known:
Custom Design: CADENCE: DF-II (Version 4.4.8 / 5.0.3).
Composer, ADE, Spectre, Virtuoso, Virtuoso-XL.
MENTOR: Design Architect, ELDO, and Zelga.
OTHER Simulators: H-spice, Smart Spice.
Front End: Verilog, & VHDL.
Simulator: NC-VERILOG.
Project Profile:
Project #1:
CMOS Bandgap Voltage and Current reference.
Client: Toshiba.
Technology: 90nm, CMOS Toshiba Process.
Supply: 3.3V  10.
Temperature: -40º ~ 125º C
Reference Voltage: 1.25V ± 10%, 0.55V ± 10%.
Reference Current: 50uA ± 5%, 10uA ± 5%.
Power Consumption: 4mWatts.
Tools used: Cadence composer, Hspice, Virtuoso-XL.
My Role: Designing and Verification of the Bandgap circuit. The major blocks include
Bandgap, Opamp1 (NMOS input) and Opamp2 (PMOS input).
 Bandgap: Bandgap has designed to generate the Reference Voltage of 1.25V.
 Opamp1: A folded cascode opamp has designed with NMOS differential input to
buffer the 1.25V. The Opamp has Typically 74dB gain and 84° Phase margin.
 Opamp2: A folded cascode opamp has designed with PMOS differential input to
buffer the 0.55V. The Opamp has Typically 63dB gain and 86° Phase margin.
The Reference current generated using resister and mirroring circuit.
Using the virtuoso-XL, the Layout of Opamp1 and Opamp2 has done.
Application: LVDS.
Project #2:
Digital Clock Multiplier with duty cycle correction for Memory Application.
Client: Onsite Japan (Siliconized).
Technology: 0.18u, CMOS UMC.
Supply: 1.5  10.
Temperature: -25º ~ 120º C
Input Frequency: 66MHZ.
Output Frequency: 133MHz, 66MHz.
Locking Time: 20u Sec.
Jitter: <150psec.
Power Consumption: 4.6mWatts.
Tools used: Cadence composer, Spectre, smart-spice, Virtuoso.
My Role: Includes architecture selecting, designing and verifying. The major blocks are
Phase Detector, Control Block, Shift register, and Digitally Controlled Delay line
(DCDL). The implementation is of fully digital way since it’s for memory application.
 PD: Bang-Bang type Phase detector is designed.
 Control Block: To remove the Metastable state and control signal for the shift
register the control block is designed.
 Shift Register: A 128-bit linear bi-directional thermo-coded shift register.
 DCDL: A digitally controlled delay line, with I bit delay resolution of 80ps.
Project #3:
3-wire bus Interface for RF Transceiver.
Client: Offshore Germany (TMM-Siliconized).
Designed at: U&I Scotty computer ltd.
Technology: 0.5u CMOS UMC.
Supply: 3.3  10.
Temperature: -40 to +125C.
Frequency: 40MHZ.
Tools used: Cadence composer, Spectre, Virtuoso, Virtuoso, NC-Verilog.
My Role: Includes architecture selecting, designing, verifying, and Layout designing. The
major blocks designed are Bus Controller, Decoder, Reset and SIPO.
 Bus Controller: Generates control signals for bi-directional data transfer bus
operation and can handle seven target peripherals.
 Decoder: Decodes the serial data multiplexed address of the target peripherals.
 Reset: Reset full Operation when strobe signal is asserted from Master.
 SIPO: Coverts data serial parallel in transmitter and send status signal back to
master.
Application: As Slave controller in RF Transceiver and wireless LAN (WLAN).
Verification: Architecture verified using the Verilog structural level coding.
Layout: The abstract level layout has done using the virtuoso.
Project #4
Low Power 400MHz PLL.
Client: IP (UMSL).
Specification:
Technology: 0.18u, CMOS TSMC.
Supply 3.3v  10
Temperature: -25 to +125C.
Reference Frequency: 25MHz
PLL Output Frequency: 400MHz
Jitter: <50psec.
Locking time: 25usec.
Power Consumption: 18mWatt
Tools used: Cadence composer, Spectre, Virtuoso.
My Role: Designing the loop dynamics major blocks VCO, Charge Pump, PFD and
programmable divider.
 PFD: digital circuit with static gets and Flip-flops.
 Charge pump: Analog block designed to conversion of digital signal to analog
signal typically designed for 50uA.
 VCO: Designed using single ended current starved ring oscillator with gain 150
MHz/V.
 Divider: 2- bit programmable divider, to select PLL output frequency.
Project #5
High Gain Telescopic Opamp for ADC.
Client: FTD.
Specification:
Technology: 0.18u, CMOS TSMC.
Supply 3.3V  10
Temperature: -25 to +125C.
Gain: 91dB
UGB: 300MHz
Phase Margin: 68Deg.
Power Consumption: 3.9mWatt
Tools used: Cadence composer, Spectre, Virtuoso.
My Role: Fully Differential Telescopic cascode structure with Switched capacitor
Common Mode Feedback (CMFB). The Opamp has designed for 1Vpp Output Swing.
Using the Virtuoso-XL the layout has done.
Project #6
6-bit, 66-MSPS Current Steering DAC for WLAN.
Client: IP (UMSL).
Technology: 0.18u, CMOS TSMC.
Supply: 1.8V  10.
Temperature: -25 to +125C.
Number of Bits: 6.
Frequency: 66MHZ.
INL: < 0.6lsb.
DNL: <0.5lsb.
Output Voltage: 1V.
Load: 3K.
Tools used: Cadence composer, Spectre, Virtuoso.
My Role: Designing the 6-bit 66-MSPS DAC with 4-Thermometer and 2-Binary
segmentation architecture. The major blocks designed are Current sources, current
biasing, latches, decoder matrix and the latches. Typically the system was designed for an
output current over 3k so that output peak-to-peak voltage is 1v.
Project #7
Low Power Low Supply 400MHz PLL.
Client: IP (FTD).
Specification:
Technology: 0.18u, CMOS TSMC.
Supply: 1.8V  10
Temperature: -25 to +125C.
Reference Frequency: 25MHz
PLL Output Frequency: 400MHz
Jitter: <30psec.
Locking time: 20usec.
Power Consumption: 8mWatt
Tools used: Cadence composer, Spectre, Virtuoso.
My Role: Designing the loop dynamics, and major blocks VCO, Charge Pump PFD and
divider.
 PFD: Static PFD has designed.
 Charge pump: Analog block designed to conversion of digital signal to analog
signal typically designed for 25uA.
 VCO: Designed using single ended current starved ring oscillator with Gain 100
MHz/V.
 Divider: Asynchronous divide by 16 has designed.
Project #8
3-Lsb offset current Correction Block for ADC.
Specifications
Client: IP.
Technology: 0.18u CMOS 3.3V Process.
Supply: 1.8V  10.
Frequency: 160MHZ.
Temperature: -25 to +125C.
Tools used: Cadence composer, Spectre,
MyRole: Block has designed to correct the 3-lsb offset current in ADC using digital
Implementation.Whenever data is changed from the previous state, the 3-LSB current is
additionally added to output.
Project #9
Digital Blocks for 140-MSPS 10-BIT Pipeline ADC.
Client: IP (UMSL).
Technology: 0.18u CMOS 3.3V TSMC Process.
Supply: 3.3  10.
Frequency: 140MHZ.
Temperature: -25 to +125C.
Tools used: Cadence composer, Spectre,
My Role: Design the digital blocks required for 10-bit 1.5Bit/Stage Pipeline ADC. The
blocks are bit synchronizer (delay block), digital-correction block, clock generator,
latches and decoder blocks for MDAC.
Project #10:
The H-spice to Verilog switch level converter.
Designed at: U&I Scotty computer ltd.
Software used: Lex, Yacc and C- language.
Operating system: Solaris.
My Role: Design a converter to convert the H-spice net list to the Verilog switch level.
The LEX file declares the tokens to be parsed from the input file. The YACC file
declares and checks the grammar for the extracted tokens if grammar matches the token
will be parsed. The parsed parameters are stored in the array. Then using the c program
the output is printed in the Verilog switch level format.
Project #11:
High Speed Full Custom Mixed Signal Library Development for 2.125GHz SerDes.
Technology: 0.25u /3.3V UMC CMOS Process.
Client: Korean
My Role: Designing the digital cells and blocks for 2.125GHz SerDes. Circuits includes
dynamic flip-flop called TSPC, all the basic gates like NOT, AND, NAND, NOR, OR,
EXOR and building blocks like MUX, DECODER, PRIORITY ENCODERS,
COUNTERS etc.
TRAINING COURSE: Completed course on VHDL conducted by SILICON MICRO
SYSTEMS, Bangalore.