Download Current-Fed Switched Inverter

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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 61, NO. 9, SEPTEMBER 2014
Current-Fed Switched Inverter
Soumya Shubhra Nag, Student Member, IEEE, and Santanu Mishra, Senior Member, IEEE
Abstract—High-boost dc-ac inverters are used in solar photovoltaic (PV), fuel cell, wind energy, and uninterruptible power
supply systems. High step-up and step-down capabilities and
shoot-through immunity are some of the desired properties of an
inverter for a reliable, versatile, and low-distortion ac inversion.
The recently developed Z-source inverter (ZSI) possesses these
qualities. However, the realization of ZSI comes at a cost of higher
passive component count as it needs two sets of passive filters. A
switched boost inverter (SBI) has similar properties as ZSI, and
it has one L-C pair less compared to ZSI, but its gain is less than
ZSI. This paper proposes the current-fed switched inverter (CFSI)
which combines the high-gain property of ZSI and low passive
component count of SBI. The proposed inverter uses only one L-C
filter and three switches apart from the inverter structure. The
inverter topology is based on current-fed dc/dc topology. Steadystate analysis of the inverter is presented to establish the relation
between the dc input and the ac output. A pulse width modulation
(PWM) control strategy is devised for the proposed inverter. An
experimental prototype is built to validate the proposed inverter
circuit in both buck and boost modes of operation. A 353-V dc-link
and a 127 V (rms) ac are obtained from a 35.3-V dc input to
demonstrate the boost mode of operation. A 200-V dc-link and a
10.5-V (rms) ac are obtained from a 37.8-V dc input to verify the
buck mode of operation of CFSI.
Index Terms—Current-fed dc/dc topology, electromagnetic
interference (EMI) immunity, switched boost inverter (SBI),
Z-source inverter (ZSI).
I. I NTRODUCTION
V
OLTAGE SOURCE INVERTERS (VSIs) find wide application in uninterruptible power supplies, solar photovoltaic (PV) and fuel-cell applications, wind power systems,
hybrid electric vehicles, industrial motor drives, etc. [1], [2].
The limitation of traditional VSI is that its peak ac output
voltage is always less than the input dc-link voltage [3]. Also,
shoot-through in any of the inverter legs is not permitted as
it results in flowing of high short-circuit current. Therefore,
a dead-band is introduced between the switching signals of
complementary switches of the inverter legs, which, in turn,
causes ac output distortion. High-boost inversion is essential
in small rooftop solar PV/fuel-cell applications when it is
connected to 110–240-V ac systems. For such applications,
either a step-up transformer at the inverter output or a two-stage
boost-inverter structure is used. Inverter systems with step-up
transformers having a high turns ratio are generally bulky and
noisy. Therefore, the alternate option is to go for a transformer-
Manuscript received March 31, 2013; revised August 17, 2013; accepted
September 19, 2013. Date of publication November 8, 2013; date of current version March 21, 2014. This work was supported by the Science and Engineering
Research Board, Government of India, under Grant SR/S3/EECE/0187/2012.
The authors are with the Department of Electrical Engineering, Indian
Institute of Technology Kanpur, Kanpur 208016, India (e-mail: soumyasn@
iitk.ac.in; [email protected]).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TIE.2013.2289907
Fig. 1.
Schematic of a ZSI.
less design [4]–[6]. The maximum gain of conventional boost
converter is achieved at duty ratio (D) near unity, where the
diode and the output capacitor have to sustain a high current
with very small pulsewidth. This results in severe reverse
recovery of the diode, which increases the conduction loss and
produces electromagnetic interference (EMI). This problem
is aggravated at high switching frequencies as the reverserecovery time (trr ) of the device may be larger than the time
available during (1-D) interval [7]. Moreover, a boost converter
has a maximum output to input voltage conversion ratio of 4–5
[8]. Cascaded boost converter or quadratic boost converter can
provide higher gain, but they need more passive components
and passive switches [7]. Converter with coupled inductor can
deliver high gain without extreme duty cycle operation [9], [10].
Single-switch high-gain dc/dc converters using four terminal
switched cells and switched-capacitor cells possess high gain
at reduced switch stress [11].
For high-boost dc-ac inversion, a two-stage structure is
adapted, where a VSI follows a high-gain dc-dc boost topology. The output of the dc-dc stage is voltage-stiff. The major
problem associated with a two-stage dc-ac inversion is that the
inverter can fail due to EMI. EMI can lead to shorting of inverter
legs, resulting in flowing of short-circuit current, and damaging
of the inverter switches.
Z-source inverter (ZSI) was proposed [3] for single-stage dcto-ac inversion with buck-boost capability. ZSI allows shootthrough of the inverter switches. Fig. 1 shows the schematic of
ZSI which has a diode and an “X”-shaped impedance network
between the dc source and the inverter. The ratio of peak
inverter input voltage (V̂pn ) to the input dc voltage Vg (boost
factor) for ZSI is given by
BZSI =
V̂pn
1
=
Vg
1 − 2D
where D denotes the shoot-through duty ratio (interval in which
both switches of any leg of the inverter conduct). As the input to
the inverter is a switched voltage, shoot-through is an allowed
state of operation for this inverter, which leads to better EMI
immunity.
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NAG AND MISHRA: CURRENT-FED SWITCHED INVERTER
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Fig. 3. (a) Circuit diagram of the current-fed dc/dc topology (CFT).
(b) Conversion ratio of the CFT.
Fig. 2.
Schematic and boost factor of SBI.
Switched boost inverter (SBI) was proposed by retaining the
same dynamic states of ZSI but lowering the passive component
count by replacing the “X”-shaped impedance network with an
active network [12]–[14]. Similar to ZSI, SBI also possesses
better EMI noise immunity. SBI has only one L-C pair, as
shown in Fig. 2, which makes it a compact solution. The major
drawback of SBI is that its boost factor is (1-D) times that of
ZSI. Therefore, it is not suited for very high boost inversion.
Both ZSI and SBI have maximum gain near D = 0.5.
This paper presents a current-fed dc/dc topology (CFT)
based inverter. The new inverter is named current-fed switched
inverter (CFSI). It has the following characteristics.
1) It combines the advantages of both ZSI and SBI. The gain
of the proposed circuit is the same as the ZSI. It also has
the same component count as the SBI.
2) The proposed inverter possesses good EMI noise immunity similar to ZSI and SBI.
3) The proposed inverter draws continuous input current
from the dc source, which makes it suitable for renewable
applications.
4) It does not require dead-band for the switching signals,
and hence, output waveform distortion is avoided.
5) It does not require extreme duty ratio operation to achieve
high voltage boost.
In the next section, the basic current-fed dc/dc topology
is reviewed. In Section III, the development of CFSI and its
steady-state characteristics are described. The implementation
and pulse width modulation (PWM) control technique of CFSI
are detailed in Section IV. Section V establishes the relation
between the shoot-through duty cycle, the shoot-through constant, and the inverter modulation index. Performance comparison of CFSI is done in Section VI. Section VII provides
the total harmonic distortion (THD) comparison among the
aforementioned four inverters. Closed-loop control of CFSI is
described in Section VIII. Section IX provides the experimental
verifications. Concluding remarks of this paper are presented in
Section X.
X and X̂ represent the steady-state and peak values of a
signal x(t), respectively, while x̃ and Δx represents the smallsignal variation in x(t) and ripple in x(t), respectively. Use
of superscript “∗ ” for a particular signal denotes its reference
value. For a digital signal Y , its complementary signal is represented by Y . Note that in this paper, GS , GS1 , GS2 , GS3 , and
GS4 represent the gate control signals of switches S, S1 , S2 , S3 ,
and S4 , respectively, fed through a non-inverting gate driver.
Fig. 4. (a) Circuit diagram of the complementary current-fed dc/dc topology
(CCFT). (b) Conversion ratio of the CCFT. (c) CCFT with switch at position 1.
(d) CCFT with switch at position 0.
II. R EVIEW OF THE C URRENT-F ED DC/DC T OPOLOGY
Current-fed dc/dc converter can provide high boost without
operating at extreme duty cycle condition [8]. In the boost
converter, the inductor charges the output capacitor only during
(1-D) interval in a switching cycle. However, the current-fed
dc/dc converter utilizes both D and (1-D) intervals to boost up
the output voltage to a high value.
The circuit diagram of the current-fed dc/dc topology (CFT)
is shown in Fig. 3(a). Under continuous conduction mode
(CCM) operation, in D interval (position 1 of the switch), the
output terminals are connected across the inductor and ground.
In D (position 0 of the switch) interval, the output terminal
connections are reversed. From the volt-second balance of the
inductor L [8], the conversion ratio of CFT can be obtained as
in the following and as shown in Fig. 3(b)
Vc
1
.
=
BCFT (D) =
Vg
2D − 1
From the transfer characteristic of Fig. 3(b), it is noted that
the converter gain is negative when the duty ratio (D) of the
converter is between 0 and 0.5, and the gain is positive when D
is beyond 0.5. Fig. 4(a) shows the complementary current-fed
topology (CCFT) structure which is obtained by interchanging
the D and D intervals of the CFT structure.
In this case, the controlled switches and the passive switches
are interchanged in order to get the CCFT structure from the
CFT structure. The equivalent circuits of the CCFT converter in
the D and D intervals are shown in Fig. 4(c) and (d), respectively. Using inductor volt-second balance [8], the steady-state
output to input conversion ratio can be derived as
Vc
1
.
=
BCCFT (D) =
Vg
1 − 2D
The conversion ratio is plotted in Fig. 4(b). When D < 0.5, the
output of the converter is positive. For D > 0.5, the output polarity becomes negative. In this paper, D < 0.5 is only considered as
a valid region of operation to make switch realization easier.
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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 61, NO. 9, SEPTEMBER 2014
Fig. 6. (a) CFSI topology. (b) Shoot-through switching signal, switch node
voltage, and inductor current waveforms.
Fig. 5. Development of the CFSI topology. (a) CCFT topology. (b) CCFT
topology redrawn. (c) Shifting of load to the switching terminals. (d) Introduction of the VSI switching network to form the complete CFSI topology.
The topology in Fig. 4(a) can be easily extended to a twostage inverter structure by connecting a VSI in place of the
resistor. Buck and boost operations can be achieved by controlling the duty ratio D and the modulation index M of the
inverter properly. The problem with this topology is that it is
not shoot-through protected. Nevertheless, the dc-to-ac gain of
this structure will be higher than the boost cascaded inverter
structure. Another interesting inverter topology with superior
EMI noise immunity can be realized just by rearranging the
devices in CCFT cascaded VSI structure. This will be explained
in the next section.
III. D EVELOPMENT OF THE CFSI S TRUCTURE
A. Development of the Proposed Topology
Fig. 5(a) shows the realization of Fig. 4(a) using active and
passive switches. The load is realized using a resistor Ro . The
circuit is redrawn with a different orientation in Fig. 5(b).
Instead of connecting the load across the capacitor, if it is
connected across the switch Sa , an alternate circuit is realized
as shown in Fig. 5(c). This circuit has special significance for
inverter realization. The switch Sa is replaced by the inverter
legs as shown in Fig. 5(d) [15]. In this case, the shoot-through
interval of inverter legs is equivalent to turning on Sa . This
topology is called CFSI in this paper. Note that here the inverter
input is a switched voltage similar to ZSI and SBI. As shootthrough of the inverter leg (S1 -S4 or S3 -S2 turned on at the
same time) is part of its operation, the CFSI provides singlestage dc-ac inversion as well as buck and boost capabilities. In
the power interval of the inverter, either S1 -S2 or S4 -S3 are
turned on, delivering power to the load. Fig. 5(d) shows the
complete CFSI topology.
In a VSI structure, shoot-through in any of the inverter leg is
not permitted due to the potential damage to switches. Therefore, a dead-time between complementary switching signals is
always in place. As turning on of both switches of an inverter
leg is a valid state, CFSI has better noise immunity.
B. Steady-State Analysis
Fig. 6(a) shows the CFSI structure, with its important switching diagrams shown in Fig. 6(b). In order to establish a relation
between the maximum inverter input voltage (V̂s2 ) and the
Fig. 7. Equivalent circuit of the CFSI in (a) D interval and (b) 1-D interval.
(c) Gain comparison between the CFSI and the boost converter and their
operating region with Vg = 36 V, L = 1 mH, and rL = 100 mΩ.
input dc voltage (Vg ), the inverter shoot-through action is
represented by turning on switch Si .
The initial voltage of the capacitor Co is equal to Vg , and the
initial inductor current is zero before the switching signals are
started. In the shoot-through interval (D interval), switches S
and Si are turned on, and diodes Da and Db become reverse
biased as they are now in parallel with Co . In this interval,
source Vg and capacitor Co charge inductor L together. In nonshoot-through interval (D interval), switches S and Si are
turned off, which forces diodes Da and Db to turn on, and
the inductor charges Co and power are delivered to the ac load
through the inverter. Here, turning off switch Si denotes the
power interval or zero interval of the inverter. The equivalent
circuits of the CFSI in the D and D intervals are shown in
Fig. 7(a) and (b). Assuming small ripple approximation, the
voltage across inductor L and the current through capacitor Co
in one switching period of Ts are given by
V + Vc
During D · Ts
(1)
vL = g
V
−
V
During
(1 − D) · Ts
g
c
−IL
During D · Ts
ic = (2)
IL − Ii During (1 − D) · Ts .
NAG AND MISHRA: CURRENT-FED SWITCHED INVERTER
Fig. 8.
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Implementation of the CFSI topology.
In steady-state equilibrium, using inductor volt-second balance and capacitor charge-second balance [8], we get
Vc
1
(3)
BCFSI (D) =
=
Vg
1 − 2D
IL =
1−D
Ii .
1 − 2D
(4)
The relation between the peak ac output and input Vg is
M
VACpeak = M × Vc =
Vg
1 − 2D
(5)
where M is the modulation index of the inverter. The condition
for the converter to be in CCM is
Vg + Vc
.DTs .
(6)
IL ≥
2L
At duty cycle close to 0.5, nonidealities lead to reduction in
maximum achievable gain. Comparison of conversion ratio of
CFSI and conventional boost converter is shown in Fig. 7(c)
for different values of series resistance of inductor (rL ) to load
resistance (RAC ) ratio. From this figure, it can be clearly seen
that CFSI can provide a gain of 10 without operating at extreme
duty cycle, whereas the maximum gain of the boost converter
is around 5 near D = 0.9.
C. Selection of Passive Components
The inductor current ripple and capacitor voltage ripple are
given by
ΔiL =
Vg + Vc
DTs
L
Δvc =
IL
DTs .
C
(7)
Under CCM condition with Vg = 35 V, Vc = 350 V, Dmax =
0.46, and Ts = 52 μs, the inductor is designed for 20 A and
50% peak-to-peak ripple rating. The capacitor is designed for
0.5-V peak-to-peak ripple, which is about 0.15% ripple for
350-V dc-link voltage. The output ac filter components Lf and
Cf are calculated by keeping unity gain at 50 Hz and at least
40-dB attenuation for high-frequency components.
IV. I MPLEMENTATION AND PWM C ONTROL S TRATEGY
The complete CFSI topology is shown in Fig. 8. Here, the active devices are realized using insulated gate bipolar transistors
(IGBTs). It is to be noted here that no reverse voltage appears
across the switch S as the emitter terminal is either connected
to the ground when Db is on or to the negative terminal of
Fig. 9. (a) Generation of the PWM control signals. (b) PWM control scheme
when Vm (t) > 0. (c) PWM control scheme when Vm (t) < 0.
the capacitor Co when S is on. Thus, an IGBT is sufficient for
realization of S. A bleeder resistance RDC is connected across
capacitor Co to avoid overvoltage appearing at the dc-link. To
incorporate the shoot-through state in the PWM control, the
traditional PWM technique for VSI is modified accordingly.
The modified PWM scheme for CFSI is developed based on the
traditional sine-triangle PWM with unipolar voltage switching
as shown in Fig. 9.
Similar to unipolar sine-triangle PWM, in the positive half
cycle, gate signals GS1 and GS2 are generated by comparing
the sinusoidal modulation signals Vm (t) and −Vm (t) with
high-frequency carrier signal Vtri (t). In order to insert shootthrough, shoot-through signals ST1 and ST2 are generated by
comparing VST and −VST with Vtri (t), and they are logically
added with GS3 and GS4 , respectively. Gate signals GS3 , GS4 ,
and GS are generated using the following logic as shown in
Fig. 9(a) and (b)
GS3 = GS2 +ST1; GS4 = GS1 +ST2; GS = ST1+ST2. (8)
Likewise, in the negative half cycle (Vm (t) < 0) of the modulation signal, GS3 and GS4 are generated by comparing the
sinusoidal modulation signals −Vm (t) and Vm (t) with carrier
signal Vtri (t). The shoot-through signals are generated in the
same way as in the positive half cycle of the modulation signal,
but here, the shoot-through intervals are inserted in gate signals
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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 61, NO. 9, SEPTEMBER 2014
Fig. 10. Generating shoot-through duty interval during the positive half cycle
of modulation signal Vm (t).
GS1 and GS2 . Gate signals GS1 , GS2 , and GS are generated
using the following logic as shown in Fig. 9(a) and (c)
GS1 = GS4 + ST1; GS2 = GS3 + ST2; GS = ST1+ ST2.
(9)
Fig. 11.
Schematic of the two-stage boost-VSI topology.
does not exceed the total available width for zero interval in
any switching cycle, i.e.,
Vm (t)Ts
DTs < Ts − max
(14)
V̂tri
⇒ D < 1 − M.
(15)
From (13) and (15), we get
Inserting the shoot-through interval in GS3 and GS4 in the
positive half cycle of Vm (t) and in GS1 and GS2 in the
negative half cycle of Vm (t) ensures that all of the four switches
participate in shoot-through generation equally.
It is worthwhile mentioning that the carrier signal frequency
is much higher than the modulation signal frequency (ftri fm ), but for demonstration purposes, it is shown to be very less.
where M is the modulation index. Thus, the sum of the shootthrough duty ratio and modulation index must be less than unity.
V. R ELATION B ETWEEN S HOOT-T HROUGH D UTY C YCLE
(D), VST , AND M ODULATION I NDEX (M )
In this section, the performance of the CFSI (shown in
Fig. 8) is compared along with a two-stage boost-VSI structure
(shown in Fig. 11), ZSI (shown in Fig. 1), and SBI (shown in
Fig. 2). The advantages and disadvantages of these converters
are discussed in the following.
Shoot-through duty ratio D can be varied by varying shootthrough constant voltages VST and −VST , as seen from Fig. 10.
To get the mathematical relation between D and VST , equations
for the triangular carrier signal can be written as
− V̂tri t − TS if 0 < t < Ts
TS
4
2
Vtri (t) = V̂ 4 (10)
Ts
Ttri t − 3TS
if
<
t
<
T
S
4
2
4S
also
Vtri (t1 ) = Vtri (t2 ) = −VST
t2 − t1 =
DTs
.
2
(11)
From the aforementioned two equations, the expressions for t1
and t2 can be found as
Ts
Ts
VST
VST
t1 =
t2 =
.
(12)
1+
3−
4
4
V̂tri
V̂tri
Putting these values of t1 and t2 in (11), the expression for the
shoot-through duty interval comes out to be
D =1−
VST
V̂tri
.
(13)
In order to ensure that the shoot-through duty D interval does
not overlap with the power interval of the inverter, D should be
chosen such that the total width of the shoot-through interval
VST > M · V̂tri
(16)
VI. P ERFORMANCE C OMPARISON OF CFSI
A. Conversion Ratio
The conversion ratio (Vc /Vg ) of the CFSI is the same as that
of the ZSI, which is 1/(1-2D). Compared to CFSI, both boostVSI topology and SBI offer a lower voltage conversion ratio.
In a practical scenario, considering maximum boost converter
gain to be 5 and loss-less inversion, the overall rms ac to input
dc conversion ratio (GAC ) for a boost-VSI topology is about
3.53 (which is 5 × 0.707). SBI offers a GAC of 2 [13]. The
experimentally obtained overall conversion ratio for CFSI is 3.6
(127 V rms ac from a 35.3-V dc input). It is to be noted here
that, in the case of the two-stage boost-VSI topology, there is
no restriction on the modulation index of the VSI. However, in
CFSI, the shoot-through duty ratio puts some restriction on the
modulation index as given by (15). This is similar to the case in
ZSI and SBI.
B. Dead-Time Requirement
In order to prevent shoot-through in the inverter bridge in a
boost-VSI topology, a dead-time circuit is required so that the
switching signals do not overlap. Also, to nullify the waveform
distortion due to dead-time, additional dead-time compensation
circuits are required [16], [17]. Similar to ZSI and SBI, CFSI
uses shoot-through as an active state in its operation, and hence,
it does not require any dead-time and compensation circuit.
NAG AND MISHRA: CURRENT-FED SWITCHED INVERTER
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TABLE I
P ERFORMANCE C OMPARISON OF CFSI
C. EMI Immunity
F. Voltage Stress of Switching Devices
The boost-VSI topology may fail at the occurrence of a
shoot-through event due to EMI noise which cannot be eliminated by using a dead-time circuit. As shoot-through of the
inverter leg is allowed in CFSI, it exhibits better EMI noise
immunity similar to ZSI and SBI.
Comparison of voltage stresses of the switches is done in
Table I. From the table, it can be seen that all of the switches of
all topologies have to withstand a voltage equal to the dc-link
voltage, except for the diode Db and switch S of SBI which
have to withstand a voltage of (Vc -Vg ).
D. Component Count
The number of passive components required in ZSI is 6,
whereas for CFSI and SBI, it is 4 owing to one less L-C
pair. Again, CFSI and SBI need 11 switches compared to 9
of ZSI (break-up shown in Table I). Although the total component count remains the same for ZSI, SBI, and CFSI, due to
the elimination of passive magnetic components, CFSI leads
to a more compact design in a low-power application. The
total component count for the boost-VSI topology is one less
compared to others.
G. Input Current Property
Due to the presence of the diode in series with the dc source,
SBI and ZSI take discontinuous input current from the supply.
In some renewable applications, like solar PV and fuel cell,
an input filter stage becomes essential as discontinuous input
current may lead to decay in life expectancy of the renewable
sources. On the other hand, due to the presence of the input inductor, CFSI draws continuous input current which minimizes
the need of extra input filter stage. The boost-VSI topology also
possesses the continuous input current property.
H. TDR
E. Extreme Duty Ratio Operation
The extreme duty ratio operation of a boost converter leads
to severe reverse recovery of the diode, which, in turn, leads
to enhancement of EMI noise level and imposes restriction
over the switching frequency. In CFSI, the duty ratio is always
limited to 0.5 for a positive dc bus voltage, similar to ZSI and
SBI which eliminate the possibility of severe reverse recovery
of the diode.
Total device rating (TDR) is defined as the sum of individual device ratings of all of the switching devices, which
is the product of the peak voltage across the device and the
peak current through the device. CFSI possesses the highest
TDR (7 ∗ BCFSI ∗ Pout ), and ZSI possesses the lowest TDR
(5 ∗ BZSI ∗ Pout ) among all four inverter topologies as shown
in Table I. It is also observed that ZSI needs two inductors
(L1 and L2 ) and two capacitors (C1 and C2 ) that are twice
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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 61, NO. 9, SEPTEMBER 2014
the value compared to the inductor (L) and capacitor (Co ) of
CFSI, SBI, and boost-VSI topology to have the same current
and voltage ripple, i.e., L1 = L2 = 2L and C1 = C2 = 2Co
(refer to Figs. 1, 2, 8, and 11).
VII. THD C OMPARISON OF CFSI
THD analysis is done to give a comparison among the four
inverter topologies, namely, CFSI, SBI, ZSI, and boost-VSI
topology, for the same operating conditions. While carrying
out the THD analysis, the following operating conditions are
maintained.
1) The same duty ratio (D = 0.45) and output ac rms voltage (110 V) are maintained for all topologies.
2) A similar PWM scheme as in Section IV is provided
for CFSI, SBI, and ZSI. A conventional unipolar sinetriangle PWM scheme is provided for the boost-VSI
topology.
3) The values of inductor L and capacitor Co are kept
the same to maintain the same input current and dclink voltage ripple. For the same reason, the impedance
network of ZSI consists of inductors (L1 and L2 ) that are
twice the value of L and capacitors (C1 and C2 ) that are
twice the value of Co (refer to Figs. 1, 2, 8, and 11).
The THD analysis is done by varying the ac load of the
inverters. To maintain the same current and voltage ripple, L
and Co are chosen as 1 mH and 940 μF, respectively. L1 and L2
are chosen to be 2 mH, and C1 and C2 are chosen to be 1880 μF.
Fig. 13 shows the harmonic spectrum of the output ac voltage
of the boost-VSI topology and CFSI.
The harmonic spectra
of SBI and ZSI are the same as CFSI, and hence, they are not
shown. This results in the same THD at the output for CFSI,
SBI, and ZSI, shown in Fig. 12 for varying load conditions
which are much lower than those of the boost-VSI topology.
Simulation results depict that THD decreases with the increase
in values of inductor L and capacitor Co . Note that the presence
of a limited-value capacitor leads to lower order harmonics in
all of the topologies.
Fig. 12. Harmonic spectrum of (a) boost-VSI topology and (b) CFSI at 110 V
rms ac and 1.5-A load condition.
VIII. C LOSED -L OOP C ONTROL OF CFSI
The simplified equivalent circuit diagram of CFSI is shown
in Fig. 14. The bleeder resistance is represented by resistance
RDC , and the inverter bridge is represented by a parallel combination of a switch Si and a resistor Ri [17]. Using state space
averaging technique [8], the small signal state space model of
the CFSI can be obtained as follows:
x̃˙ = A · x̃ + B · ũ
ỹ = E · x̃ + F · ũ
(17)
where x̃ = [ĩL ṽC ]T , ũ = [d˜ ṽg ]T , ỹ = [ṽC ], E = [0 1], F = [0 0]
(2D−1)
0
L
A = (1−2D)
1
− C1o RDC
+ 1−D
Co
Ri
2VC
1
L
L .
B = 1. 2VC
0
Co
Ri − 2IL
Fig. 13. Comparison of THDs among the four inverter topologies with
varying load currents.
NAG AND MISHRA: CURRENT-FED SWITCHED INVERTER
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Fig. 14. Simplified equivalent circuit diagram of CFSI.
From the state space model in (17), the control to output transfer
˜ of the dc bus voltage controller can be
function (= ṽC /d)
calculated as
Fig. 15. Block diagram of the cascaded ac bus voltage controller.
ṽC
−b1 s − b0
=
, where
a2 s 2 + a1 s + a0
d˜
a0 = RDC Ri (1 − 2D)2
a1 = L (Ri + (1 − D)RDC )
a2 = LCo RDC Ri b0 = 2RDC Ri VC (2D − 1)
2VC
b1 = LRDC Ri 2IL −
.
Ri
The output side equations can be written as (from Fig. 8)
Fig. 16. DSP-based closed-loop control scheme of CFSI.
diLf
Rf
1
=−
iLf +
(vAB − vo )
dt
Lf
Lf
dvo
iLf
vo
=
−
.
dt
Cf
RAC Cf
(18)
TABLE II
P ROTOTYPE S PECIFICATION
(19)
Using DQ transformation, (18) and (19) can be transformed
to the following control to output transfer functions in
s-domain [13]
Id (s)
Iq (s)
1
(s) = U (s) = sL + R
Uid
f
f
iq
(20)
Vd (s)
Vq (s)
RAC
(s) = U (s) = sR
Uvd
AC Cf + 1
vq
(21)
TABLE III
C OMPONENT L IST
where
= VABd − Vd + ωLf Iq = A
Uid
Uiq
= VABq − Vq − ωLf Id = A
Uvd
= Id + ωCf Vq = Id∗
Uvq
= Iq − ωCf Vd = Iq∗ .
The block diagram of the ac bus voltage controller is shown
in Fig. 15. The outputs of the controller are the modulation
signals in the DQ domain, i.e., Md and Mq with B = Vc in
Fig. 15. From these two signals, the sinusoidal modulation
signal M (= Vm (t)) is obtained using DQ to 1-ϕ transformation
using the following equations:
Uid
= Md
Vc
Uiq
= Mq
Vc
Vm (t) = M = Md sin θ + Mq cos θ
(22)
(23)
Vd , Vq = d, q-axis components of Vo , Vd∗ , Vq∗ = d, q-axis references for Vo , VABd , VABq = d, q-axis components of VAB ,
Id , Iq = d, q-axis components of iLf , Id∗ , Iq∗ = d, q-axis references for iLf , ω = 2πf , and f = 50 Hz.
Fig. 16 shows the complete closed-loop control scheme of
CFSI. The control scheme is implemented on a Texas Instruments TMS320F28335 DSP. Analog sensed signals VC , Vo , and
4688
Fig. 17.
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 61, NO. 9, SEPTEMBER 2014
PWM control signals for the (a) positive half cycle of Vm (t), (b) negative half cycle of Vm (t), and (c) switch node voltage waveforms of the converter.
Fig. 18. Steady-state operation of the inverter circuit of CFSI in (a) boost mode, (b) buck mode, and (c) boost mode with output filter inductor current and output
load current at Vg = 33 V.
iLf are fed to the built-in 12-b ADC of the DSP. The DSP-based
controller takes the digital output of the ADC and produces
shoot-through duty D and modulation index M such that the dc
bus and ac bus voltages are regulated to their reference values
VC∗ and Vo∗ , respectively.
All of the closed-loop controllers are realized using a PI
controller. As the synchronous reference frame control method
is adapted for the ac controller, the reference for the ac bus
controller is given in d-q domain (i.e., Vd∗ , Vq∗ , and angular
frequency ω). The outputs of the closed-loop controller are D
and M (= Vm (t)), which are fed to the ePWM modules of the
DSP to generate gate signals Gs , Gs1 , Gs2 , Gs3 , and Gs4 .
IX. E XPERIMENTAL V ERIFICATION
A laboratory prototype of CFSI, shown in Fig. 8, is developed
to verify the theoretical analysis done in this paper. The PWM
control scheme, shown in Fig. 9, is realized in an analog PWM
controller. The prototype specifications are tabulated in Table II.
The carrier frequency is chosen according to the highest switching frequency of the switching devices. The values of L and Co
are decided based on (7). A 25-kΩ 10-W bleeder resistance is
connected across Co . The lists of semiconductor devices used
are tabulated in Tables II and III. The analog PWM controller
is developed using operational amplifiers, comparators, and
logic gates. The closed-loop control scheme is developed using
TMS320F28335 DSP.
The PWM switching signals for CFSI are shown in Fig. 17(a)
and (b) for the positive and negative half cycles of modula-
tion signal Vm (t), respectively. Fig. 17(c) shows the converter
switch node voltages along with the input voltage and dc-link
capacitor voltage. With input voltage Vg of 35 V, a dc-link
output voltage Vc of 375 V is obtained at D = 0.46, as shown
in Fig. 17(c). The reduction in achieved gain can be attributed
to the nonidealities.
Fig. 18(a) and (b) shows the steady-state operation of CFSI
in boost mode and buck mode, respectively. In boost mode, a
127-V (rms) 50-Hz output is obtained from a 353-V dc-link
voltage, where the input voltage Vg is 35.3 V.
In buck mode, a 10.5-V (rms) 50-Hz output is obtained from
a 200-V dc-link voltage, where the input voltage Vg is 37.8 V.
Fig. 18(c) shows the steady-state operation with dc-link voltage
(Vc ), current through output filter inductor Lf (iLf ), output ac
voltage (Vo ), and output load current (iAC ) with a 200-Ω ac
load at an input voltage Vg of 33 V. To verify the regulation and
dynamic performance of CFSI, a 30% step change is applied in
ac load. Fig. 19(a) shows the waveforms with 30% step-down
change in ac load when the load is changed from 138 to 180 Ω.
Fig. 19(b) shows the waveform with 30% step-up change in ac
load when the load is brought back to 138 Ω.
In both cases, the ac bus voltage Vo is regulated at 110 V
(rms; Vo pk−pk = 312 V which is encircled in red in Fig. 19),
and the dc bus voltage Vc is regulated at 330 V with an
input voltage of 35 V. Comparison of experimental gain with
ideal gain of CFSI is shown in Fig. 20(a). The experimental
gain curve is drawn for three input voltage levels, e.g.,Vg =
12 V, 24 V, and 36 V. From the figure, it is seen that the
gain at low duty ratio is higher than the ideal gain. This
NAG AND MISHRA: CURRENT-FED SWITCHED INVERTER
4689
X. C ONCLUSION
Fig. 19. Dynamic performance of the ac bus controller with (a) 30% stepdown change in ac load and (b) 30% step-up change in ac load.
This paper has proposed a high-boost inverter structure based
on the current-fed dc/dc converter topology. The proposed converter (CFSI) can work in both buck mode and boost mode and
exhibits improved EMI noise immunity. The high gain of the
converter is obtained due to insertion of shoot-through interval.
In this paper, the development of the CFSI circuit has been
described in detail along with its steady-state characteristics.
The PWM switching scheme and the restriction on modulation
index have also been described. The proposed inverter has been
compared with traditional boost-VSI topology, SBI, and ZSI to
present the advantages and disadvantages of CFSI. This paper
has also presented a DSP-based closed-loop control scheme
meant to regulate the ac and dc bus voltages. The proposed
converter is tested on a laboratory prototype and verified.
R EFERENCES
Fig. 20. (a) Comparison of experimentally obtained gain (Vc /Vg ) with ideal
gain of CFSI. (b) Phenomenon of finite commutation time.
Fig. 21. Efficiency versus load power plot of CFSI for a gain of 7.5.
phenomenon is due to the commutation delay of the IGBT
switches which take some time to get turned off after the
gate signal becomes low due to its finite turn-off delay time
td(off) (td(off) 10 td(on) ) which is shown in Fig. 20(b). It can
also be seen that the gain of the converter near the duty ratio
of 0.5 is restricted due to the nonidealities of the converter.
Efficiency versus load power plot of the CFSI is shown in
Fig. 21 for converter gain (Vc /Vg ) of 7.5. It is to be noted
here that the switching frequency of switch S (in Fig. 8)
is twice the carrier frequency ftri , i.e., 19 kHz, while the
switching frequencies of the inverter switches (S1 , S2 , S3 , S4 )
vary from 9.5 kHz to around 17.8 kHz but can never exceed
19 kHz.
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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 61, NO. 9, SEPTEMBER 2014
Soumya Shubhra Nag (S’13) received the B.E.E.
degree from Jadavpur University, Kolkata, India, in
2009 and the M.Tech. degree in electrical engineering from the Indian Institute of Technology Kanpur,
Kanpur, India, in 2011, where he is currently working toward the Ph.D. degree.
His research interests include power electronics
for dc distribution systems, inverter topology, PWM
control techniques of inverters, and digital control in
power electronics.
Santanu Mishra (S’00–M’04–SM’12) received
the B.Tech. degree in electrical engineering from
the College of Engineering and Technology,
Bhubaneswar, India, in 1998; the M.Tech. degree in
energy systems engineering from the Indian Institute
of Technology Madras, Chennai, India, in 2000; and
the Ph.D. degree from the Department of Electrical
and Computer Engineering, University of Florida,
Gainesville, FL, USA, in 2006.
He was a Senior and Staff Application Engineer
with the International Rectifier Corporation from
2004 to 2008. He is currently an Associate Professor with the Indian Institute
of Technology Kanpur, Kanpur, India. His research interests include renewable
power conversion, high-frequency power converters, and converter modeling
and control.