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Delay Locked Loop with Linear Delay Element TELSIKS 2005, Niš Goran Jovanović, Mile Stojčev and Dragiša Krstić Faculty of Electronic Engineering, Niš, Serbia and Montenegro Definition of DLL DLL circuit is designed for fine, precise, and accurate pulse delay control in a high-speed digital and mixed integrated circuits. Applications of DLL • achieve correct synchronization between different digital blocks (CPU and SDRAM interface, ...), • eliminate clock skew and jitter within VLSI ICs, • low-jitter clock synthesis, • implementation of Time-to-Digital-Converter with Vernier delay pattern, • PN code tracking in spread spectrum systems… Types of the DLL architecture The DLL structure is based on a delay element. According to the principle of delay generation DLL architectures classified as: VCDL CLKin •hybrid (dual loop) DL CLKin C PS Vctrl LPF CP UP DOWN PD Digital DLL Analog DLL VCDL DCDL CLKin CLKout FSM PD CLKout C •analog, •digital, and CLKout PS Vctrl CP FSM PD LPF UP Hybrid DLL DOWN PD VCDL – voltage controlled delay line, PD – phase detector, CP – charge pump, PS – phase selector, FSM – finite state machine Classification of delay line elements Variable delay line elements are classified as: • Digital- Controlled Delay Elements (DCDEs) realized as series of delay elements of variable length (the number of elements in a chain determines the amount of the delay). • Voltage-Controlled Delay Elements (VCDEs) are inverter-based circuits, efficient in applications where small, accurate, and precise amount of delay is necessary to achieve. Common to VCDLs Advantages: • Simple structures • Fine delay resolution Disadvantages: • Voltage controlled DLs have non-linear transfer function, delay variation in term of control voltage Problem of VCDL realization was considered by: • • • Y. Moon, et al., “An All-Analog Multiphase Delay-Locked Loop Using a Replica Delay Line for Wide-Range Operation and Low-Jitter Performance”, IEEE JSSC, vol.35, No. 3, pp. 377-384, March 2000. M. Maymandi-Nejad, M. Sachdev, “A digitally Programmable Delay Element: Design and Analysis”, IEEE Trans. on VLSI Systems, vol. 11, No. 5, October 2003. G. Jovanović, M. Stojčev, “Voltage Controlled Delay Line for Digital Signal”, Facta Universitatis, Series: Electronics and Energetic, vol. 16. No. 2, pp. 215-232, August 2003... What we propose • Linearization of VCDL’s transfer function • We use Current Starved DE. • Why: – Simple structure – Relatively wide range of delay regulation • How we achieve linear VCDL? – We modify the bias circuit. – We use a non-linear bias circuit which is based on the square-law characteristics of a MOS transistor in saturation. – By a cascade connection of two non-linear elements, the bias circuit and the current starved delay element, we obtain a linear transfer function (delay in terms of control voltage). Delay Line Element – standard solution Cascade composition of a bias circuit and VCDL Vdd 1.5/21 VBP Vctrl linear bias circuit VBP Vdd Vdd Icp M5 M2 IN VBN M1 2/21 2/21 OUT 2/7 VBN Cload M3 2/7 M6 Icp M4 1.5/7 voltage control delay element where: tdelay C Vsw I cp tdelay - delay time, C - parasitic output capacitance, Vsw clock buffer (inverter) swing voltage, Icp - charging/discharging current of C. Bias circuit with reciprocal current regulation proposal Vdd I0' Vctrl Vdd Bias Circuit MS1 VBP R VBP M2 MS2 B1 B1 MA1 I1 I2 WA / L A WA / LA Current Starved Delay Elements Vdd M4 MD2 Vctrl Vctrl+ Vdd I0'' Vdiff R MD1 Vdd IBss B2 in VBN out M5 M3 Icp MS3 (b) (a) M6 C M1 VBN MA2 Icp Schematic of a bias circuit with analytic model Vdd Vdd MB1 6/28 MB2 6/28 4/28 MB3 3/28 MB5 MB4 4/28 d_BP d_BPc I0' Vctrl MD1 3/28 Vdiff R R 2/28 Vctrl - MB6 Vdd MS1 I0'' 6/21 MD2 BP 2/28 VB1 I1 Vtn kn I1 B1 W A / LA MA1 I1 I 0' I2 B1 IBss B2 BN MS3 W A / LA A MA2 Vctrl V I 2 I 0'' ctrl R R 6/7 V 4 kp MS2 6/21 Vctrl+ I Bss A B I1 C I1 To Delay Line Fro ban m dcirc gap uit AGND B dd 2Vtp Vtn k p 2 Vdd 2Vtp Vtn 4 1 kp C 4 kn kn 2 Bias circuit HSpice simulation Icp [A] 28 22 18 Charge-discharge current variation in terms of control voltage 14 Approximation Error [%] Relative approximation error of the reciprocal charge-discharge current variation in terms of control voltage 26 -0.8 -0.4 0 Vctrl [V] 0.4 0.8 1 a) 2 1 0 -1 -2 -3 -4 -0.8 -0.4 0 Vctrl [V] 0.4 0.8 1 b) Current starved VCDL with linear delay regulation - Complete design Vctrl+ I I V VBP V2 V CLKin I Vctrl- bias Schematic of four stage DL VBN VBP VBP VBP VBP VCDE1 VCDE2 VCDE3 VCDE4 VBN VBN VBN VBN CLKout1 OB1 CLKout2 OB2 OB3 delay line OB4 CLKout3 CLKout4 HSpice delay line simulation – results relate to CLKout4 – tdelay [ns] 60 50 40 Time delay, tdelay , in term of control voltage Vctrl 30 25 -0.8 -0.4 0 0.4 Vctrl [V] 0.8 1 0.8 1 a) 3000 2500 2000 1500 Relative approximation error of time delay, tdelay , in term of control voltage Vctrl tdelay [ps] 1000 500 0 -500 -1000 -0.8 - 0.4 0 Vctrl [V] 0.4 b) DLL differential architecture VCDL CLKout Voltage Controlled Delay Line VBN V2 I I V V I DOWN UP Charge Pump CP2 Charge Pump Vctrl- DOWN Vctrl+ LPF2 C2 C1 UP Bias circuit VBP LPF1 ►differential charge pump, ►two low-pass filter and ►nonlinear bias circuit with differential input CLKin CP1 New DLL architecture with: PD Phase Detector Vdd Other DLL’s parts: UP Vdd DOWN [8] [8] From phase detector 1.5/16 [8] CP_BP 8/16 From bias CP_BN Vctrl + 8/8 [8] From phase detector 1.5/16 - dual charge pump - dynamic phase detector Vdd Vdd DOWN Vdd [8] CP_BP From bias CP_BN M14 1.5/7 Vdd UP REF M12 M15 1.5/7 1.5/4 DOWN [8] Charge pump - CP1 Charge pump - CP2 1.5/4 M17 1.5/7 M13 1.5/8 [8] M18 1.5/7 M16 1.5/4 1.5/4 BACK Vdd M21 Vdd Vdd M24 1.5/7 Vdd M22 M28 1.5/7 M25 1.5/7 1.5/4 BACK BACK UP UP M26 1.5/4 REF REF 1.5/4 M27 1.5/7 M23 UP 1.5/4 DOWN a) 8/8 [8] 1.5/8 M11 8/16 DOWN b) Vctrl- HSpice simulation of the full DLL CLKin CLKout VctrlVctrl+ UP DOWN Conclusion ►An implementation of DLL with a linear VCDL is proposed. ►Current starved DL is used. ►Linearization is achieved by modifying the bias circuit of current starved DL. ► HSpice simulation results points to the fact that for 1.2 m CMOS technology high delay linearity (error is less then 500 ps) within the full range of regulation (from 28 to 55 ns) is achieved. ►Linear DL requests new DLL architecture with differential charge pump, two low-pass filter and bias circuit with differential input. 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