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Department of Electrical and Computer Engineering
Digital System Design 1
Final Research Project
Shaun Murphy
April 25, 2003
In this digital system design class, we discussed concepts and designs of components
typically found in a von Neumann computer. This architecture performs very well for many
things, but for certain tasks, such as emulating natural information processing that biological
entities handle routinely, their performance is sub optimal. This is where the need for a newer
and better-suited architecture is observed.
Natural processing is a method in which a tolerance for imprecision and uncertainty is
exploited such that a flexible and robust solution is generated. A set of theories have been
established to embrace natural processing and collectively they are called soft computing. Soft
computing is comprised of three main classes of methodologies: neural networks, fuzzy logic,
and probabilistic reasoning. Each of these methodologies can be considered as a solution to
certain types of applications but they are in fact complementary to each other, and in many cases,
it is better to utilize them in combination rather than in exclusivity. Two of the soft computing
methodologies have had some development work and contain the most potential for future
architectures: neural networks and fuzzy logic.
Neural networks address the issue of effect information organization and processing.
Since biological brains are massively parallel, self-organizing computational networks, they are a
model of an ideal prototype after which special purpose hardware can be modeled.
Understanding a biological brain requires an intimate understanding of the basic processing
elements: neurons. This field is quite expansive and just introducing this material would
consume many pages and a formal design or derivation could consume an entire semesters worth
of work.
Fuzzy logic attempts to deal with imprecision and approximate reasoning as opposed to
precision and formal reasoning. This is an attempt to duplicate the ability of a brain to
summarize data and focus on decision relevant information. A variation of this logic is multivalued logic. This supplies the need to conserve chip area in order to have extremely complex
circuits. These circuits allow signals with more than two values to provide a significant savings
in chip area. Since this area is closely related to the material we discussed in this class, I will
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inspect the multi-value logic area in this paper. This will include a simple theoretical design and
development of a half-adder.
Researchers have always questioned the use of the binary system in today’s architectures.
They argue that it does not fully utilize interconnection wires between components given the fact
that wires constitute a large part of any computer system. This is particularly true with any VLSI
chip where interconnections comprise about 70% of the total system. By letting each wire carry
more than two levels of logic, a significant savings in chip area is achieved.
Binary
Signals
Multi-valued
signals
Encoder
Decoder
Binary
Signals
Multi-valued Signals
Figure 1 The use of a multiple valued logic circuit
integrated into a binary-valued system
In general, for a n radix system, the values can be labeled as 0, 1, … n-1. Typically,
systems are modeled with a radix that is a power of 2 such as 4, 8, and 16. This makes the
conversion between binary logic and multiple-valued logic very efficient. Binary systems
obviously dominate the design of digital systems and multiple-valued components can only
comprise certain elements of a system, therefore a code conversion, such as the one presented in
this paper, are required. Figure 1 illustrates how a multiple-valued component can be embedded
into a binary system. The encoder circuit (this is where a radix of a power of two allows for
efficiency) converts binary inputs to multiple-valued outputs. The decoder circuit then converts
the multiple-valued inputs to binary outputs.
Traditional binary design techniques, such as a truth table, can be used in designing the
multiple-valued circuits. The only difference being more values must be considered in the
multiple-valued system design.
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Input
Output
A
B
C
X
0
0
0
0
0
1
0
1
..
..
..
..
3
3
1
2
Table 1 Truth table of a half adder for four-valued
inputs (A, B)
An example of this technique adaptation, the truth table for the two variable, four-valued
half adder (shown in Table 1) adds two input signals (A,B) producing an output X and a carry C.
In theory this is a rather convenient solution, but how practical is it? After all, most of our
hardware switches between off and on (0, 1.) Many designs have been presented for multiplevalued circuits. One such design is called a T-gate and is actually a radix four, four-input
multiplexer. (The T-gate was first published in Kameyama, Michitaka, T. Hanya, and T.
Higuchi, “Design and Implementation of Quaternary NMOS Integrated Circuits for Pipelined
Image Processing,” IEEE J. Solid-state Circuits, SC-22(1), 1987, pp. 20-27.)
The function of the T-gate can be defined as
Z = xi, if s = i
where s is a four-valued input select signal that takes on the value 0-3. Each input xi is also a
four-valued signal ranging from 0-3. This functional description of the device can be further
viewed as a traditional digital system design exercise. From the equation, we can construct a
trivial entity (or black box) view of this device (see Figure 2.)
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X0
X1
X2
X3
X1
X2
s
T-gate
Z
X0
X3
a
a
b
s
c
d
Literal Gates
Z
Figure 2 Block and Circuit Diagram of the T-gate
Figure 2 presents a detailed schematic of the T-gate. The transistors are used as switches
for connecting an input signal to the output signal. An input signal appears at the output if the
gate voltage of the corresponding transistor goes high. The gate voltage of each transistor is
controlled by a ‘literal’ gate. The output voltages of these gates go high if the logical value is
equivalent to their respective values. In our previous example, the logical values 0, 1, 2, and 3 of
the select line correspond to the voltages 0, 2, 4, and 6 volts. Each gate consists of a few
transistors and its output increases based on a certain input voltages. To illustrate this, we’ll set
the signal s at 4V. The output voltage of the literal gate c goes high, while the outputs of the
other gates stay low. This is implemented by employing transistors with different threshold
voltages in different literal gates.
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2
3
1
0
2
3
1
0
0
3
3
2
T1
2
1
1
0
T2
B
1
3
0
3
2
2
1
3
0
3
T3
A
2
1
2
0
1
0
T4
3
2
1
0
T5
X
Figure 3 Diagram for the sum output of a half-adder using Tgates.
The T-gate can be used to design any combinational or sequential circuit. Figure 3
illustrates the sum output of our half-adder. Although this gate provides a structural and generic
tool for design multi-valued circuits, it obviously does not lead to efficient or minimized designs.
Today, multi-valued logic is used as a mathematical notation in logic synthesis
applications, which allows for efficient minimization of functions. Intel has fabricated a multivalue memory chip and multi-valued image processing VLSI chips are beginning to be
fabricated. Multi-valued logic provides a great solution for many applications, like memory
design, where it is desirable to reduce the number of lines for parallel transmission of large
amounts of data. (Smith, Kenneth C., “A Multiple-Valued Logic: A Tutorial and Appreciation,”
Computer, 21(4), 1988, pp.17-27.) In general, this reduces the interconnection complexity by
reducing the number of pins and increasing the data-processing capability per chip area. Multivalued logic has obvious applications in software as well as hardware. Multi-valued gates are
built as circuits and multi-valued VLSI chips can be constructed with them. This approach is still
uncommon in industry, but many researchers expect that new optical, DNA and quantum
computers, which will arrive before year 2020, will have to use this logic.
References
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Barto, A.G. and P. Anandan, “Pattern Recognizing Stochastic Learning Automata,” IEEE Trans.
Systems Man Cybernetics, SMC-15(3), 360-375.
Kameyama, Michitaka, T. Hanya, and T. Higuchi, “Design and Implementation of Quaternary
NMOS Integrated Circuits for Pipelined Image Processing,” IEEE J. Solid-state Circuits, SC22(1), 1987, pp. 20-27.
Smith, Kenneth C., “A Multiple-Valued Logic: A Tutorial and Appreciation,” Computer, 21(4),
1988, pp.17-27.)
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