Download 2012_0080. Introduction to MV logic

Introduction
By Marek Perkowski
Some slides of M. Thornton used
Introduction:
What is the sense
in MV logic
THE MULTIPLE-VALUED
LOGIC.
• What is it?
• WHY WE BELIEVE IT HAS A BRIGHT
FUTURE.
• Research topics (not circuit-design oriented)
• New research areas
• The need of unification
Is this whole a nonsense?
• When you ask an average engineer from industry,
he will tell you “multi-valued logic is useless
because nobody builds circuits with more than
two values”
• First, it is not true, there are such circuits built by
top companies (Intel Flash Strata)
• Second, MV logic is used in some top EDA tools
as mathematical technique to minimize binary
logic (Synopsys, Cadence, Lattice)
• Thirdly, MV logic can be realized in software and
as such is used in Machine Learning, Artificial
Intelligence, Data Mining, and Robotics
Short Introduction: multiple-valued logic
Signals can have values from some
set, for instance {0,1,2}, or {0,1,2,3}
{0,1} - binary logic (a special case)
{0,1,2} - a ternary logic
{0,1,2,3} - a quaternary logic, etc
1
2
21
M
I
N
Minimal value
1
2
3
23
M
A
X
23
Maximal value
Binary logic is doomed
• It dominates hardware since 1946
• Many researchers and analysts believe that the
binary logic is already doomed - because of
Moore's Law
• You cannot shrink sizes of transistors indefinitely
• We will be not able to use binary logic alone in
the generation of computer products that will start
to appear around 2020.
Quantum phenomena
• They will have to be considered in one way
or another
• It is not sure if standard binary logic will be
still a reasonable choice in new generation
computing
• Biological models
Future “Edge” of MVL
• Chip size and performance are increasingly related
to number of wires, pins, etc., rather than to the
devices themselves.
• Connections will occupy higher and higher
percentage of future binary chips, hampering
future progress around year 2020.
• In principle, MVL can provide a means of
increasing data processing capability per unit chip
area.
• MVL can create automatically efficient
programs from data
From two values to more values
• The researchers in MV logic propose to abandon
Boolean principles entirely
• They proceed bravely to another kind of logic, such
as multi-valued, fuzzy, continuous, set or
quantum.
• It seems very probable, that this approach will be
used in at least some future calculating products.
Multi-Valued Logic Synthesis(cont)
• The MVL research investigates
– Possible gates,
– Regular gate connection structures (MVL PLA),
– Representations - generalizations of cube calculus
and binary decision diagrams (used in binary world to
represent Boolean functions),
– Application of design/minimization algorithms
– General problem-solving approaches known from
binary logic such as:
• generalizations of satisfiability, graph algorithms or
spectral methods,
• application of simulated annealing, genetic algorithms and
neural networks in the synthesis of multiple valued
functions.
Binary versus MV Logic Synthesis Research
• There is less research interest in MVL because such
circuits are not yet widely used in industrial products
• MV logic synthesis is not much used in industry.
• Researchers in hundreds
• Only big companies, military, government. IBM
• The research is more theoretical and fundamental.
• You can become a pioneer – it is like Quine and
McCluskey algorithm in 1950
• Breakthroughs are still possible and there are many
open research problems
• Similarity to binary logic is helpful.
However………,
• if some day MV gates were introduced to
practical applications, the markets for them
will be so large that it will stimulate
exponential growth of research and
development in MV logic.
• and then, the accumulated 50 years of
research in MV logic will prove to be very
practical.
Applications
• Image Processing
• New transforms for encoding and
compression
• Encoding and State Assignment
• Representation of discrete information
• New types of decision diagrams
• Generalized algebra
• Automatic Theorem Proving
History
and
Concepts
Jan Lukasiewicz (1878-1956)
• Polish minister of
Education 1919
• Developed first ternary
predicate calculus in
1920
• Many fundamental works
on multiple-valued logic
• Followed by Emil Post,
• American logician born in
Bialystok, Poland
Literals
MV functions of single variable
• Post Literals:
2
1
0
1
2
2
1
1
2
0
1
2
0
1
2
0
1
2
• Generalized Post Literals:
2
2
2
1
1
1
0
1
2
0
1
2
MV functions of single variable (cont)
• Universal Literals:
= negation
2
1
0
2
1
0
0
1
2
1
1
1
0
2
2
0
= wire
2
0
1
2
1
2
Multiple-Valued Logic
• Let us start with an
example that will help
to understand,
Suppose that we have the
following table, and
we need to build a
circuit with MV-Gates,
(MAX & MIN).
As we can see, this is
ternary logic.
ab c 0
00 2
01
-
02 1,2
1
2
-
2
2
0,2
1,2
0,1
10
2
2
-
11
2
2
-
12
0
0
0
20
1
2
2
21
-
2
2
22
0
0
-
ab c 0
00 2
1
2
2
2
01
-
-
0,2
02
1
1
0,1
10
2
2
-
a0,1 b0,1
b0,1 c1,2
11
2
2
-
12
0
0
0
20
1
2
2
a0,1 b0,1 + b0,1 c1,2
21
-
2
2
“Covering 2’s in the
22
0
0
-
map”
ab c 0
00 -
1
-
2
-
a0
01
-
-
-
02
1
1
1
10
-
-
-
11
-
-
-
12
0
0
0
20
1
-
-
21
-
-
-
22
0
0
-
b0,1
1.a0,1 +1.b0,1
“Covering 1’s in the map”
MVL Circuits
MAX-gate
MIN-gate
SOP = a0,1 b0,1 + b0,1 c1,2+ 1.a0,1
a
b
c
0,1
+1.b0,1
Min
0,1
Min
1,2
Max
Min
1
Min
1
f
Example of Application of logic with MV inputs and binary
outputs to minimize area of custom PLA with decoders.
• Pair of binary variables corresponds to quaternary variable X
• a’+b’=X012
0 1
• a’+b=X013
ab
a + b’ = X023
0
a + b = X123
1
0
1
2
3
(a + b’) *(a’+b)= X023 * X013
Thus equivalence can be realized by single column in
PLA with input decoders instead of two columns in
standard PLA
Multiple Valued Logic
• Currently Studied for Logic Circuits with More
Than 2 Logic States
– Intel Flash Memory – Multiple Floating Gate
Charge Levels – 2,3 bits per Transistor
http://www.ee.pdx.edu/~mperkows/ISMVL/flash.html
• Techniques for Manipulation Applied to Multioutput Functions
– Characteristic Equation
– Positional Cube Notation (PCN) Extensions
MVI Functions
• Each Input can have Value in Set {0, 1, 2, ..., pi-1}
F :{0,1,..., pi 1}  {0,1, X }
• MVI Functions
• X is p-valued variable
• literal over X corresponds to subset of values
of S  {0, 1, ... , p-1} denoted by XS
MVL Literals
• Each Variable can have Value in Set {0, 1, 2, ..., pi-1}
• X is a p-valued variable
• MVL Literal is Denoted as X{j} Where j is the Logic
Value
• Empty Literal: X{}
• Full Literal has Values S={0, 1, 2, …, p-1}
X{0,1,…,p-1} Equivalent to Don’t Care
MVL Example
• MVI Function with 2 Inputs X, Y
– X is binary valued {0, 1}
– Y is ternary valued {0, 1, 2}
– n=2 pX=2 pY=3
• Function is TRUE if:
–
–
–
–
X=1 and Y= 0 or 1
Y=2
SOP form is:
F = X{1}Y{0,1} + X{0,1}Y{2}
• Literal
X{0,1}
F
is Full, So it is Don’t Care
– implicant is
– minterm is X {1}Y{0}
– prime implicants are X{1} and Y{2}
X{1}
Y{0,1}
Y
X
0
1
0
1
1
1
2
1
1
MVL to
encode
binary logic
Standard PLA
PLA with decoders
X012
a
b
c
d
X013
X023
x
x
x
X123
Y012
Y013
x
Y023
Y123
x
x
x
x
decoders
T1= (a’  b) (c  d)
T2 = (a’ + b’) (c’ + d)
Z=T1+T2
PLA with decoders
• Such PLAs can have much smaller area
thans to more powerful functions realized in
columns
• The area of decoders on inputs is negligible
for large PLAs
• Multi-valued logic is used to minimize mvinput, binary-output functions with capital
letter inputs X,Y,Z,etc.
Multi-output Binary Function
• Consider
f 0 ( x, y , z )  x z  x y  x z
x
y
z
f1 ( x, y, z)  z  x y
x
0
0
0
0
1
1
1
1
y
0
0
1
1
0
0
1
1
z
0
1
0
1
0
1
0
1
f0
1
1
1
0
0
1
0
1
f1
0
1
1
1
0
1
0
1
f0
f1
Multi-output Binary Function
• Consider f 0 ( x, y, z )  x z  x y  x z
f1 ( x, y, z)  z  x y
x
y
z
f0
f1
x
0
0
0
0
1
1
1
1
y
0
0
1
1
0
0
1
1
z
0
1
0
1
0
1
0
1
f0
1
1
1
0
0
1
0
1
f1
0
1
1
1
0
1
0
1
Characteristic
Equation
W
x
y
z
F
x
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
y
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
z
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
W
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
F
1
0
1
1
1
1
0
1
0
0
1
1
0
0
1
1
Characteristic
Equation
Characteristic Equation
Sum of Minterms
F  x{0} y{0} z{0}W {0}  x{0} y{0} z{1}W {0}
 x{0} y{0} z{1}W {1}  x{0} y{1} z{0}W {0}
 x{0} y{1} z{0}W {1}  x{0} y{1} z{1}W {1}
 x{1} y{0} z{1}W {0}  x{1} y{0} z{1}W {1}
 x{1} y{1} z{1}W {0}  x{1} y{1} z{1}W {1}
x
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
y
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
z
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
W
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
F
1
0
1
1
1
1
0
1
0
0
1
1
0
0
1
1
Positional Cube Notation (PCN) for MVL
Functions
 00
• Binary Variables, {0,1},
Represented by 2-bit Fields
0 10
1 01
* 11
• MV Variables, {0,1,…,p-1}, Represented by p-bit Fields
• BV Don’t Care is 11
• MV Don’t Care is 111…1
• MV Literal or Cube is Denoted by C()
PCN for MVL Example
F  X {1}Y {0,1}  X {0,1}Y {2}
X
01
11
Y
110
001
• Positional Cube Corresponding to X{1} is C(X{1})
C ( X )  01 111
{1}
• Since Y{0,1,2} is Don’t Care
PCN for MVI-BO Example
z
f1  ab  ab
f 2  ab
f3  ab  ab
f (a, b); f  ( f1 , f 2 , f 3 )
a
b
f1 f2 f3
a b
10
10
100
a b
10
01
001
a b
01
10
001
ab
01
01
110
• View This as a SOP of MVI Function:
F  f  a{0}b{0} z{0}  a{0}b{1} z{2}  a{1}b{0} z{2}  a{1}b{1} z{0,1}
• F is the Characteristic Equation
List Oriented Manipulation
• Size of Literal = Cardinality of Logic Value Set
x{0,2}  size = 2
• Size of Implicant (Cube, Product Term) = Integer
Product of Sizes of Literals in Cube
• Size of Binary Minterm = 1  Implicant of Unit Size
EXAMPLE f (x1,x2,x3,x4,x5,x6)
implicant  x1 x3 x4  x1{1} x3{1} x4{0} x2{0,1} x5{0,1} x6{0,1}
size  111 2  2  2  01 01 10 11 11 11  8
# Don ' t Cares  3 ( x2 , x5 , x6 )
Logic Operations
• Consider Implicants as Sets
– Apply (, , , etc)
• Apply Bitwise Product, Sum, Complement to PCN
Representation
• Bitwise Operations on Positional Cubes May Have
Different Meaning than Corresponding Set Operations
EXAMPLE
Complement of Implicant  Complement of Positional Cube
MVL Logical Operations
• AND Operation – MIN - Set Intersection
• OR Operation – MAX - Set Union
• NOT Operation – Set Complement
EXAMPLE
X {0,1,3}Y {1,2}  X {1}Y {2}  X {1}Y {2}
X {0,1,3}Y {1,2}  X {1}Y {2,3}  X {0,1,3}Y {1,2,3}
p  5; X {0,1,3}  X {2,4}
MVL Number of Functions of 1 Variable
p
2
3
4
5
6
7
8
p
p
4
27
256
3125
46656
823543
16777216
Example of
MV function
minimization
Cube Merging
•
Basic Operation – OR of Two Cubes
•
MVL Operation – MAX is Union of Two Cubes
EXAMPLE
 = 1 {0,1} 0 1
 = 0 {0,1} 0 1
Merge  and  into 
 = {0,1} {0,1}0 1
a c d  ac d c d (a  a )c d
a{1}b{0,1}c{0}d {1}  a{0}b{0,1}c{0}d {1}
 (b
{0,1} {0}
{1}
c d )(a
{1}
 a{0,1}b{0,1}c{0}d {1}
a )
{0}
Multi-Output Minimization Example
X1
0
0
0
0
1
1
1
1
Input
X2
0
0
1
1
0
0
1
1
X3
0
1
0
1
0
1
0
1
Output
f0 f1 f2
0 1 1
0 0 1
0 0 0
0 0 1
0 0 0
1 1 0
1 0 0
1 0 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
X1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
X2
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
X3
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
X4
0
1
2
0
1
2
0
1
2
0
1
2
0
1
2
0
1
2
0
1
2
0
1
2
F
0
1
1
0
0
1
0
0
0
0
0
1
0
0
0
1
1
0
1
0
0
1
0
0
Minimization Example (cont)
Sum of Minterms (Fig. 10.7 PLA Implementation)
F  X1 X 2 X 3 X 4  X1 X 2 X 3 X 4
{0}
{0}
{0}
{1}
{0}
{0}
{0}
{2}
 X1 X 2 X 3 X 4
{2}
 X1 X 2 X 3 X 4
 X1 X 2 X 3 X 4
{0}
 X1 X 2 X 3 X 4
 X1 X 2 X 3 X 4
 X1 X 2 X 3 X 4
{0}
{1}
{1}
{0}
{0}
{1}
{1}
{1}
{0}
{0}
{0}
{1}
{1}
{1}
{0}
{1}
{2}
{1}
{1}
{1}
{1}
{0}
Merging
• Merge 1st and 2nd
• Merge 3rd and 4th
• Merge 5th and 6th
• Merge 7th and 8th
F  X1 X 2 X 3 X 4
{0}
{0}
{0}
{1,2}
 X1 X 2 X 3 X 4
{1}
{0}
{1}
{0,1}
 X1 X 2
{0}
{0,1}
{1}
 X1 X 2 X 3
{1}
{1}
{2}
X3 X4
{0,1}
{0}
X4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
X1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
X2
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
X3
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
X4
0
1
2
0
1
2
0
1
2
0
1
2
0
1
2
0
1
2
0
1
2
0
1
2
F
0
1
1
0
0
1
0
0
0
0
0
1
0
0
0
1
1
0
1
0
0
1
0
0
Minimization Example (cont)
F  X1 X 2 X 3 X 4
{0}
{0}
{0}
{1,2}
 X1 X 2 X 3 X 4
{1}
{0}
{1}
{0,1}
 X1 X 2
{0}
{0,1}
{1}
 X1 X 2 X 3
{1}
{1}
{2}
X3 X4
{0,1}
{0}
X4
Multi-Output Function Using of Multi-Output Prime Implicants
(Fig. 10.8 PLA Implementation)
f0  X1 X 2 X 3  X1 X 2
f1  X 1 X 2 X 3  X 1 X 2 X 3
f2  X1 X 2 X 3  X1 X 2
History
again
Why we need Multiple-Valued logic?
• In new technologies the most delay and power
occurs in the connections between gates.
• When designing a function using Multiple-Valued
Logic, we need less gates, which implies less
number of connections, then less delay.
• Same is true in case of software (program)
realization of logic
• Also, most the natural variables like color, is
multi-valued, so it is better to use multi-valued logic
to realize it instead of coding it into binary.
• In multi-valued logic, the binary AND
gate is replaced by MIN gate, and OR by
MAX
• But, AND can be also replaced by
arithmetic multiplication, or modulo
multiplication, or Galois multiplication
• OR can be also replaced by modulo
addition, or by Galois addition, or by
Boolean Ring addition, or by…..
• Finally, the number of values in infinite
• This way we get Lukasiewicz logic, fuzzy
logic, possibilistic logic, and so on…
• Continuous logics
• There are very many ways of creating gates in
MVL
• They have different mathematical properties
• They have very different costs in various
technologies
• The values and operators can describe time, moral
values, energy, interestingness, utility,
emotions…….
Mathematical, logical, system science,
or psychological/ methodological/
philosophical foundations
• Functional completeness theory studies the
construction of logical functions from a set of
primitives and enumeration of bases.
• The problems which are investigated include:
– classification of functions
– enumeration of bases of a closed subset of the set of
all k-valued logical functions
– study of particular kinds of functions (monotone,
symmetric, predicate, etc.) in multi-valued logics.
Are we sure that Lukasiewicz
was the first human who had
these ideas?
• Some Chinese philosophers claim that the
Buddhist logic, invented Before Christ Era,
was very similar to fuzzy logic
• Raymon Lullus (Ramon Llull) invented
many concepts that were hundreds years
ahead of his time
Raymon Lullus, 1235-1316 (probably)
• Creator of “Cartesian
Product”
• Creator of binary
counting system
• Creator of multivalued logic and
counting system
• Creator of the concept
of logic computer
Lotfi Zadeh (1921- )
• Father of Fuzzy
Logic
• Professor of
University of
California in
Berkeley
• First paper on fuzzy
logic published in
1956
Continuous
Logic
Continuous Logic
• From two values to many values to infinite number of
values
–
–
–
–
–
–
–
Fuzzy logic (Lotfi Zadeh),
Lukasiewicz logic,
Probabilistic logic,
Possibilistic logic,
Arithmetic logic,
Complex and Quaternion logic,
other continuous logics
• Find now applications in software and in hardware
• Are studied now outside the area of MV logic, but
historically belong to it.
Example:Arithmetic Logic
AB = A+B - A*B
Logic sum
We express logic operators by
arithmetic operators
Arithmetic sum
A=0.5 B=0.5 then result = 0.5+0.50.5*0.5=1-0.25=0.75
1-(1-A)(1-B)=1-(1-A-B+AB)=A+B-AB
This corresponds
to probabilistic
reasoning
Example:Arithmetic Logic
A B = A+B - 2*A*B
Logic exor
Arithmetic sum
A=0.5 B=0.5 then result = 0.5+0.52*0.5*0.5=1-0.5=0.5
We express logic
operators by arithmetic
operators
Various operators can be
defined to model certain
reasonings and because
their hardware realization
is simple
A B = A’B + AB’=(1-A)B+A(1-B)-(1-A)B(1-B)A=B-AB+AAB-AB(1-A)(1-B)=A+B-2AB-AB(1-A-B+AB)
In this definition, the same results for
natural numbers 0 and 1, but slightly
different for A=B=0.5
Check it, define
other operators of
similar properties.
Functional Representations
in Logic Synthesis
• New representations aim at more compact
representation of discrete data that allows:
– less memory space,
– smaller processing time.
• Data can be functions, relations, sets of functions
and sets of relations.
• Result of logic synthesis is a computer program for
a robot
• Logic Synthesis = Automatic Program Synthesis
• Good synthesis = better program (smaller, faster,
more reliable - noise, generalization)
• Examples of representations :
1. Cube Representation and the corresponding
Cube operations (Cube Calculus).
2. Decision Diagram (DD) Representation and the
corresponding DD operations.
3. Labeled Rough Partitions encoded with BDDs.
• Cube Representations :
1-a. Graphical Cube Representations of
Multi-Valued Input Binary Output.
cd
ab
00
01
02
10
11
12
20
21
22
00 01 02 10 11 12 20 21 22
1
0
0
1
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Cube
• 1-b. Expression (Flattened Form)
Representation of Cubes of MultiValued Input Binary Output .
For the previous example :F = 1.a0b0c0d0 + 1.a0b0c0d1 + 1.a0b0c1d0 +
1.a0b0c1d1 + 1.a1b0c0d0 + 1.a1b0c0d1 +
1.a1b0c1d0 + 1.a1b0c1d1
= 1 . a 0,1 b0c 0,1 d 0,1
Tabular Representation
a
b
f
g
0
1
0,2
0,1
1
0
_
0,2
2
0
2
3
2
1
0
1
1,2
1,2
0
2
Cube#
Functions and Relations are just mappings
• To recognize faces we obtain the following
tabular representation :Input Features
Output is
a relation
due to the imprecise
measurements of S
Person
N
H
M
S
John 1
1
1
1,2
Peter 2
0
1
0,1
Cubes Philip 0
1
0
1,2
0
2
2
Ken
2
ab c 0
00 0,1
1
2
1
1,2
Multi-valued Logic
To get it’s Decision Diagrams, we
follow these steps.
01
1
0,1
2
02
1
0,1
2
10
11
0
0
2
0
Step 1: Expand the function with
respect to variable “a”,”b” and “c”.
12
1,2
1,2 0,2
20
-
-
Expand the function with respect to
variable ‘a’ first.
f
21
22
2
0
2
2
0
2
0
a
0
2
1
b\c
0
1
2
b\c
0
1
2
b\c
0
1
2
0
0,1
1
1,2
0
0
-
-
0
-
-
0
1
1
0,1
2
1
0
2
0
1
2
2
2
2
1
0,1
2
2
1,2
1,2
0,2
2
0
2
0
Multi-valued Logic
When a=0, expand the function with respect to ‘b’ and ‘c’.
b=
b\c
0
1
2
0
0,1
1
1,2
1
1
0,1
2
2
1
0,1
2
0
C
Because this
group can
be 1, the 0
can be ignored
0
0,1
1
1
1
2
1,2
1
C
0
1
2
1
0,1
0 1
1
0,1
2
2
C
2
2
0
1
1
0,1
0 1
1
0,1
2
2
2
2
f equals ‘1’ here no matter if c is 0, 1 or 2, so it terminals at 1.
Multi-valued Logic
a=1
b=
b\c
0
1
2
0
0
-
-
1
0
2
0
2
1,2
1,2
0,2
0
C
0
0
1
-
2
-
1
C
0
0
0
0
0
2
1
2
2
0
1
2
C
0
1,2
1
1,2
2
0
2
2
0,2
Multi-valued Logic
a=2
b=
b\c
0
1
2
0
-
-
0
1
2
2
2
2
0
2
0
0
C
0
-
1
-
0
2
0
1
C
0
2
2
2
1
2
2
2
C
0
0
1
2
2
0
0 1 2
0 2
0
Multi-valued Logic
Step 2: Draw the Decision Tree
f
a
1
0
b
1 2
0
1
1
c
0
1 2
1
b
0 1
0
c
c
2
0
1
2
1
2
1
Choice done
for
simplification
2
2
0
b
1
2
0
2
0 1
2
0 2 0
2
c
0
1 2
0 2 0
Multi-valued Logic
Step 3: Combine the same terminals to get Decision Diagram
f
a
0
2
1
b
1,2
b
0
0
b
1
2
c
0 2 1
c
2
0,2
1
1
0,1
0
1
2
FUTURE
RESEARCH
AREAS AND
ANALOGIES
First Extension from Binary
Binary Logic ------------ MV Logic
And Gate
----------------------- MIN gate
Or Gate
-------------------------- MAX gate
Inverter
-------------------------- Literal
Post, generalized Post
or Universal
This is standard, many published results, both
two-level and multi-level, complete system
Second Extension from Binary
Binary Logic ------------ MV Logic
And Gate
<---------------------
EXOR Gate <--------------------
Inverter
Galois Multiplication gate
Galois Addition gate
<------------------------ Power of variable
This system was introduced by Pradhan and Hurst,
few papers have been published, no software,
most is two-level logic
Another very recent extension
Binary Logic ------------ MV Logic
And Gate
------------------- MIN gate
Exor Gate
-----------------------
Inverter
MODSUM gate
----------------------- Literals
Perhaps universal literals
will increase the power, not
investigated yet
This system was introduced by Muzio and Dueck
and independently by Elena Dubrova in her Ph.D.
Two papers have been published. Recent interest.
Problems
to think about
1. What is multivalued logic.
2. Can multi-valued logic be used to synthesize binary
circuits?
3. Ternary logic, prime implicants and covering.
4. Continuous and Arithmetic logic
5. Multi-valued decision trees and diagrams.
6. Types of MV literals.
7. Types of MV logic.
8. PLA with decoders and how it relates to MV logic.