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A 975 to 1960 MHz, Fast-Locking
Fractional-N Synthesizer with
Adaptive Bandwidth Control and
4/4.5 Prescaler for Digital TV Tuners
Lei Lu1,2, Zhichao Gong1,2, Youchun Liao2,
Hao Min1, Zhangwen Tang1
1 Fudan
University, Shanghai, China
2 Ratio Microelectronics, Shanghai, China
Outline
• Motivation
• Synthesizer Architecture
• Proposed Techniques
¾ Adaptive Bandwidth Control
¾ Division-Ratio-Based AFC Technique
¾ 4/4.5 Prescaler
• Measurement Results
• Conclusions
© 2009 IEEE International Solid-State Circuits Conference © 2009 IEEE
2
Motivation
• Digital TV tuners need a wideband frequency
synthesizer such as DVB-T
• Loop bandwidth changes greatly during a wide
frequency range
• Wideband VCO needs AFC to select the subband automatically
• Low phase noise and low phase error are
required in the receiver
© 2009 IEEE International Solid-State Circuits Conference © 2009 IEEE
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Pros & Cons
• Advantages
¾ Loop bandwidth is adaptively controlled
¾ Residual fractional error is reduced and VCO clock is
counted directly
¾ Lower phase noise due to the 4/4.5 prescaler
¾ Measured low phase noise, low phase error and fast
locking time
• Disadvantages
¾ The 4/4.5 prescaler leads to a little bit higher power
¾ The fractional spur is high when fractional modulus is
close to 0 or 1
© 2009 IEEE International Solid-State Circuits Conference © 2009 IEEE
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Synthesizer Block Diagram
8
AFC
8
4 MSBs
C2
s1 R1
C1/2
Vref
fref
25MHz PFD
s1
.F[22:0]
23
23
Dithering
s1
Vref
C3
C3
R1
C2
Double-edge
Retiming
3rd-order
DSM
N[7:0]+.F[23]
3
fout
0.975~
1.96GHz
s1
R3
s2
LPF
Differential
CP
s2
R3
VCO
P/S
Counter
Prescaler
4/4.5
9
9
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Loop Bandwidth
I CP K VCO f ref
R1C1
Loop bandwidth =
⋅
C1 + C2 + C3
2πf vco
• KVCO and fvco are two factors affecting loop
bandwidth
• Maintain loop bandwidth
¾ Output frequency fvco varies greatly across the wide
range, but ICP also is tuned to compensate fvco
¾ KVCO is maintained
¾ Then the loop bandwidth is adaptively controlled
across the whole frequency range
© 2009 IEEE International Solid-State Circuits Conference © 2009 IEEE
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Simplified LC-tank of Multiband VCO
• Switched capacitors and
switched varactors are both
adjusted simultaneously
with different values of units
to maintain both KVCO and
band steps
• α1 ~ α255 and β1 ~ β255 are
programmed coefficients
• See [Lu, et al., IEEE RFIC
Symp., 2008]
osc+
osc-
f
f
1
en1
f
255
f
1
en255
f
255
f
ctrl
v
v
en1
B
1
ctrl
v
B
255
1
en255
v
v
ctrl
255
v
LC
© 2009 IEEE International Solid-State Circuits Conference © 2009 IEEE
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Multiband VCO Calibration Using AFC
• The purpose of AFC is to select the sub-band of
VCO whose center frequency is closest to the
target frequency automatically
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Conventional AFC
• Frequency comparison by counter
• Selected fvco is closest to N*fref, not (N+.F)*fref
¾ Residual fractional error .F*fref is generated
ref
div
ref
vco
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Division-Ratio-Based AFC
• Ndec is decoded from the division ratio N.Fdec,
¾ Residual fractional error is reduced to 2-4*fref
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Direct Count of VCO Clock
Ncntr
vco
cntr
cntr
dec
dec
dec
ref
AFC
ref
vco
cntr
Counter
Ncntr
cntr
cntr
cntr
cntr
• High-speed asynchronous divide-by-2 counters
are used to count the VCO clock directly
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Divider Chain
• N=4, P=9~20, S=0~7, the overall division ratio
without DSM is N*P+0.5*S=36~83.5 (step=0.5)
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Behavioral Simulations of Phase Noise
-70
step size of 1
CP
-90
Phase Noise (dBc/Hz)
Phase Noise (dBc/Hz)
• Comparison between step size of 1 and step size of 0.5
• Similar phenomenon in [Yang, et. al., IEEE JSSC, Nov.
2006]
total
-110
-130
Ref.
Div
VCO
LPF
-150 2
10
3
DSM
4
5
6
7
10 10 10 10 10
Frequency Offset (Hz)
-70
step size of 0.5
CP
-90
total
4.5dB
reduction
-110
-130
Ref.
Div
VCO
LPF
-150 2
10
3
DSM
4
5
6
7
10 10 10 10 10
Frequency Offset (Hz)
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Schematic of 4/4.5 Prescaler
• Works at both rising edge and falling edge
• In divide-by-4.5 mode when mod is high
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Timing Chart
• Divide-by-4.5 mode
• Q8 lags half a period behind Q5
vco
9
9
9
9
4.5
4.5
4.5
4.5
4.5
4.5
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Double-Edge-Triggered Retiming Circuit
• Comparison between single and double edge
¾ single-edge-triggered retiming
¾ double-edge-triggered retiming
div
vco
div
vco
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Other Circuit Details
• VCO
¾ Power supply from LDO
¾ Complementary cross-coupled transistors
¾ Two tail inductors to lower the phase noise
• Charge Pump
¾ Differentially configured
¾ Rail-to-rail CMFB
• Loop Filter
¾ On-chip MIM capacitor and high-res poly resistor
• DSM & P/S Counter
¾ Programmed using Verilog language
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Die Micrograph
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VCO Gains and Band Steps
12
9
11
KVCO (MHz/V)
10
7
9
8
6
7
5
6
4
5
4
0
Band Step (MHz)
8
50
100
150
200
Sub-band (0~255)
3
250
© 2009 IEEE International Solid-State Circuits Conference © 2009 IEEE
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2.1
160
1.9
140
1.7
120
1.5
100
1.3
80
1.1
60
0.9
40
0.7
20
0.5
1
1.2
1.4
1.6
1.8
Output Frequency (GHz)
Loop Bandwidth (kHz)
Phase Error (Deg)
Loop Bandwidth & Phase Error
0
2
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Phase Noise
• The division ratio is 53.56
Target
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Frequency (GHz) Frequency (GHz)
Locking Time
1.5
1.216
1.214
1.212
1.21
5
1.4
1.3
15
25
35
1.2
1.1
1.4
1.3
1.2
1.1
1
start
0
10
20
30
Time (μs)
40
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Performance Summary
Technology
Die Area
0.18 μm
CMOS
1.58 *1
mm2
Supply
Voltage
1.8 V
Current
14 mA
Loop
Bandwidth
Frequency
Resolution
83 to 102
kHz
< 1.5 Hz
Reference
Frequency
25 MHz
Output
Frequency
0.975 to 1.96
GHz (67.1%)
Phase Noise
(dBc/Hz)
Phase Error
(rms)
-91@ 3kHz
-123@1 MHz
0.6° to 1.05°
20 μs (6.4 μs
Locking Time
for AFC)
© 2009 IEEE International Solid-State Circuits Conference © 2009 IEEE
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Conclusions
• Have demonstrated loop bandwidth is
maintained in calibration-enable mode
• Have obtained 20 μs locking time and residual
fractional error is reduced for AFC
• Have designed a 4/4.5 prescaler to obtain lower
output phase noise contributed from DSM
• Have demonstrated low phase noise and low
phase error performance across the whole
wideband tuning range
© 2009 IEEE International Solid-State Circuits Conference © 2009 IEEE
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