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International Journal of Emerging Technology and Advanced Engineering Website: www.ijetae.com (ISSN 2250-2459, ISO 9001:2008 Certified Journal, Volume 4, Issue 6, June 2014) Reduced Surface Field Technology For LDMOS: A Review Sunitha HD1, Keshaveni N2 1 Assistant Professor, Department of ECE, EPCET, Bangalore Professor,Department of ECE,KVG College of Engineering, Sullia 2 Abstract-- RESURF (Reduced Surface Field) technology is the frequently used method to design a high voltage lateral devices with high break down voltage and low on-resistance. Devices working on higher voltages require thick and low doped epitaxial layer, which makes them difficult to get integrated with low voltage circuitry. Because of high resistivity, the on- resistance of the epitaxial layer is large. RESURF concept gives the best tradeoff between the break down voltage and on-resistance of lateral devices. This paper gives a technical review of RESURF concept used for LDMOS and also discusses about multiple RESURF technology. II. INTRODUCTION TO RESURF Appels and Vaes proposed the first RESURF concept in the year 1979[1]. The frequently used method to design high voltage devices on thin epitaxial layer with low onresistance is the RESURF. The RESURF concept [2] gives the best trade-off between the breakdown voltage and the on-resistance of lateral devices .It has been successfully used for lateral high voltage devices such as diodes and LDMOS transistors for 20-1200V. This technology provides an efficient way to integrate high voltage devices with low voltage circuitry [2]. Devices working on higher voltage require thick and low doped epitaxial layer, which makes them difficult to get integrated with low voltage circuitry. Because of high resistivity epi layer, onresistance is large. The traditional RESURF structure is constructed by a lateral p+/ n diode that defines the onresistance characteristics of the device and a vertical p/ n diode that supports a charge depletion region enabling high BV. Figure 1 defines the on-resistance characteristics of the device and a vertical diode which supports a space charge depletion region enabling increased break down voltage. The lateral break down voltage of this structure depends on net charge of the drift region. The maximum BV is determined by the BV of the vertical diode (p-substrate/nepitaxial). Keywords- Break down voltage (BV), LDMOS (Laterally Diffused Metal Oxide Semiconductor), on-resistance(Ron), RESURF. I. INTRODUCTION High power devices are the common building blocks in RF and microwave communication systems. Mobile phones, base stations and satellite systems all depend on such high power amplifiers. CMOS technology has been widely used in RF circuits for low cost and easy integration of both logic circuits and RF circuits on the same chip. For the large signal capability requirement in power amplifier, high break down voltage and reliable transistors are preferred which is a big challenge for CMOS technology. LDMOS device becomes a good candidate for power amplifier circuits with faster switching speed, high breakdown voltage and low on resistance .LDMOS uses RESURF technology to achieve high break down voltage and low on resistance. The break down voltage of LDMOS can be improved by increasing the drift length(Ld). However this also increases the on resistance as per the equation Ron α Ld2 /Qepi (1) Qepi in equation (1) represents the doping dose of the epitaxial layer. By increasing the doping dose of the epitaxial layer the BV can be increased and Ron can be decreased. Fig 1-Lateral RESURF structure at full depletion(google) Net charge in this region is inversely proportional to the drift region resistance. Because of vertical junction of RESURF structure a second electric field peak forms at cathode end of the device. 173 International Journal of Emerging Technology and Advanced Engineering Website: www.ijetae.com (ISSN 2250-2459, ISO 9001:2008 Certified Journal, Volume 4, Issue 6, June 2014) Lateral improvement was obtained by adding lateral gradation in the RESURF. Stepping field plates[5](fig 4a) were applied for enhanced depletion at the source side end on thick 2-3μm oxide for reduced high fields at the end of field plate leading to LDMOS up to 1200V. A local buried p-layer [6](fig 4b) provides a graded RESURF pinching from the substrate side. An epitaxial dose of 2.1*1012/cm2was allowed that resulted in Ron*A=5.6Ωmm2 for 400V. Vertical improvement was achieved by using enhanced depletion by field plates or by vertically profiled layers allowing more charge. This resulted in double acting RESURF[5] with a p-layer on top of the n-layer for lower Ron and high voltage operation of RESURF devices. Fig 2- Electric field comparison at the surface(google) Figure 2 shows the electric field at the surface of the RESURF device. It assumes a parabolic form. This helps to reduce electric field at the surface of device during off. The basic properties of RESURF structures are determined by the p-substrate doping concentration, n-epilayer doping concentration (Nepi) and n-epi layer thickness (tnepi). An approximate net charge Qn of fig 1 is determined by Qn=Nepi * tnepi (2) The lateral electric field is reduced as the vertical space charge width extends and interacts with lateral junction space charge region allowing the lateral depletion width to effectively span a larger distance. For high break down voltage in RESURF structures, the n-epi region is to be fully depleted before the lateral electric field reaches a critical value. III. RESURF IN LDMOS The most important RESURF device is the LDMOS transistor used from 20V to 1200V. The epitaxial RESURF was first used for a 425V LDMOS with Ron of 9.4Ωmm2 [3-4]. Fig 4- Improved Resurf LDMOS (a) with stepped field plate;(b) with local buried p-layer;(c) double layer with dotted p-layer of double dose.[3] The top p-layer of an LDMOS must be interrupted to allow the current flow from surface inversion channel to the drift region(fig 4c). By doing this, devices upto 1200V have been realized with 2*10 12cm-2 n-layer dose and dose tolerance of +/-20% for 80% of BV max[7]. A continuous p-layer on top and a vertical link under the polysilicon gate between the sources like in VDMOS has been maintained resulting in 2.4*1012/cm-2for 880V. To prevent high side punch through a local n+ buried layer has been used. Fig 3-HV LDMOS-Epitaxial Resurf [5-6] The thicker RESURF layer allows for higher break down for bipolar and high side devices. RESURF dose can be controlled by a deep N-well implanted in lightly doped nepitaxy or directly into the p-substrate. Improvement was obtained in 2 ways: vertically and laterally. For the optimization of the BV and Ron many analytical models have been studied. Some first order equations are used to estimate the BV and specific Ron for the active area(Ron*A). 174 International Journal of Emerging Technology and Advanced Engineering Website: www.ijetae.com (ISSN 2250-2459, ISO 9001:2008 Certified Journal, Volume 4, Issue 6, June 2014) The n-/p- dope and thickness gives the maximum break down voltage vertically under the n+ contact. Lateral break down at shorter drift length is calculated by the integration of the lateral field having peaks at p+ and n+ regions and lower field in between. A constant average field of 1015V/μm is estimated. BV is dependent on drift length between body and drain. BV=Elat*Ldrift A better (Ron*A) at 800V[10] from 24(double RESURF) to 16Ωmm2 and 11 to 7Ωmm2 at 550v is obtained by using a dual path sandwich layer with intermediate p-layer. IV. MULTIPLE RESURF RESURF effect can also be achieved in multiple junction devices where an additional layer of opposite doping is incorporated in n-drift region. The epitaxial layer of a multiple RESURF LDMOS can be more heavily doping for same BV as compared with single RESURF LDMOS. Multiple RESURF LDMOS[11] provides a superior performance in the compromise of high BV and low Ron. Double RESURF LDMOS[11] helps to reduce Ron by about 50% lower than single RESURF LDMOS. (3) Figure 5 shows the measured examples for epitaxial RESURF LDMOS with various Ldrift and an effective Rsh of 4-5ohm/sq. Also (Ron*A) is proportional to BV2. Ron consists of channel , drift and spread resistance. At increasing Vds maximum current is limited by the current limiting JFET behavior of the drift region. Ron * A~Rsh………..(BV/Elat)2 (4) Recent investigations revealed some improved ( Ron*A) versus BV and improved ruggedness. Fig 6- cross section of double RESURF LDMOS[11] Figure 6 the shows structure of double RESURF LDMOS. P-type top layer (p-tl) is located on the surface of the drift region. It gives an excellent performance in the compromise of BV and Ron. One disadvantage is that the Ron increases drastically if the distance between p-tl and pwell is not kept large enough to avoid high JFET resistance. Further there may be charge sharing problems during LOCOS. Fig 5-Resurf LDMOS data for BV ,Ron*W versus Ldrift and Ron*A versus BV[2] A better on state BV[8] is provided by a graded drift dope, lower Ron at slightly lower off state BV. Improved ( Ron*A) at 760V from 33 to 26Ωmm2 is obtained[9] by a more elaborated stepped field plate with poly and2x metal with a narrow gap and HV stability is also improved. Fig 7- cross section of triple RESURF LDMOS[11] Figure 7 shows the structure of a triple RESURF LDMOS[11]. It has a p-type buried layer (p-bl) located in the drift region. Therefore it will not be affected by LOCOS. 175 International Journal of Emerging Technology and Advanced Engineering Website: www.ijetae.com (ISSN 2250-2459, ISO 9001:2008 Certified Journal, Volume 4, Issue 6, June 2014) The relationship between Ron and BV is shown in fig 9, which explains that, by changing Ld, p-tl length(Xtl) and Xbl under the precondition that BV is linearly proportional to Ld. The lower slope explains that the triple RESURF LDMOS promises a better performance of a lower Ron in a wide range of BV. BV ranging from 300 t0 700V can be obtained by altering Ld and Xbl. V. CONCLUSION High BV and low Ron makes the RESURF devices desirable for use in HVIC technologies. RESURF devices suffer from the unique requirement of charge control. Variations on charge control may lead to a lower BV. BV modulation and charge balance sensitivity are especially critical for double RESURF LDMOS. A triple RESURF LDMOS has achieved on resistance of 100mΩ-cm2 and BV of 700V where as it is 30% lesser in double RESURF LDMOS. To overcome the sensitivity of the BV to variations in the vertical dimensions strict process tolerance control is required during diffusion and implantation process. Fig 8- relationship b/w BV and Nepi [11] Figure 8 shows the relationship between BV and N-epi doping concentration with p-tl and p-bl dose variations for double and triple RESURF LDMOS. At any given p-tl(Qtl) or p-bl(Qbl), the BV has a bell shaped pattern with a plateau while doping concentration on N-epi varies comparatively with double RESURF LDMOS, Triple RESURF LDMOS allows a larger Qepi. Since p-bl is located in the drift region there are 3 parallel p/n junctions in the vertical direction. When the drain electrode is applied with high voltage 2 junctions close to p-bl will deplete it vertically from top and bottom. Compared to double RESURF LDMOS with only one pn junction close to p-tl in the vertical direction, it can deplete more completely and value of Qepi can be increased. Therefore a better performance of Ron can be achieved. The main problem occurring in triple RESURF LDMOS is that the BV is very sensitive to the vertical dimensions of the p-bl. If the implantation depth or diffusion thickness of the buried layer fluctuates slightly from the optimal value the block characteristics will deteriorate and this requires high process tolerance. REFERENCES [1] J. A. Appels and H. M. J. Vaes, ``HV Thin Layer Devices (RESURF Devices),'' in Proc. Intl. Electron Devices Meeting, pp. 238-241, 1979 [2] A. W. Ludikhuize, ``A Review of RESURF [3] A.W.Ludikhuize, “Performance and Innovative trends in RESURF Technology”, Solid State Device Research conference, 2001, pp 3544. [4] K.Awane et al, “HV DSA MOS for EL-display”, ISSCC-78 p.224225. [5] A.Ludikhuize, “HV DMOS and PMOS in analog IC’s” , IEDM80,p.81-84 [6] E.Stupp,et al, “Low-R 400V LDMOS” ,IEDM-81,p.426 [7] A.Ludikhuize, “ A versatile 700/1200V IC process”, IEEE-TED38(1991),p.1582-1589 [8] P.Hower et al, “Drift gradient” , ISPSD-2000,p.345-348 [9] N.Fujishima et al, F-plate, ISPSD-01,p.255-258 [10] D.Disney et al, Dual path, ISPSD-01,p.399-402 [11] Yin Shan et al , “ Design of 700V triple RESURF LDMOS with low on resistance”, 2011, Journal of Semiconductors, vol 32, Fig 9- Relationship b/w Ron and BV[11] 176