Download IR`s Rugged HVICs

• Negative VS no-flip-glitch compared with
state-of-the-art gate driver IC
• Negative Transient Safe Operating Area datasheet
specification
Improved Performance and Application-Specific
Features Simplify Motor Control Design
5. Redundacy in the number of reset pulses transmitted to the high-side
Leveraging years of experience as a leading supplier of high-voltage ICs (HVICs)
in a wide spectrum of high-voltage switching applications, IR has introduced two
families of high-voltage gate drivers for motor control applications using either
IGBTs or power MOSFETs.
The newly developed IR gate driver families for motor control feature:
• Ruggedness – capable of operating with large negative transient, without
failing even under extreme stresses such as hard short circuit of the inverter outputs
• Micro power consumption on high-side floating driver
• Enhanced integrated bootstrap diode to significantly ease power supply design
• Fully controlled timings – propagation delays and channel-to-channel matching
so tight that pulse width compensation is not required
From the simplest half bridge gate drivers (IRS260xD family) to application-specific
devices (IRS263xD), motor control designers can now select from a wide range of IR’s
HVICs to best suit their design needs.
3. Low voltage supply short failure detection and protection through zero vector insertion
2. DC Bus over-voltage detection and protection through zero vector insertion
Package
1. Integrated logic for fault dignostic (GND/PFC/DC Bus shunt over-current and VCC UVLO faults)
QFN, MLP
available
MLP available
4. Minimum VS voltage allowing full functionality
THE POWER MANAGEMENT LEADER
• Negative VS IQCC latch-up
robustness compared to competitors, G2 and G5-D version
• Negative VS no-flip-glitch compared with state-of-the-art gate driver IC
• Negative Transient Safe Operating Area datasheet specification
Robustness
Improvement
• Redundant
reset5
ProductSpecific
Improvement
• No-short-pulse input filter
• Turn-on/turn-off delay and deadtime matching between channels
• VS headroom4
• Reset dominance5
• Power on reset of all internal latched logic
Improvement
vs G2 Family
• GND shunt overcurrent protection
• Redundant reset5
• GND/PFC/
DC+ Shunt
over-current
protection
• DC bus
over-voltage
protection2
• Op-Amp for
GND shunt
• Integrated
fault
diagnostic
protocol1
• VCC short
protection3
• Integrated
Bootstrap
• Op-Amp for
GND shunt
• Integrated
bootstrap
• Integrated
bootstrap
• Integrated
bootstrap
• VCC & VBS
UVLO
• VCC & VBS
UVLO
• VCC & VBS
UVLO
• VCC & VBS
UVLO
• VCC & VBS
UVLO
• VCC & VBS
UVLO
• VCC & VBS
UVLO
For more information, call +(33) 1 64 86 49 53 or +49 6102 884 311 or visit us at www.irf.com
• Integrated bootstrap suitable for sinusoidal modulation
• Integrated bootstrap suitable for Trapezoidal
and Sinusoidal modulation
• Single input
(programmable
deadtime)
• Complementary
inputs
(programmable
deadtime)
• Independent
high- and lowside inputs
• GND shunt
over-current
protection
• GND/PFC/
DC+ Shunt
over-current
protection
• GND shunt
over-current
protection
ProductSpecific
Function
• GND shunt
over-current
protection
• GND shunt
over-current
protection
• GND shunt
over-current
protection
• GND shunt
over-current
protection
2 HB
2 HB
2H&L
6
6 +1
6
6
Driving
Channels
6
6
IRS26302D
6
IRS2607D
IR’s Rugged HVICs
IRS2330D
IRS2332D
IRS2330
IRS2332
IRS2336
Three-Phase
HVIC / MOTOR CONTROL
IRS2336D
IRS26310D
IRS26320
Single-Phase
IRS2608(4)D
IRS2609(4)D
IR’s Rugged HVICs
10230FS
Rugged Gate Drivers by Design
In a typical motor control application design, problems arise when undertaking
prototype validation tests. When checking for waveforms and voltages, unexpected
large negative voltage transients can typically appear. This situation is even worse
when trying short circuits tests that often result in an inverter catastrophic failure.
The key challenge is to design the HVIC in a way that these negative transients are
managed properly and that the driver can cope with them safely.
International Rectifier has introduced:
• A solid method to characterize and specify the HVIC
• A reliable and methodical solution to design negative VS rugged gate drivers
+VBUS
LD2
HO
VBUS
Q2
Control IC
VS Undershoot
LS2
VS
To Load
LD1
COM
LO
VS -COM
Q1
LS1
-VS
t
Load Return
Tolerant to Negative Transient Voltage
For more information, call +(33) 1 64 86 49 53 or +49 6102 884 311 or visit us at www.irf.com
10230FS
IR’s Rugged HVICs
Bootstrap diode
only when required
For proper operation, the device should be used within the recommended conditions. All voltage parameters are
absolute voltage referenced to VSO. The offset rating is tested with all suplies biased at 15V differential.
VB1,2,3
High-side floating supply voltage
VS1,2,3
Static high-side floating offset voltage
VSt1,2,3
Transient high-side floating offset voltage
VHO1,2,3
High-side floating outpt voltage
VCC
Low-side and logic fixed supply voltage
Min
Max
VS 1,2,3 + 10
VS 1,2,3 + 20
VSO-8 (Note1)
600
-50 (Note2)
600
VS 1,2,3
VB 1,2,3
10
20
VSS
Logic ground
-5
5
VLO1,2,3
Low-side output voltage
0
VCC
VIN
Logic input voltage (HIN 1,2,3; LIN 1,2,3 and ITRIP)
VSS
VSS +5
VFLT
Fault output voltage
VSS
VCC
VCAO
Operational amplifier output voltage
VSS
VSS +5
VCA-
Operational amplifier inverting input voltage
VSS
VSS +5
TA
Ambient temperature
-40
125
Units
˚C
IR has introduced a comprehensive and unique method for characterizing
and specifying gate driver capability to manage negative transient by
using the concept of Negative Transient Safe Operating Area (NTSOA).
The NTSOA is a region defined by a locus of points for the negative pulse’s
pulse-width and amplitude that can be safely managed by the driver.
The new IR gate drivers are found to be highly robust against short
circuits even when a negative transient extends well below the limits
defined by NTSOA. Passing both NTSOA and short circuit tests is a
requirement for IR’s new motor control gate drivers.
Negative Vs Transient SOA for IR gate drivers (@ VBS=15V)
In competitor comparison tests, IR’s gate drivers were found to
be the most rugged and reliable and the only gate driver capable of
withstanding the inverter’s hard short circuit test.
-10
Boosting Short Circuit Immunity
400
Time (ns)
500
600
NTSOA
-20
-30
VI (V)
In addition to NTSOA, each new part is tested in an
inverter assembly and stressed under inverter short circuit
operation. The inverter PCB is designed to replicate the
worst case parasitic conditions of a real inverter assembly
and the driver is tested for inverter output to ground short
circuit using a wide range of IGBT types and rated current.
This represents the worst case configuration to generate
severe negative transients on VS nodes.
More Rugged, More Reliable
300
-40
-50
-60
-70
-80
-90
Fig 2: Negative Transient Safe Operating Area
700
800
HIN
HIN
LIN
LIN
VB
900
Tested safe operating area
1000
0
-30
VS
200
100u
C1
HV1
+
COM
Time (nsec)
300
400
500
600
700
-10
R1
LO
100
-21
-20
HO
Bad
-26
Bad
-40
-50
Good
-50
-60
HIN is pulsed
LIN is inactive
V
Negative Transient Safe Operating Area
200
VCC
0
IGBT
Q1
CB
IGBT
Q2
• In transient operating conditions (Table 1, Note 2), in either normal or hard switching conditions, the capability for the driver to sustain the
large negative spikes occurring at each switching event is specified.
100
DB
VSS
In the DC operating condition (Table 1, Note 1) when the negative voltage is excessive and a transmission failure occurs, the IR gate driver
is designed such that the last information to be transmitted will be a reset (reset dominance). This guarantees the high-side will hold the off
state, thereby protecting the system against catastrophic failures.
IR gate drivers are 100% tested at wafer and final test level for the minimum Vs DC biasing condition as well as reset dominance functionality.
IR’s gate drivers are characterized to withstand the NTSOA limits by
means of dedicated test equipment. The gate driver works properly for any
negative pulse whose amplitude and pulse-width falls within
the white area indicated in Figure 2 . Pulses whose amplitude
are large enough to fall in the gray area might result in the
0
0
gate driver not working properly.
RB
C2
Note 1: Logic operational for VS of (VSO -8 V) to (VSO +600 V). Logic state held for VS of (VSO -8 V) to (VSO – VBS)
Note 2: Operational for transient negative VS of VSS - 50 V with a 50 ns pulse width.
Note 3: CAO input pin is internally clamped with a 5.2 V zener diode.
•
•
VCC
R2
-70
Competitor A
Competitor B
IRS2607D
-80
-90
Fig 3: Short circuit test setup
Fig 4: Negative vs transient event point of failure test comparison
Figure 4 plots the negative VS voltage at which the gate driver IC
destructively fails when subjected to negative VS events of varying
duration. During a 300nsec duration negative VS event, while competing
gate driver ICs will fail at a voltage of -21V (Competitor A) and -26V
(competitor B), IRS2607D will fail only at -50V, thus exhibiting nearly 2x
or higher negative VS capability.
where the long-off-times of the low-side switch and extended tri-state
conditions renders bootstrap circuit design generally difficult.
Competing parts typically require additional protection components
(such as clamping diode) to be added to limit the extent of negative
transient on VS pins resulting in higher cost, increased complexity and
possibly impacting the switching performance of the inverter itself.
Enhanced Integrated Bootstrap Functionality
Along with under-voltage lockout functionality provided by almost all
IR gate drivers, the new motor control-specific HVIC families feature
a very low quiescent current which enables using a bootstrap power
supply for even the most demanding applications such as trapezoidal
or six-step as well as other PWM modulation techniques requiring one
inverter leg to keep a high level for long periods.
In addition, to reduce the component count and make the design easier
and more reliable, the new family of motor control gate drivers feature
integrated bootstrap functionality implemented by means of an internal
high-voltage MOSFET whose biasing conditions are properly managed
to deliver current to the high-side circuit through the low-side supply
network, emulating the external high voltage bootstrap diode.
In particular, the IRS2607D’s bootstrap function has been designed
to accommodate the more complex trapezoidal modulation scheme,
High Fidelity in Power Motor Control
The new family of motor control-specific gate drivers from IR offer full
compatibility to 3.3V CMOS standards and integrate a new low distortion
input filter that guarantees precise pulse width transmission even at the
extremes of the filtering time while guaranteeing that too short pulses
do not reach the power section as they would not be long enough for
the inverter output to change state.
Three-phase gate drivers are also designed to accurately match
propagation delays among all six channels and are tested to guarantee
the input to output pulse width distortion (defined as difference between
input pulse-width and output pulse-width) to be lower than 75ns.
Application-Specific Features
The new IR HVIC families include gate driver ICs that have been tailored to
the final application. In addition to ruggedness and extreme fidelity, new
features have been included to create even more compact and robust
inverters. The IRS26302D, for example, is the first HVIC that includes
all type of over-current protection required in a modern brake+inverter
system or in a modern PFC+inverter system. The IRS26310D includes a
special zero vector braking function that can be extremely important
when assessing the safety level of a system with certification agencies.
Whenever a Permanent Magnet (PM) motor is driven in field weakening,
protection must already be integrated in the IRS26310D.
Advanced Input Filtering
EXAMPLE 1
Definiton
EXAMPLE 2
Symbol
6 inch wire to short
output to negative bus
Voltage
Table 1: Negative VS Ruggedness Specifications in IR HVIC Product Datasheets
IN
tFIL,IN
IN
OUT
IN
tFIL,IN
OUT
tFIL,IN
Small pulses to the gate of the
switches may cause inverter damage
OUT
IN
tFIL,IN
OUT
COMPETITOR’S HVIC
INTERNATIONAL RECTIFIER HVIC
IR’s Rugged HVICs
Bootstrap diode
only when required
For proper operation, the device should be used within the recommended conditions. All voltage parameters are
absolute voltage referenced to VSO. The offset rating is tested with all suplies biased at 15V differential.
VB1,2,3
High-side floating supply voltage
VS1,2,3
Static high-side floating offset voltage
VSt1,2,3
Transient high-side floating offset voltage
VHO1,2,3
High-side floating outpt voltage
VCC
Low-side and logic fixed supply voltage
Min
Max
VS 1,2,3 + 10
VS 1,2,3 + 20
VSO-8 (Note1)
600
-50 (Note2)
600
VS 1,2,3
VB 1,2,3
10
20
VSS
Logic ground
-5
5
VLO1,2,3
Low-side output voltage
0
VCC
VIN
Logic input voltage (HIN 1,2,3; LIN 1,2,3 and ITRIP)
VSS
VSS +5
VFLT
Fault output voltage
VSS
VCC
VCAO
Operational amplifier output voltage
VSS
VSS +5
VCA-
Operational amplifier inverting input voltage
VSS
VSS +5
TA
Ambient temperature
-40
125
Units
˚C
IR has introduced a comprehensive and unique method for characterizing
and specifying gate driver capability to manage negative transient by
using the concept of Negative Transient Safe Operating Area (NTSOA).
The NTSOA is a region defined by a locus of points for the negative pulse’s
pulse-width and amplitude that can be safely managed by the driver.
The new IR gate drivers are found to be highly robust against short
circuits even when a negative transient extends well below the limits
defined by NTSOA. Passing both NTSOA and short circuit tests is a
requirement for IR’s new motor control gate drivers.
Negative Vs Transient SOA for IR gate drivers (@ VBS=15V)
In competitor comparison tests, IR’s gate drivers were found to
be the most rugged and reliable and the only gate driver capable of
withstanding the inverter’s hard short circuit test.
-10
Boosting Short Circuit Immunity
400
Time (ns)
500
600
NTSOA
-20
-30
VI (V)
In addition to NTSOA, each new part is tested in an
inverter assembly and stressed under inverter short circuit
operation. The inverter PCB is designed to replicate the
worst case parasitic conditions of a real inverter assembly
and the driver is tested for inverter output to ground short
circuit using a wide range of IGBT types and rated current.
This represents the worst case configuration to generate
severe negative transients on VS nodes.
More Rugged, More Reliable
300
-40
-50
-60
-70
-80
-90
Fig 2: Negative Transient Safe Operating Area
700
800
HIN
HIN
LIN
LIN
VB
900
Tested safe operating area
1000
0
-30
VS
200
100u
C1
HV1
+
COM
Time (nsec)
300
400
500
600
700
-10
R1
LO
100
-21
-20
HO
Bad
-26
Bad
-40
-50
Good
-50
-60
HIN is pulsed
LIN is inactive
V
Negative Transient Safe Operating Area
200
VCC
0
IGBT
Q1
CB
IGBT
Q2
• In transient operating conditions (Table 1, Note 2), in either normal or hard switching conditions, the capability for the driver to sustain the
large negative spikes occurring at each switching event is specified.
100
DB
VSS
In the DC operating condition (Table 1, Note 1) when the negative voltage is excessive and a transmission failure occurs, the IR gate driver
is designed such that the last information to be transmitted will be a reset (reset dominance). This guarantees the high-side will hold the off
state, thereby protecting the system against catastrophic failures.
IR gate drivers are 100% tested at wafer and final test level for the minimum Vs DC biasing condition as well as reset dominance functionality.
IR’s gate drivers are characterized to withstand the NTSOA limits by
means of dedicated test equipment. The gate driver works properly for any
negative pulse whose amplitude and pulse-width falls within
the white area indicated in Figure 2 . Pulses whose amplitude
are large enough to fall in the gray area might result in the
0
0
gate driver not working properly.
RB
C2
Note 1: Logic operational for VS of (VSO -8 V) to (VSO +600 V). Logic state held for VS of (VSO -8 V) to (VSO – VBS)
Note 2: Operational for transient negative VS of VSS - 50 V with a 50 ns pulse width.
Note 3: CAO input pin is internally clamped with a 5.2 V zener diode.
•
•
VCC
R2
-70
Competitor A
Competitor B
IRS2607D
-80
-90
Fig 3: Short circuit test setup
Fig 4: Negative vs transient event point of failure test comparison
Figure 4 plots the negative VS voltage at which the gate driver IC
destructively fails when subjected to negative VS events of varying
duration. During a 300nsec duration negative VS event, while competing
gate driver ICs will fail at a voltage of -21V (Competitor A) and -26V
(competitor B), IRS2607D will fail only at -50V, thus exhibiting nearly 2x
or higher negative VS capability.
where the long-off-times of the low-side switch and extended tri-state
conditions renders bootstrap circuit design generally difficult.
Competing parts typically require additional protection components
(such as clamping diode) to be added to limit the extent of negative
transient on VS pins resulting in higher cost, increased complexity and
possibly impacting the switching performance of the inverter itself.
Enhanced Integrated Bootstrap Functionality
Along with under-voltage lockout functionality provided by almost all
IR gate drivers, the new motor control-specific HVIC families feature
a very low quiescent current which enables using a bootstrap power
supply for even the most demanding applications such as trapezoidal
or six-step as well as other PWM modulation techniques requiring one
inverter leg to keep a high level for long periods.
In addition, to reduce the component count and make the design easier
and more reliable, the new family of motor control gate drivers feature
integrated bootstrap functionality implemented by means of an internal
high-voltage MOSFET whose biasing conditions are properly managed
to deliver current to the high-side circuit through the low-side supply
network, emulating the external high voltage bootstrap diode.
In particular, the IRS2607D’s bootstrap function has been designed
to accommodate the more complex trapezoidal modulation scheme,
High Fidelity in Power Motor Control
The new family of motor control-specific gate drivers from IR offer full
compatibility to 3.3V CMOS standards and integrate a new low distortion
input filter that guarantees precise pulse width transmission even at the
extremes of the filtering time while guaranteeing that too short pulses
do not reach the power section as they would not be long enough for
the inverter output to change state.
Three-phase gate drivers are also designed to accurately match
propagation delays among all six channels and are tested to guarantee
the input to output pulse width distortion (defined as difference between
input pulse-width and output pulse-width) to be lower than 75ns.
Application-Specific Features
The new IR HVIC families include gate driver ICs that have been tailored to
the final application. In addition to ruggedness and extreme fidelity, new
features have been included to create even more compact and robust
inverters. The IRS26302D, for example, is the first HVIC that includes
all type of over-current protection required in a modern brake+inverter
system or in a modern PFC+inverter system. The IRS26310D includes a
special zero vector braking function that can be extremely important
when assessing the safety level of a system with certification agencies.
Whenever a Permanent Magnet (PM) motor is driven in field weakening,
protection must already be integrated in the IRS26310D.
Advanced Input Filtering
EXAMPLE 1
Definiton
EXAMPLE 2
Symbol
6 inch wire to short
output to negative bus
Voltage
Table 1: Negative VS Ruggedness Specifications in IR HVIC Product Datasheets
IN
tFIL,IN
IN
OUT
IN
tFIL,IN
OUT
tFIL,IN
Small pulses to the gate of the
switches may cause inverter damage
OUT
IN
tFIL,IN
OUT
COMPETITOR’S HVIC
INTERNATIONAL RECTIFIER HVIC
• Negative VS no-flip-glitch compared with
state-of-the-art gate driver IC
• Negative Transient Safe Operating Area datasheet
specification
Improved Performance and Application-Specific
Features Simplify Motor Control Design
5. Redundacy in the number of reset pulses transmitted to the high-side
Leveraging years of experience as a leading supplier of high-voltage ICs (HVICs)
in a wide spectrum of high-voltage switching applications, IR has introduced two
families of high-voltage gate drivers for motor control applications using either
IGBTs or power MOSFETs.
The newly developed IR gate driver families for motor control feature:
• Ruggedness – capable of operating with large negative transient, without
failing even under extreme stresses such as hard short circuit of the inverter outputs
• Micro power consumption on high-side floating driver
• Enhanced integrated bootstrap diode to significantly ease power supply design
• Fully controlled timings – propagation delays and channel-to-channel matching
so tight that pulse width compensation is not required
From the simplest half bridge gate drivers (IRS260xD family) to application-specific
devices (IRS263xD), motor control designers can now select from a wide range of IR’s
HVICs to best suit their design needs.
3. Low voltage supply short failure detection and protection through zero vector insertion
2. DC Bus over-voltage detection and protection through zero vector insertion
Package
1. Integrated logic for fault dignostic (GND/PFC/DC Bus shunt over-current and VCC UVLO faults)
QFN, MLP
available
MLP available
4. Minimum VS voltage allowing full functionality
THE POWER MANAGEMENT LEADER
• Negative VS IQCC latch-up
robustness compared to competitors, G2 and G5-D version
• Negative VS no-flip-glitch compared with state-of-the-art gate driver IC
• Negative Transient Safe Operating Area datasheet specification
Robustness
Improvement
• Redundant
reset5
ProductSpecific
Improvement
• No-short-pulse input filter
• Turn-on/turn-off delay and deadtime matching between channels
• VS headroom4
• Reset dominance5
• Power on reset of all internal latched logic
Improvement
vs G2 Family
• GND shunt overcurrent protection
• Redundant reset5
• GND/PFC/
DC+ Shunt
over-current
protection
• DC bus
over-voltage
protection2
• Op-Amp for
GND shunt
• Integrated
fault
diagnostic
protocol1
• VCC short
protection3
• Integrated
Bootstrap
• Op-Amp for
GND shunt
• Integrated
bootstrap
• Integrated
bootstrap
• Integrated
bootstrap
• VCC & VBS
UVLO
• VCC & VBS
UVLO
• VCC & VBS
UVLO
• VCC & VBS
UVLO
• VCC & VBS
UVLO
• VCC & VBS
UVLO
• VCC & VBS
UVLO
For more information, call +(33) 1 64 86 49 53 or +49 6102 884 311 or visit us at www.irf.com
• Integrated bootstrap suitable for sinusoidal modulation
• Integrated bootstrap suitable for Trapezoidal
and Sinusoidal modulation
• Single input
(programmable
deadtime)
• Complementary
inputs
(programmable
deadtime)
• Independent
high- and lowside inputs
• GND shunt
over-current
protection
• GND/PFC/
DC+ Shunt
over-current
protection
• GND shunt
over-current
protection
ProductSpecific
Function
• GND shunt
over-current
protection
• GND shunt
over-current
protection
• GND shunt
over-current
protection
• GND shunt
over-current
protection
2 HB
2 HB
2H&L
6
6 +1
6
6
Driving
Channels
6
6
IRS26302D
6
IRS2607D
IR’s Rugged HVICs
IRS2330D
IRS2332D
IRS2330
IRS2332
IRS2336
Three-Phase
HVIC / MOTOR CONTROL
IRS2336D
IRS26310D
IRS26320
Single-Phase
IRS2608(4)D
IRS2609(4)D
IR’s Rugged HVICs
10230FS
Rugged Gate Drivers by Design
In a typical motor control application design, problems arise when undertaking
prototype validation tests. When checking for waveforms and voltages, unexpected
large negative voltage transients can typically appear. This situation is even worse
when trying short circuits tests that often result in an inverter catastrophic failure.
The key challenge is to design the HVIC in a way that these negative transients are
managed properly and that the driver can cope with them safely.
International Rectifier has introduced:
• A solid method to characterize and specify the HVIC
• A reliable and methodical solution to design negative VS rugged gate drivers
+VBUS
LD2
HO
VBUS
Q2
Control IC
VS Undershoot
LS2
VS
To Load
LD1
COM
LO
VS -COM
Q1
LS1
-VS
t
Load Return
Tolerant to Negative Transient Voltage
For more information, call +(33) 1 64 86 49 53 or +49 6102 884 311 or visit us at www.irf.com
10230FS