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International Journal of Advances in Engineering Sciences Vol.1, Issue 2, April, 2011
VLSI DESIGN OF LOW POWER HIGH SPEED
ADC
Ms.T.P.Patil
Dr. Prof. A.A.Gurjar
Electronics & telecommunication
Sipna‟s C.O.E.T., Amravati
Amravati, India
Email id: [email protected]
Electronics & telecommunication
Sipna‟s C.O.E.T., Amravati
Amravati, India
Email id: [email protected]
Abstract-Analog-to-digital converters (ADCs) are key design
blocks in modern microelectronic digital communication systems.
With the fast advancement of CMOS fabrication technology,
more and more signal-processing functions are implemented in
the digital domain for a lower cost, lower power consumption,
higher yield, and higher re-configurability. This has recently
generated a great demand for low-power, low-voltage ADCs that
can be realized in a mainstream deep-submicron CMOS
technology. Various examples of ADC applications can be found
in data acquisition systems, measurement systems and digital
communication systems also imaging, instrumentation systems.
Hence, we have to considered all the parameters and improving
the associated performance may significantly reduce the
industrial cost of an ADC manufacturing process and improved
the resolution and design specially power consumption . In this
paper we have proposed a design of ADC, in < 0.18um CMOS
process.
Review of work:
The first documented example of an ADC was a 5‐bit,
electro‐optical and mechanical flash‐type converter patented
by Paul Rainey in 1921, used to transmit facsimile over
telegraph lines with 5‐bit pulse‐coded modulation (PCM) . The
first all‐electrical implementation came in 1937 by Alec
Harvey Reeves, this also had a 5‐bit resolution and the ADC
was implemented by converting the input signal to a train of
pulses which was counted to generate the binary output at a
sample rate of 6 kS/s. Following this, the successive
approximation ADC was developed in 1948 by Black, Edson
and Goodall to digitize voice to 5‐bits at 8 kS/s .Also in 1948,
a 96 kS/s, 7‐bit ADC was developed and it was implemented
using an electron beam with a sensor placed on the other side
of a mask. The mask had holes patterned according to the
binary weights so that all bits were simultaneously detected,
the pattern also employed Gray coding of the output in order
to reduce the effect of errors in the most significant bit (MSB)
transition , much as is done in modern high‐speed flash ADCs.
Keywords- ADC, CMOS process, VLSI systems.
INTRODUCTION
As IC fabrication technology has advanced, more analog
signal processing functions have been replaced by digital
blocks ,analog-to-digital converters (ADCs) retain an
important role in most modern electronic systems because
most signals of interest are analog in nature and must to be
converted to digital signals for further signal processing in the
digital domain. Analog to Digital Converters (ADCs) are
currently adopted in many application fields to improve digital
systems, which achieve superior performances with respect to
analog solutions[5]. With the continued proliferation of mixed
analog and digital VLSI systems supporting diverse chip
functionalities, the need for small sized, low-power and highspeed analog-to-digital converters using conventional CMOS
process has increased[6]. Flash ADCs and pipelined
ADC[2][8] are best for applications requiring very large
bandwidth. Generally flash ADCs are made by cascading high
speed comparators and each comparator represents 1LSB, and
the output code can be resolute in only one clock cycle The
pipeline ADC architecture consists of N, high speed, low
resolution cascaded stages. The digital output of each stage is
stored in a shift register.
Following the development of the transistor in 1947 and
the integrated circuit in 1958, the ADC development
continued in the 1960‟s with for example an 8‐bit,10 MS/s
converter that was used in missile‐defense programs in the
United States . During the same decade, all the currently used
high‐speed architectures were developed including pipeline
ADCs with error‐correction.
Motivation
In the recent years there has been a trend in ADC research
to use low accuracy analog components which are
compensated for through the use of digital error correction
.The motivation behind this is that analog design have not
been able to benefit from process scaling in the same way as
digital logic and therefore the relatively area‐cheap digital
logic is used to compensate for the shortcomings of expensive
analog circuits.
Commercial flash converters appeared in instruments
and modules of the 1960s and 1970s and quickly migrated to
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International Journal of Advances in Engineering Sciences Vol.1, Issue 2, April, 2011
integrated circuits during the 1980s. The monolithic 8-bit flash
ADC became an industry standard in digital video applications
of the 1980s. Today, the flash converter is primarily used as a
building block within subranging "pipeline". Using Partial
amplifier sharing topology , a 6 bit pipeline ADC, developed
in 0.35µm CMOS process. A 6-bit, 2.5 V flash ADC design
has been reported new flash topology and this new topology
has only 2(N-2) + 2 comparators required. Here area of the
chip is large and its required to minimize it. The AD7880 is a
high speed, low power, 12-bit A/D converter which operates
from a single +5 V supply. For device reliability reasons, the
supply voltage needs to be reduced to ensure gate oxide
integrity over time and prevent p-n junction from breakdown.
Present-day CMOS processes are making the transition from
3.3 V to 1.8 V supplies.
There are many applications for analog‐to‐digital
converters, ranging from sensors, audio and data acquisition
systems to video, radar and communications interfaces. The
applications which require the highest sample rates in the
ADC are typically found in the video, radar and
communication areas. The converter should operate with high
sampling rate from an operating supply as low as possible, to
facilitate integration with low-voltage, power efficient digital
circuits.
Power dissipation in CMOS logic arises from following
1.Switching current from charging and discharging parasitic
capacitance.
2.Short circuit current when both N & P channel transistors
are momentarily on at the same time
3.Leakage current & subthreshold current.
Average dynamic power dissipated is given by:Pavg = Ctot * VDD^2* Fclk
Power dissipation is a function of clock frequency. A great
deal of effort is put into reducing the power dissipation in
CMOS circuits. Together with the scaling of process
geometry, the supply voltage (squared term) is reduced in
order to both reduce the digital power dissipation and the rate
of device degradation.
specification , here some tuning is required for expected result
.After validation of circuit level we go for layout, at
completion of Layout we do drc check and lvs verification.
Related Work:
1) TSMC NMOS circuit
Figure 1 : NMOS CIRCUIT
Simulation Results
Proposed work
We first led down the target parameters from required
specification. Study each and every aspect of target parameters
and also dependency. We analyzes the earlier documents /
papers for better design guideline. We select two- three fix
topology for initial trials simulation and comparing these
initial results with expected target specification and after
taking final decision on topology we go for full custom design.
We first chop the complete ADC into subsection, like current
source ,op-amp , latch , decoder , dummy load, active load
etc. We design these subsections in their best fit specification
in a view of Low power high speed constraint. We try to
integrate these subsections to form complete ADC. we are
going for circuit simulation at transistor level , at first glance it
would not be running as target specification . We simulate
this transistorized ADC for cross verification with target
Figure 2
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International Journal of Advances in Engineering Sciences Vol.1, Issue 2, April, 2011
Simulation Result
2.0
vout2, V
vin1, V
1.5
1.0
0.5
0.0
-0.5
0.2
0.4
0.6
0.8
1.0
1.2
0.8
1.0
1.2
vin
Figure 3
2.0
2) Differential Amplifier
vo, V
1.5
1.0
0.5
0.0
0.2
0.4
0.6
vin
Figure 5
3) Transmission Gate
Figure 4: Differential amplifier
Figure 6: Transmission gate
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International Journal of Advances in Engineering Sciences Vol.1, Issue 2, April, 2011
[9] P. E. Allen and D. R. Holberg, „CMOS Analog Circuit Design‟, 2nd
edition.
[10] Unbehauen, R., Cichocki, A. “MOS Switched-Capacitor and Continuous
Time Integrated Circuits and systems – Analysis and Design”, Springer
Verlag Berlin Heidelberg, ISBN 3-540-50599-7, (1989).
[11] Min, B., M., Kim, P., Bowman, F., W., Boisvert D., M., Aude, A., J. „A
69-mW 10-bit 80-Msample/s Pipelined CMOS ADC“. IEEE Journal of SolidState Circuits, volume 38, No. 12, pp. 2031 – 2039, (2003).
...AN.vout, V
TRAN.vin, V
TRAN.clk, V
Simulation Result
2
1
0
1.0
0.5
0.0
1.0
0.5
0.0
-0.5
0
10
20
30
40
50
60
70
80
90
100
time, msec
Figure 7
As we have to design low power high speed ADC with
.18μm technology. With ADS we have designed some
components first and we have taken simulation results of
them.
CONCLUSION
ADC is the key design Block in modern
microelectronics digital communication system. With the
continued proliferation of mixed analog and digital VLSI
systems, the need for small sized, low-power and high-speed
analog-to-digital converters using conventional CMOS
process has increased.In this paper we have proposed VLSI
Design of Low Power High Speed ADC in <0.18 μm CMOS
process .
REFERENCES
[1] Aparicio, R., Hajimiri, A. “Capacity limits and matching properties of
integrated capacitors”. IEEE Journal of Solid-State Circuits, volume 37, No.3,
pp. 384 – 393, (2002).
[2] Stojcevski, H.P. Le, J. Singh and A. Zayegh, „Flash ADC architecture‟,
Electronics Letters, Vol. 39 No. 6, March 2003.
[3] Jincheol Yoo, Kyusun Choi, and Jahan Ghaznavi, „Quantum Voltage
Comparator for 0.07 μm CMOS Flash A/D Converters‟, IEEE, 2003.
[4] Razavi, „Principles of Data Conversion System Design‟, IEEE Press,
1995.
[5]Shehata, K.A.; Ragai, H.F.; Husien, H.; “Design and Implementation of
high speed low power 4 bit Flash ADC”International Conference on Design
and technology of integrated systems in nanoscale era ,2007
[6] Nicholas Gray, „ABCs of ADCs, Analog-to-Digital Converter Basics‟,
National Semiconductor Corporation, 2006.
[7] S. H. Lewis and H. Scott Fetternan and George F. Gross jr. and R.
Ramachandran and T. R. Vismanathan, “10-b 20 Msamples/s analog-to-digital
converter,” Journal of IEEE Solid State Circuit, vol. 27, pp. 351-358, March
1992.
[8] Dwight U. Thomson and Bruce A. Wooley, “A 15-b pipelined CMOS
floating point A/D converter, ” Journal of IEEE Solid State Circuit,vol. 36,
no. 2, February 2001.
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