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Chapter 8
MOS Memory and Storage Circuits
Microelectronic Circuit Design
Richard C. Jaeger
Travis N. Blalock
Microelectronic Circuit Design, 4E
McGraw-Hill
Chap 8 - 1
Chapter Goals
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Overall memory chip organization
Static memory circuits using the six-transistor cell
Dynamic memory circuits
Sense amplifier circuits used to read data from memory
cells
Learn about row and address decoders
Implementation of CPU registers via flip-flops
Pass Transistor Logic (PTL)
Read Only Memory (ROM)
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Chap 8 - 2
Random Access Memory
• Random Access Memory (RAM) refers to memory in a
digital system that has both read and write capabilities
• Static RAM (SRAM) is able to store its information as
long as power is applied, and it does not lose the data
during a read cycle
• Dynamic RAM (DRAM) uses a capacitor to temporarily
store data which must be refreshed periodically to prevent
information loss, and the data is lost in most DRAMs
during the read cycle
• SRAM takes approximately four times the silicon area of
DRAM
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Chap 8 - 3
A 256-Mbit Memory Chip
Note that the basic building block for this
memory is a 128Kb cell
• The figure shows the
block structure of a 256Mb memory
• There are sets of column
and row decoders that are
used for memory array
selection
• The column decoder splits
the memory into upper and
lower halves
• The row decoder and
wordline drivers bisect
each 32-Mb subarray
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A 256-Mbit Memory Chip
• The memory block
diagram contains 2M+N
storage locations
• When a bit has been
selected, the set of sense
amplifiers are used to
read/write to the
memory location
• Horizontal rows are
referred to as wordlines,
whereas the vertical
lines are called bitlines
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Chap 8 - 5
Static Memory Cells
• Inverters configured as shown in the above figure
form the basic static storage building block
• These cross-coupled inverters are often referred to
as a latch
• The circuit uses positive feedback
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Chap 8 - 6
Static Memory Cells VTC
• The previous latch has
only two stable states
and is termed bistable
• However, it is possible
for it to be held at an
unstable equilibrium
point where slight
changes in the voltage
will cause it to latch in
one of the stable states
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Chap 8 - 7
The 6-T Cell
• With the addition of two control transistors it is
possible to create the 6-T cell which stores both
the true and complemented values of the data
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Chap 8 - 8
8.2.2 The Read Operation of a 6-T Cell
Initial state of the 6-T cell storing
a “0” with the bitlines’ initial
conditions assumed to VDD/2
Conditions after the WL
transistors have been
turned on
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Chap 8 - 9
The Read Operation of a 6-T Cell
Final read state condition of
the 6-T cell
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Chap 8 - 10
The Read Operation of a 6-T Cell
Waveforms of the 6-T cell read
operation: Wordline capacitive
coupling effect
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Chap 8 - 11
The Read Operation of a 6-T Cell
• Reading a 6-T cell that is storing a “1” follows the
same concept as before, except that the sources
and drains of the WL transistors are switched
• Note that the delay is approximately 20ns for this
particular cell
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Chap 8 - 12
8.2.3 The Write Operation of a 6-T Cell
It can be seen that not much happens while writing a “0”
into a cell that already stores a “0”
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Chap 8 - 13
The Write Operation of a 6-T Cell
While writing a “0” to a cell that is storing a “1”, the
bitlines must be able to overpower the output drive of
the latch inverters to force it to store the new condition
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Chap 8 - 14
8.3 Dynamic Memory Cells
• The 1-T cell uses a capacitor for its storage element (data
is represented as either a presence or absence of a charge)
• Due to leakage currents of MA, the data will eventually be
corrupted, hence it needs to be refreshed
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Chap 8 - 15
Data Storage in a 1-T Cell
Storing a “0”
Storing a “1”
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Chap 8 - 16
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Chap 8 - 17
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Chap 8 - 18
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Chap 8 - 19
8.3.2 Data Storage in a 1-T Cell
• Notice that the voltage stored on the storage
capacitor on the previous slide does not reach VDD
• It instead is determined by the following:
VC  VG  VTN

VC  VG  VTO  
V
C
 2 F  2 F
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
Chap 8 - 20
Data Storage in a 1-T Cell
• To read a DRAM cell, the bitline is precharged to
either VDD or VDD/2, and then MA is turned on
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Chap 8 - 21
Data Storage in a 1-T Cell
• The charge stored on CC will be shared with CBL
through the process of charge sharing, where the
read voltage varies slightly
CBLVBL  CCVC
VF 
 VBL
CBL  CC
• Normally CBL >> CC, and the charging time
constant is:

  RON
CBLCC
 RON CC
CBL  CC
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Chap 8 - 22
The Four-Transistor (4-T) Cell
• Since the 6-T SRAM provides a large signal current drive
to the sense amplifier, it generally has shorter access time
as compared to a DRAM
• The 4-T DRAM cell is an alternative that increases access
time, and automatically refreshes itself
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Chap 8 - 23
• Node D charges up to 3 – VTN = 1.9 V through
access transistor MA1.
• If BL, BL’ and the wordline are all forced high,
the two access transistors temporarily at as load
devices for the 4-T cell, and the cell levels are
automatically refreshed.
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Chap 8 - 24
Reading and Writing to the 4-T DRAM
Cell
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Chap 8 - 25
8.4 Sense Amplifiers
• Sense amplifiers are used to detect the small
currents that flow through the access transistors or
the small voltage differences that occur during
charge sharing
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Chap 8 - 26
A Sense Amplifier for the 6-T Cell
• MPC is the precharge
transistor whose main
purpose is to force the
latch to operate at the
unstable point
previously mentioned
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Chap 8 - 27
Sense Amplifier Example
• For the figure on the previous slide, find the currents in the
latch transistors when MPC is turned on under the following
conditions:
W 
2
VDD  3 V

 
 L All 1
PMOS :
NMOS :
K n'  25 A /V 2
K n'  60 A /V 2
VTO  0.7 V
VTO  0.7 V
  0.5 V 1/ 2
2 F  0.6V
  0.7 V 1/ 2
2 F  0.6 V
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Chap 8 - 28
Sense Amplifier Example
• Since the output voltage should equal on both sides of the
latch when MPC is on, it is known that VGSn = VDSn for the
latch NMOS devices and VSGp = VSDp for the latch PMOS
devices. Therefore these transistors are saturated.
• Due to the symmetry of the situation, the drain currents are
equal giving the following:
K 'p W 
K n' W 
2
2
 VSG  VTP  
 VGS  VTN 
2  L 
2  L 
1 25A 2 
1 60A 2 
2
2
3

V

0.7

V

0.7

 

  O


O
2  V 2 1 
2  V 2 1 
35VO2  31VO 102.9  0  VO  1.33V
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Chap 8 - 29
Sense Amplifier Example
• The drain currents are then found by:
1 60A 2 
2
iD   2  1.33  0.7  23.6A
2  V 1 
• Note that the PMOS and NMOS drain currents are
equal

• The power dissipation is given by:
P  2iDVDD  223.5A3V   0.140mW

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Chap 8 - 30
A Sense Amplifier for the 1-T Cell
• The same sense
amplifier used in the
6-T cell can be used
for the 1-T cell in
manner shown in the
figure
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Chap 8 - 31
Sense Amplifier for the 1-T Cell
• The sense amplifier works the same as it did for the 6-T
cell, but takes longer to reach steady state after precharge
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Chap 8 - 32
The Boosted Wordline Circuit
• Obviously it is desired to have a fast access in
many DRAM applications.
• By driving the wordline to a higher voltage
(referred to as a boosted wordline), say 5V instead
of 3V, it is possible to increase the amount of
current supplied to the storage capacitors
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Chap 8 - 33
Clocked CMOS Sense Amplifiers
• The sense amplifier can definitely be a major source of power
dissipation, but by using a clocking scheme, it is possible to reduce the
power dissipated, Dummy Cell (DC), Precharge (PC), Latch clock (LC)
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Chap 8 - 34
Clocked CMOS Sense Amplifiers
• Clocking the previous
circuit in the manner
shown in the figure will
eliminate static currents
in the latch during the
precharge state, and only
transient currents will
appear
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Chap 8 - 35
Address Decoders
• The following figures are examples of commonly used
decoders for row and column address decoding
NMOS NOR Decoder
NMOS NAND Decoder
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Chap 8 - 36
Address Decoders
Complete 3-bit domino
CMOS NAND decoder
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Chap 8 - 37
Address Decoders
3-bit column data
selector using passtransistor logic
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Chap 8 - 38
Data Transmission through the PassTransistor Decoder
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Chap 8 - 39
Read-Only Memory (ROM)
• ROM is often needed in digital systems such as:
–
–
–
–
Holding the instruction set for a microprocessor
Firmware
Calculator plug-in modules
Cartridge style video games
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Chap 8 - 40
Read-Only Memory (ROM)
• The basic structure of the
NMOS static ROM is
shown in the figure
• The existence of an NMOS
transistor means a “0” is
stored at that address
otherwise a “1” is stored
• Power dissipation is large
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Chap 8 - 41
Read-Only Memory (ROM)
• The domino
CMOS ROM is
one technique
used to lower the
amount of power
dissipation
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Chap 8 - 42
Read-Only Memory (ROM)
• Another ROM
option is the
NAND array
ROM which
can be directly
used with a
NAND decoder
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Chap 8 - 43
Read-Only Memory (ROM)
• The main problem with these previous ROMs is that they
must be designed at the mask level, meaning that it is not a
versatile product.
• To solve this problem, the programmable ROM (PROM)
was introduced
• The standard PROM cannot be erased, so the erasable
ROM (EPROM), and later, electrically erasable ROM
(EEPROM) were introduced
• High density flash memories allow for electrical erasure
and reprogramming of memory cells
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Chap 8 - 44
8.7 Flip-Flops
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Chap 8 - 46
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Chap 8 - 47
RS Flip-Flop
• The reset-set (RS) flip-flop can be easily realized by using
either two cross-coupled NOR or NAND gates
• The RSFF has the following truth tables
NOR RSFF
NAND RSFF
R
S
Q
Q
R
S Q
Q
0
0
Q
Q
0
0
Q
Q
0
1
1
0
0
1
0
1
1
0
0
1
1
0
1
0
1
1
0
0
1
1
1
1
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Chap 8 - 48
RS Flip-Flop
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Chap 8 - 49
RS Flip-Flop
• Simplified RS flip-flop
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Chap 8 - 50
D-Latch using T-Gates
• A very important circuit of digital systems is the D-Latch
which is used for a D Flip-Flop
• Whenever clock C goes high in the D-Latch, the data on D
is passed through to Q
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Chap 8 - 51
Master-Slave D Flip-Flop
• By using series DLatches that latch
the data on
opposite clock
phases, a masterslave D flip-flop
can be realized
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Chap 8 - 52
End of Chapter 8
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Chap 8 - 53