Download High Level Synthesis Overview.

High-level Synthesis
and System
Synthesis
SOURCESMark Manwaring
Kia Bazargan
Giovanni De Micheli
Gupta
Youn-Long Lin
Camposano,
J. Hofstede,
Knapp,
MacMillen
Lin
Why the level of automation must go up
and up?
What Went Wrong with early
approaches to design automation ?
1. Too much emphasis on incremental work on algorithms
and point tools
2. Unrealistic assumption on component capability,
architectures, timing, etc
3. Lack of quality-measurement from the low level
4. Too many promises on fully automated system (silicon
compiler??)
Example of a Silicon Compiler System
Simulation
µ¿ÀÛÀû
Initial ȸ·ÎÀÇ
specification
񃬣
Flow graph Transformation
IN
+
D
+ OUT
D
Flow graph Database
IN
D
D
D
+
OUT
Estimation
Min Bounds On Hardware
2 Adders
6 Registers
2 Buses
Assignment / Scheduling
Hardware Mapping
reg
+
reg
shif t
reg
Silicon Compilation
Time
1
2
Adder1
Adder2
Shift
*
*
*
*
*
3
4
5
6
*
*
*
*
*
7
*
*
*
Benchmarks for a silicon compiler
benchmark
cascade
fir 11
iir5
wave
mult(*)
7
11
10
7
add(+)
7
10
10
8
sub(-)
.
.
.
3
critical path
6
11
8
8
VLSI Design Tools
• Design Capturing/Entry
• Analysis and Characterization
• Synthesis/Optimization
• Physical (Floor planning, Placement, Routing)
• Logic (FSM, Retiming, Sizing, DFT)
• High Level(RTL, Behavioral)
• Management
Design Methodology Progress
Specify and ???
Describe and Synthesize
Capture and Simulate
Why Synthesis?
Why not Synthesis?
Productivity
Performance Loss
Correctness
Unsynthesizability
Re-Targetability
Inertial
Structural
Behavioral
Block
Algorithm
FSM
RTL
Boolean
Gate
X’tor
GDSII
Y-Chart
Dan D Gajski
Placement
Floorplan
Physical
Structural
Behavioral
Block
Algorithm
FSM
RTL
Boolean
Gate
X’tor
GDSII
Layout
Synthesis
Placement
Floorplan
Physical
Structural
Behavioral
Block
Algorithm
FSM
RTL
Boolean
Gate
X’tor
GDSII
Logic
Synthesis
Placement
Floorplan
Physical
Structural
Behavioral
Block
Algorithm
FSM
RTL
Boolean
Gate
X’tor
GDSII
High-Level
Synthesis
Placement
Floorplan
Physical
Target Architectures
• Bus-based
• Multiplexer-based
• Register file
• Pipelined
• RISC, VLIW
• Interface Protocol
Goal of synthesis for future
systems
From
Behavioral specification at ‘System Level’
(Algorithms)
To
Structural implementation at ‘Register Transfer Level’ of
Data path (ALU’s, REG’s, MUX’s) and Controller
• Generally restricted to a single process
• Generally data path is optimized; controller is by-product
Levels of Abstraction
In Camposano
• Behavioral
• Register-Transfer (RTL)
• Logic
Our Abstraction levels
• System
• Register
• Logic
Abstraction levels
Synthesis
step
System
High-level
Level
Behavior
Structure
Level
Behavior
Specification
System specification
System
Algorithms
CPU’s, MEM’s
BUS’s
Register (RTL)
Register
transfers
REG’s, ALU’s, MUX’s
Logic
Boolean
expressions
Gates,
flip-flops
Circuit
Transfer
functions
Transistors
Logic
Physical
Structure
Intermediate Representation
*
*
+
Data Flow Graph
Control Flow Graph
What are possible levels of
synthesis?
What are possible styles?
How to automate big
tasks?
Layout Synthesis
Compass Placement & Routing ( 0.6µm gate array)
Layout Level
Logic Synthesis
Reminder about
blocks and
connections in
data path
Variants of simple FSMD architectures
control
Besturing
Besturing
control
Controlling
/activation
pulses
Stuurs ignalen
Controlling
/activation
pulses
Stuurs ignalen
Statussignalen
signals
Status
Data-pad
Data
Path
Data-pad
Data
Path
Variants of simple FSMD architectures
Besturing
control
Controlling
/activation
pulses
Stuursignalen
Data
Data-pad
Path
Instructions
Instructie
IR
Status signals
Statussignalen
FSM with Data Path (FSMD)
FSM
Data
Path
Interactive FSMDs
FSM
Data
Path
FSM
Data
Path
Details of control signals
Register; a) RTL level b) with control signal
details
controls:
Reg_EO
Enable Output
Reg_EI
Enable Input
RegFile_EI
RegFile_SI <p>
Control of register files
control signals:
RegFile_EO1
p
RegFile_SO1
RegFile_SI
Door
de besturing te
RegFile_EO1
sturen RegFile_SO1
signalen:
p
RegFile_EI
0
1
2
0
1
2
n
*
n
n
n
*
*
RegFile_EO2
RegFile_SO2
RegFile_SO2
<p>
RegFile_EO2
RegFile
n
Clock
k-1
<p>
k-1
RegFile_SO2
p
p = 2log(k)
RegFile_EO2
a)
*
RegFile_EO1
<p>
RegFile_SO1 <p>
n
b)
Figuura)
6.9:RTL
Register-file
Register;
level met
b) twee
withuitgangen
control signal
a) RTL-niveau
b) Met stuursignalen
details
RegFile_EI
RegFile_SI <p>
RegFile_EI
RegFile_SI <p>
The role of tri-state signals
Scheduling and
allocation problems are
similar
In1
n
In2
n
In3
n
Clock
Reg1_EO
Reg1
*
Reg2_EO
Reg2
*
n
Reg3_EO
Reg3
*
n
n
n
Clock
Figuur 6.10a: 3 bronnen met 'tri-state' uitgangen
Tri-state signals in buses instead of
multiplexing
n
Multiplexing
In1
n
In2
n
In3
n
Clock
Reg1
Reg2
Reg3
n
n
n
0 MUX
1
2
0 1 2
Reg3_EO
Reg2_EO
Reg1_EO
Clock
n
n
Communication with a memory
Memory
Address
External
Data
ex ter ne
address-bus
adres -bus
m
MAR
m
n
exExternal
ter ne data-bus
data-bus
MBR
n
Internal
interne
bus
Figuur 6.11: Communicatie met omgeving
bus
Pipeline Design Issues
• Pipelined processor design
• Pipeline is an implementation issue.
• A behavioral representation should not specify the
pipeline.
• Most processor instruction sets are conceived with an
implementation in mind.
• The behavior is defined to fit an implementation
model.
Semantics of variables
• Variables are implemented in hardware by:
• Registers.
• Wires.
• The hardware can store information or not.
• Cases:
• Combinational circuits.
• Sequential circuits.
Semantics of variables
Semantics of variables
• Combinational circuits.
• Multiple-assignment to a variable.
• Conflict resolution.
• Oring.
• Last assignment.
Semantics of variables
Semantics of variables
•
•
•
•
Sequential circuits.
Multiple-assignment to a variable.
Variable retains its value until reassigned.
Problem:
• Variable propagation and observability.
Semantics of variables
Example
• Multiple reassignments:
• x= 0 ; x = 1 ; x = 0 ;
• Interpretations:
• Each assignment takes a cycle. --> pulse.
• x assumes value 0.
• x assumes value 0 after a short glitch.
Semantics of variables
Timing semantics
• Most procedural HDLs specify a partial order among
operations.
• What is the timing of an operation?
• A posteriori model:
• Delay annotation.
• A priori model:
• Timing constraints.
• Synthesis policies.
Timing semantics
(event-driven semantics)
• Digital synchronous implementation.
• An operation is triggered by some event:
• If the inputs to an operation change
--> the operation is re-evaluated.
• Used by simulators for efficiency reasons.
Synthesis policy
for VHDL and Verilog
• Operations are synchronized to a clock by using a wait
(or @) command.
• Wait and @ statements delimit clock boundaries.
• Clock is a parameter of the model:
• model is updated at each clock cycle.
Verilog example
behavior of sequential logic circuit
module DIFFEQ (x, y, u , dx, a, clock, start);
input [7:0] a, dx;
inout [7:0] x, y, u;
input clock, start;
reg [7:0] xl, ul, yl;
always
begin
wait ( start);
while ( x < a )
begin
xl = x + dx;
ul = u - (3 * x * u * dx) - (3 * y * dx);
yl = y + (u * dx);
@(posedge clock);
x = xl; u = ul ; y = yl;
end
endmodule
Abstract models
• Models based on graphs.
• Useful for:
• Machine-level processing.
• Reasoning about properties.
• Derived from language models by compilation.
Abstract models
Examples
• Netlists:
• Structural views.
• Logic networks
• Mixed structural/behavioral views.
• State diagrams
• Behavioral views of sequential logic models.
• Dataflow and sequencing graphs.
• Abstraction of behavioral models.
Data flow graphs
• Behavioral views of architectural models.
• Useful to represent data-paths.
• Graph:
• Vertices = operations.
• Edges = dependencies.
Dataflow graph Example
xl = x + dx
ul = u - (3 * x * u * dx) - (3 * y * dx)
yl = y + u * dx
c = xl < a
Example of Data Flow Graph
continued
xl = x + dx
ul = u - (3 * x * u * dx)
- (3 * y * dx)
yl = y + u * dx
c = xl < a
Sequencing graphs
• Behavioral views of architectural models.
• Useful to represent data-path and control.
• Extended data flow graphs:
• Operation serialization.
• Hierarchy.
• Control- flow commands:
• branching and iteration.
• Polar: source and sink.
Example of sequencing graph
Example of Hierarchy
Example of branching
Example of iteration
diffeq {
read (x; y; u; dx; a);
repeat {
xl = x +dx;
ul = u - (3 * x * u* dx) - (3 * y * dx);
yl = y +u dx;
c = x < a;
x = xl; u = ul; y = yl;
}
until ( c ) ;
write (y);
}
Example of iteration
Semantics of sequencing graphs
• Marking of vertices:
• Waiting for execution.
• Executing.
• Have completed execution.
• Execution semantics:
• An operation can be fired as soon as all its immediate
predecessors have completed execution
Vertex attributes
• Area cost.
• Delay cost:
• Propagation delay.
• Execution delay.
• Data-dependent execution delays:
• Bounded (e.g. branching).
• Unbounded (e.g. iteration, synchronization).
Properties of sequencing
graphs
• Computed by visiting hierarchy bottom-up.
• Area estimate:
• Sum of the area attributes of all vertices.
• Worst-case - no sharing.
• Delay estimate (latency):
• Bounded-latency graphs.
• Length of longest path.
Summary on specification models
• Hardware synthesis requires specialized language support.
• VHDL and Verilog HDL are mainly used today:
• Similar features.
• Simulation-oriented.
•
Synthesis from programming languages is also possible.
• Hardware and software models of computation are different.
• Appropriate hardware semantics need to be associated with programming
languages.
•
Abstract models:
• Capture essential information.
• Derivable from HDL models.
• Useful to prove properties.
Control
Design
Control 1
Control design
Control of
• Registers
• Functional units
• Multiplexers and 3-state drivers
• Memory
Simple micro-programmed controller
Control signals from
ROM or data path
MUX
INCR
Program
counter
Microcode
ROM
Control lines
Jump address
Mode registers
Control lines
Control 2
Control design issues
1. To avoid false combinational cycles, either the inputs or
the outputs of the controller are registered.
2. Note the one cycle delay between a condition and the
resulting reaction in the controller.
3. Controller can even be pipelined,
•
•
which can remove the controller from the critical path,
but increases the delay for the conditions.
Overview of Hardware Synthesis
converts the program text file into strings of
tokens. Tokens can be specified by regular
expressions. In the UNIX world, the “lex” tools
are popular for this.
•The syntax of a programming language is specified by
a grammar. (A grammar defines the order and types of
tokens.) This analysis organized streams of tokens into
an abstract syntax tree.
Overview of Hardware Synthesis
analyze the semantics,
or meanings, of the
program.
Generate a symbol table.
Check for uniqueness of
symbols and information
about them.
determine the order and
organization of operations