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Chapter 2 (Part 2) Instructions: Language of the Computer 陳瑞奇(J.C. Chen) 亞洲大學資訊工程學系 Adapted from class notes by Prof. C.T. King, NTHU, Prof. M.J. Irwin, PSU and Prof. D. Patterson, UCB 1 §2.6 Logical Operations 2.6 Logical Operations Fig. 2.8, p.87 (頁87) Instructions for bitwise manipulation Operation C Java MIPS Shift left << << sll Shift right >> >>> srl Bitwise AND & & and, andi Bitwise OR | | or, ori Bitwise NOT ~ ~ nor Useful for extracting and inserting groups of bits in a word 邏輯運算子 && || 關係運算子 2 srl $s1, $s2, 8 sll $s1, $s2, 8 4 p.88 (頁88) Shift left logical (sll) Example: sll $t2, $s0, 4 Instruction Format (R-format): op 0 rs 0 rt 16 rd 10 Why not I-format? shamt funct 4 0 000000 00000 10000 01010 00100 000000 5 NOT Operations Useful to invert bits in a word Change MIPS a 0 to 1, and 1 to 0 has NOR 3-operand instruction NOR b == NOT ( a OR b ) nor $t0, $t1, $zero $t1 0000 0000 0000 0000 0011 1100 0000 0000 $t0 1111 1111 1111 1111 1100 0011 1111 1111 nor $t0, $t1, $t1 Register 0: always read as zero 8 Variety of Logic Gates 9 Logical Operations (cont.) Fig. 2.1, p.64 (頁62) Not $zero Shifts 10 2.7 Instructions for Making Decisions Decision making A computer vs. a simple calculator: Decision making instructions ? alter the control flow, i.e., change the "next" instruction to be executed MIPS conditional branch instructions (I-format): beq rs, rt, L1 if (rs == rt) branch to instruction labeled L1; bne rs, rt, L1 if (rs != rt) branch to instruction labeled L1; j L1 (J-format) unconditional jump to instruction labeled L1 11 Compiling If Statements p.91 (頁91) Example: f$s0, g$s1, h$s2, i$s3, j$s4 if (i==j) f=g+h; else f=g-h; bne add j Else: sub Exit: ... $s3, $s4, Else $s0, $s1, $s2 Exit $s0, $s1, $s2 Assembler calculates addresses Fig. 2.9 13 2.8 Supporting Procedures in Computer Hardware MIPS procedure call instruction (jump-and-link): jal ProcedureAddress #jump and link Saves PC+4 in register $ra to have a link to the next instruction for the procedure return Machine format (J-format): op 3 Then can do procedure return with a jump register instruction jr 26 bit address 2500 $ra #return Instruction format (R-format): op 0 rs 31 0 0 0 funct 8 25 Supporting Procedures (cont.) Convention in allocating its registers for procedure calling: $a0 - $a3: four argument registers $v0 - $v1: two value registers in which to return values $ra: one return address register (PC + 4) Procedure $a0 = n PC $v0 = ? = Program Counter = Instruction Address Register = IAR Caller vs. Callee 28 Aside: Spilling Registers What if the callee needs more registers? What if the procedure is recursive? uses a stack – a last-in-first-out queue – in memory for passing additional values or saving (recursive) return address(es) high addr One of the general registers, $sp, is used to address the stack (which “grows” from high address to low address) Push top of stack $sp = $sp – 4 data on stack at new $sp $sp low addr Pop add data onto the stack – push remove data from the stack–pop data from stack at $sp $sp = $sp + 4 29 Fig. 2.10 p.100(頁100) Stack 32 A = A + 5; B = B + 1; Small constants are used often in typical codeC = C - 18; Possible approaches? 2.9 MIPS Immediate Instructions e.g., put “typical constants” in memory and load them create hard-wired registers (like $zero) for constants like 1 have special instructions that contain constants ! addi $sp, $sp, 4 #$sp = $sp + 4 slti $t0, $s2, 15 #$t0 = 1 if $s2<15 Machine format (I format): op rs rt 16 bit immediate I format The constant is kept inside the instruction itself! Immediate format limits values to the range +215–1 to -215 Design Principle: Make the common case fast. 46 How About Larger Constants? p.107(頁108) We'd also like to be able to load a 32 bit constant into a register, for this we must use two instructions a new "load upper immediate" instruction lui $t0, 1010101010101010 16 0 8 1010101010101010 Then must get the lower order bits right, use ori $t0, $t0, 1010101010101010 1010101010101010 0000000000000000 0000000000000000 1010101010101010 1010101010101010 1010101010101010 47 Addresses in Branches Instructions: bne $t4,$t5,Label #Next instruction is at Label if $t4≠$t5 beq $t4,$t5,Label #Next instruction is at Label if $t4=$t5 Formats: I op rs rt 16 bit address Could specify a register (like lw and sw) and add it to address Word addressing offset (byte addressing 18 bits) use Instruction Address Register (PC = program counter) most branches are local (principle of locality) Jump instructions just use high order bits of PC address boundaries of 256 MB 48 MIPS Control Flow Instructions MIPS conditional branch instructions: bne $s0, $s1, Lbl #go to Lbl if $s0$s1 beq $s0, $s1, Lbl #go to Lbl if $s0=$s1 Instruction Format (I-format): op rs rt 16 bit offset How is the branch destination address specified? PC-relative addressing –instruction address is the sum of the PC and a 16-bit constant contained within the instruction sll 2 bits op rs rt offset Memory branch destination instruction Program Counter (PC) 49 Other Control Flow Instructions MIPS also has an unconditional branch instruction or jump instruction: j label jal proc # go to label # call proc Instruction Format (J-format): op 26-bit address from the low order 26 bits of the jump instruction 26 00 32 4 PC 32 Fetch new instruction 51 Branching Far Away What if the branch destination is further away than can be captured in 16 bits? assembler comes to the rescue – it inserts an unconditional jump to the branch target and inverts the condition The beq $s0, $s1, L1 becomes bne $s0, $s1, L2 j L1 L2: 53 MIPS Operand Addressing Modes Register addressing – operand is in a register op rs rt rd funct Register word operand Base (displacement) addressing – operand is at the memory location whose address is the sum of a register and a 16-bit constant contained within the instruction op rs rt offset Memory word or byte operand base register Register relative (indirect) with Pseudo-direct with 0($a0) addr($zero) Immediate addressing – operand is a 16-bit constant contained within the instruction op rs rt operand p.112 (頁113) 54 MIPS Instruction Addressing Modes PC-relative addressing –instruction address is the sum of the PC and a 16-bit constant contained within the instruction sll 2 bits op rs rt offset Memory branch destination instruction Program Counter (PC) Pseudo-direct addressing – instruction address is the 26-bit constant contained within the instruction concatenated with the upper 4 bits of the PC sll 2 bits op Memory jump address Program Counter (PC) | | jump destination instruction 4 bits p.112 (頁113) 55 Addressing Mode Summary Fig. 2.13 p.112 (頁113) 字組 半字組 56 p.113 (頁115) Decoding Machine Code A code dump 00af8020hex ? (assembly language) 000000 00101 op rs 01111 10000 00000 100000 rd shamt funct rt add $s0, $a1, $t7 How ? What ? 57 MIPS R3000 Instruction Set Architecture (ISA) Instruction Categories Computational Load/Store Jump and Branch Floating Point - coprocessor Memory Management Special Registers R0 - R31 PC HI LO 3 Instruction Formats: all 32 bits wide OP rs rt OP rs rt OP rd sa immediate jump target funct R format I format J format 58 MIPS Register Convention Fig. 2.14, p.105(頁106) Name Register Number $zero 0 $at 1 $v0 - $v1 2-3 $a0 - $a3 4-7 $t0 - $t7 8-15 $s0 - $s7 16-23 $t8 - $t9 24-25 $gp 28 $sp 29 $fp 30 $ra 31 Usage Preserve on call? constant 0 (hardware) n.a. reserved for assembler n.a. returned values no arguments no temporaries no saved values yes temporaries no global pointer yes stack pointer yes frame pointer yes return addr (hardware) yes $k0 - $k1 (26 – 27) are reserved for the operating system 59 MIPS instruction encoding p.114(頁114)Fig.2.17 op (31:26) 28-26 31-29 0(000) 1(001) 0(000) R-format Bltz/gez jump jump link 1(001) add addiu set less than imm. immediate 2(010) 2(010) 3(011) 4(100) 5(101) 6(110) branch eq branch ne blez bgtz sltiu andi ori xori load upper imm lbu lhu lwr TLB FlPt 4(100) load byte lh lwl load word 5(101) store byte sh swl store word 6(110) lwc0 lwc1 7(111) swc0 swc1 & 7(111) 3(011) swr 60 MIPS instruction encoding p.114(頁114)Fig.2.17 op (31:26) = 000000 (R-format), funct(5:0) 2-0 5-3 0(000) 0(000) sll 1(001) jump reg. jalr 2(010) mfhi mthi mflo mtlo 3(011) mult multu div divu 4(100) add addu subtract subu set l.t. sltu 5(101) 1(001) 2(010) srl 3(011) sra 4(100) 5(101) sllv syscal l break and or 6(110) 7(111) srlv srav xor nor 6(110) 7(111) p.115 (頁115) Fig.2.18 61 2.11 Translation and Startup Compiler Assembler Linker Loader p.119 (頁120) Fig. 2.19 69 ARM: the most popular embedded core Similar basic set of instructions to MIPS ARM MIPS 1985 32 bits 1985 32 bits Address space Data alignment 32-bit flat Aligned 32-bit flat Aligned Data addressing modes Registers 9 15 × 32-bit 3 31 × 32-bit Memory mapped Memory mapped Date announced Instruction size Input/output p.135 (頁138) Fig. 2.27 §2.16 Real Stuff: ARM Instructions 2.16 ARM & MIPS Similarities 77 x86 Overview Complexity: Instructions from 1 to 17 bytes long one operand must act as both a source and destination one operand can come from memory complex addressing modes e.g., “base or scaled index with 8 or 32 bit displacement” 86 2.19 MIPS (RISC) Design Principles Simplicity favors regularity fixed size instructions – 32-bits small number of instruction formats opcode always the first 6 bits Good design demands good compromises p.150 (頁156) three instruction formats Smaller is faster limited instruction set limited number of registers in register file limited number of addressing modes Make the common case fast arithmetic operands from the register file (load-store machine) allow instructions to contain immediate operands 90 Homework Assignment #2 (Due in 2 weeks) 題號 (分數%) 2.3 (10%) 對以下的C敘述句,對應的MIPS組合碼是什麼? 假設變數f、g、h、i及j分別被指定存於暫存器$s0、$s1、 $s2、$s3及$s4中。又假設陣列A及B的基底位址分別存於 暫存器$s6及$s7中。 B[8] = A[i - j]; 2.9 (10%) 將下列C碼翻譯成MIPS碼。假設變數f、g、h、 i及j分別被指定存於暫存器$s0、$s1、$s2、$s3及$s4中 。又假設陣列A及B的基底位址分別存於暫存器$s6及$s7 中。在假設陣列A及B的元素是4位元的字組: B[8] = A[i] – A[j]; 91 HW#2 2.12 假設暫存器$s0與$s1分別存有值0x80000000與 0xD0000000。 (5%) 執行下列組合指令後,$t0的值為何? add $t0, $s0, $s1 2.12.1 2.12.2 (5%) 在$t0中的值試所欲的值、或是已有滿溢發生? (10%) 對於下列二進制數字:0000 0010 0001 0000 1000 0000 0010 00002,寫出他的組合語言指令類型以及指 令。 2.14 (10%) 對下列指令:sw $t1,32($t2),寫出它的指令類 型以及十六進制表示法。 2.15 (10%) 對下列MIPS欄位:op=0,rs=3,rt=2,rd=3, shamt=0,funct=34,寫出它的指令類型、組合語言類型、 以及二進制表示法。 2.16 92 HW#2 2.17 (10%) 對下列MIPS欄位:op=0x23,rs=1,rt=2, const=0x4,寫出它的指令類型、組合語言類型,以及二 進制表示法。 2.21 (10%) 寫出可用於實現下列假指令的最少的MIPS指 令: not $t1, $t2 //bit-wise invert 2.24 (10%) 假設程式計數器(PC)設定為0x2000 0000。是 否可能以MIPS組合指令跳躍(j)將PC設為地址0x4000 0000?是否可能以MIPS組合指令若相等分支(beq)將PC設 為該相同地址? 2.39 (10%) 寫出能產生32位元常數0010 0000 0000 0001 0100 1001 0010 01002並將該值存於暫存器$t1中的MIPS 組合語言碼。 93