Download Computer Architecture Fall, 2016 Week 4 2016.10.03

Computer Architecture
Fall, 2016
Week 4
2016.10.03
1.
Please transform the below instruction into the decimal representation and the
binary representation.
sw $t3 1000($t5)
Instruction
Opcode
lw
100011
sw
101011
slt
101010
sltu
101001
slti
001010
Design principle 3: Make the common case fast
Design principle 4: Good design demands compromise
[Group 2]
2. Following is the description of instructions, which one is correct?
(A)Instruction is designed to 32 bits for the data is in words.
(B)Instructions have 32 bits, so shamt field can shift a 32-bits word by 32.
(C)Immediate field has 16 bits, when using operations such as addi or slti, we use
16-bits value in immediate field to calculate directly.
(D)In MIPS instruction, lw and sw divide instruction to four field, opcode, rs(base
register), rd(destination register), and immediate.
3.
Compile these C code into MIPS code.
if(register1<register2){
register3 += 5;
}
else{
register3 *= 2;
}
(register1 in $s1,register2 in $s2,register3 in $s3)
4.
sll 的 opcode=0, funct=0, $t2=10, $s0 = 16
請將此 instruction 分別轉換成二進位和十六進位
5.
After running the code, what are the values of s0,s1 and s2?
A:
slti
beq
slti
beq
add
srl
jB
addi
jA
B:
D:
C:
6.
$t1, $s0, 5
$zero, $t1, C
$t2, $s1, 1
$t2, $zero, D
$s2, $s2, $s0
$s1, $s1 ,1
$s0, $s0, 1
Why does MIPS not have "branch on more than" instruction?
7.
Please decompile the hexadecimal machine code to C language. The parameters
of a~f is represented to $s0~$s7 and store the decimal number 0~7. The negative
number use 2’s complement. Ask the final answer of a is ?
instrustion
opcode
function
add
000000
100000
sub
000000
100010
addi
001000
sll
000000
000000
slt
000000
101010
00063100
00462020
2080FF9E
8.
Translate the following C code into MIPS assembly code.
while(save[i] >= k) i+=2;
i in $s3, k in $s5, address of save in $s6