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ISSCC 2011 / SESSION 18 / ORGANIC INNOVATIONS / 18.4
18.4
Fully Printed Organic CMOS Technology on Plastic
Substrates for Digital and Analog Applications
Anis Daami1, Cécile Bory1, Mohamed Benwadih1, Stéphanie Jacob1,
Romain Gwoziecki1, Isabelle Chartier1, Romain Coppard1,
Christophe Serbutoviez1, Lidia Maddiona2, Enzo Fontana2,
Antonino Scuderi2
1
CEA-LITEN, Grenoble, France,
STMicroelectronics, Catania, Italy
2
Drastic efforts have been realized these last years in order to develop complementary organic technology. This is the essential key to produce elementary lowcost circuits for digital and analog applications. Different techniques [1-3] are
available nowadays to obtain both N- and/or P-type organic devices. Screen
printing is one of the most highly awaited low-cost techniques that can be used
to produce organic devices and circuits. It has been widely used in P-type organic technologies [4, 5]. Now that N-type semiconductors have become much
more easily processed, developers are seeking a complete CMOS and lifetime
robust technology. Many previous works have reported on a complete solution
based on CMOS technology [6-8]. Large-area-compatible organic processes
have also been demonstrated [9]. Nevertheless some of the technological steps
in these latter reports are not fully printed and/or still present some
lithography/vacuum deposition steps. We present here a complete fully printed
CMOS technology on flexible substrates showing acceptable device performances and digital/analog circuit functionalities, which can lead to more complex
designs.
Based on our design toolkit we have processed a testchip including single
devices, inverters, ring oscillators and simple analog circuits such as current
mirrors, differential pairs and cascodes (see Fig. 18.4.7) in order to show the
feasibility of our organic CMOS technology.
Our organic CMOS top-gate design fabrication is carried out on a 10×10 cm2
gold-plated 125µm-thick Polyethylene-naphtalate (PEN) substrate. The first step
consists of a patterning by laser ablation of source/drain electrodes, which also
serves as first level of interconnections, where we attain a 5µm line/space resolution. P-type and N-type semiconductors are then screen printed on the foil and
then annealed at a temperature of 100°C in normal atmospheric conditions. The
gate dielectric polymer is screen printed above both semiconductors leaving
open vias for level interconnections and then annealed. Finally the gate and the
second interconnection level are printed with same technique using a conductive
silver ink. A final annealing step at 100°C is performed.
We have carried out all our measurements in ambient temperature and pressure.
In Fig 18.4.1 we show the transfer and output characteristics of both types of
devices for the geometry W/L = 2000/20µm. We observe that both types of
devices show equivalent levels of ON and OFF state currents. Table 1 (see Fig.
18.4.2) summarizes the important electrical parameters for 2 different transistor
geometries. Threshold voltage and saturation mobility for both types of devices
have been monitored on the whole set of available transistors to evaluate their
respective dispersions. Figure 18.4.3 shows the distributions of N- and P-type
threshold voltage and mobility.
The 7-stage oscillator shows well-defined oscillation levels with oscillation frequencies varying from 70Hz @ 40V to 16Hz @ 20V, corresponding to delay/gate
values of 1ms and 4.5ms, respectively.
Regarding analog applications, basic functions such as current mirrors and differential pairs are characterized. At a preliminary stage, we have carried out our
measurements on equally sized devices of W/L=2000/20µm for both NMOS and
PMOS transistors. Figure 18.4.5 presents the electrical results concerning a Ptype current mirror tested at different supply-voltage values. Good matching
properties are observed between measured and forced currents. In Fig. 18.4.6,
we show a functional N-type differential pair loaded with a P-type current mirror
and its corresponding characterization, showing acceptable maximum gains of
17 for V+ = 10V and 9.6 for V+ = 20V.
To summarize, we have developed a complete printed organic CMOS technology on a plastic foil using large-area-compatible printing processes, that shows
good and stable electrical characteristics. In comparison to other large-area
studies, we emphasize the fact that our technology uses a mass-printing-compatible process, which can be expandable to extra-large areas with potentially
low-cost techniques. We also show elementary logic and analog circuits that are
functional and present rather good performances. These results will allow the
design and printing of higher-complexity organic CMOS circuits.
Acknowledgment:
Part of this work has been realized in the frame of the European funded project
COSMIC.
References:
[1] I. Kymissis, A.I. Akinwande, V. Bulovic, “A Lithographic Process for
Integrated Organic Field-Effect Transistors,” IEEE J. Disp. Tech., vol. 1, pp. 9-13,
Jan. 2005.
[2] H. Yan, et al., “A high-mobility electron-transporting polymer for printed transistors”, Nature, 457, 679-686, Feb. 5, 2009.
[3] R. Blache, et al., “Organic CMOS Circuits for RFID Applications”, ISSCC Dig.
Tech. Papers, pp. 208-210, Feb. 2009.
[4] M. Böhm, et al., “Printable Electronics for Polymer RFID Applications”,
ISSCC Dig. Tech. Papers, pp. 1034-1041, Feb. 2006.
[5] K. Myny, et al., “An Inductively-Coupled 64b Organic RFID Tag Operating at
13.56MHz with a Data Rate of 787b/s”, ISSCC Dig. Tech. Papers, pp. 290-292,
Feb. 2008.
[6] Wei Xiong, et al., “A 3V 6b successive-approximation ADC using complementary organic thin-film transistors on glass”, ISSCC Dig. Tech. Papers, pp.
134-135, Feb. 2010.
[7] De Vusser, et al., “ A 2V Organic Complementary Inverter”, ISSCC Dig. Tech.
Papers, pp. 1082-1091, Feb. 2006.
[8] Ishida, et al., “A Stretchable EMI Measurement Sheet with 8×8 Coil Array, 2V
Organic CMOS Decoder, and -70dBm EMI Detection Circuits in 0.18 m CMOS”,
ISSCC Dig. Tech. Papers, pp. 472-474, Feb. 2009.
[9] Da He, et al., “An integrated Organic Circuit Array for Flexible Large-Area
Temperature Sensing”, ISSCC Dig. Tech. Papers, pp. 142-144, Feb. 2010.
For digital applications, elementary inverters and ring oscillators have been tested. In Fig. 18.4.4, we present a fully functional inverter (Wn=Wp=1000µm and
L=20µm) and its corresponding 7-stage ring-oscillator time evolution. The
inverter presents respectively a noise margin of 14V and 5.5V at a supply voltage Vdd of 40V and 20V, with gains around 13 and 6 at Vdd/2. In Table 2 (see Fig.
18.4.2), we summarize the important parameters of this inverter.
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• 2011 IEEE International Solid-State Circuits Conference
©2011 IEEE
Session_18_Session_ 11/18/10 12:52 PM Page 12
ISSCC 2011 / February X, 2011 / X:XX XX
Figure 18.4.1: NMOS (black)/PMOS (red) transfer and output characteristics
for W/L=2000/20µm at Vdslin = ± 5V and Vdsat = ± 40V.
Figure 18.4.2: Summary tables for NMOS, PMOS (W=2000µm, L=20/100µm)
and inverter (W=1000µm, L=20µm) electrical parameters.
Figure 18.4.3: Threshold voltage and mobility distributions for N- and P-type
transistors.
Figure 18.4.4: Inverter static characteristic and its corresponding ring
oscillations at different power supplies. WN,P=1000µm & LN,P=20µm.
Figure 18.4.5: P-type current mirror characteristics. Transistors are equally
sized with W=2000µm and L=20µm.
Figure 18.4.6: N-type differential pair with P-type current mirror as load. N
and P-type transistors are all equally sized with W=2000µm & L=20µm.
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Session_18_Session_ 11/18/10 12:52 PM Page 13
ISSCC 2011 PAPER CONTINUATIONS
Figure 18.4.7: Back photograph of a fully printed 10cm × 10cm plastic foil with CMOS
single devices, inverters, ring oscillators and analog circuits.
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• 2011 IEEE International Solid-State Circuits Conference
©2011 IEEE