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Running head: FABRICATION AND ELECTRICAL MEASUREMENTS OF MEMORY
Fabrication and Electrical Measurements of Memory
Name
Institution
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FABRICATION AND ELECTRICAL MEASUREMENTS OF MEMORY
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Fabrication and Electrical Measurements of Memory
Fabrication of MOS Structures
Firstly, the P silicon substrate having a thin (1-2 nm) native oxide was provided, and the
silicon wafer was cleaned using a standard RCA cleaning procedure. For the bottom contact, this
was achieved through the evaporation of aluminum followed by annealing in Nitrogen gas at a
temperature of 500˚C to obtain an ohmic contact. After that, the side of a silicon wafer that had
been polished was coated with metal nanoparticles through thermal evaporation. Next, the coated
wafer had poly/crystalline nanostructures deposited on it. Finally, the device was completed by
filling it with a silicon nitride layer and an aluminum contact. For deposition, the following
parameters were followed:
Silicon Nitride Deposition Parameters
Silane flow rate = 6.6 sccm, Ammonia flow rate = 40 sccm, Nitrogen flow rate = 100 sccm,
Temperature = 300 ˚C, Pressure = 350 mTorr, RF power 20Watts, Growth time 20 minutes.
Deposition conditions for Silicon Nanostructures
Silane flow rate = 20 sccm, Hydrogen flow rate = 100 sccm, Temperature = 400 ˚C, Pressure =
500 mTorr, RF power = 15Watts, deposition time = 5 minutes.
Electrical Measurements
At first, the leakage current measurements were done using an HP4140B pico-ammeter.
If leakage current was found to be less than 10nA at a given voltage, then measurements were
continued using an LCR bridge HP4192A to allow the measurement of capacitance-voltage
FABRICATION AND ELECTRICAL MEASUREMENTS OF MEMORY
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behavior for an MIS diode. The Vrms was set at 0.150V and frequency values at 1 kHz, 10 kHz,
50 kHz, 100 kHz, and 300 kHz. After that, capacitance-voltage measurements were taken. Care
was taken in setting start and end voltages such that amount of leakage currents were less than
10nA. Subsequently, measurements were carried by employing an HP4192A impedance analyzer
in a shielded box to avoid electromagnetic interference from the electrical measurements.
Resulting voltage varied between positive and negative values. Accordingly, for a p-type MIS
structure, bias changed from an inversion region to an accumulation area. Then, C-V behavior
was measured for two memory samples at different frequencies. In the case of retention
measurements, write, read, and erase voltages were selected in agreement with C-V
measurements made. Lastly, two states ("0" and "1") were measured for a large number of 0.1second pulses.
MIS Diode and electrical charging mechanism in flash memory
In the case of flash memory, an MIS (Metal- Insulator- Semiconductor) diode translates
to an MOS (Metal-Oxide-Semiconductor) transistor. An MOS transistor allows the charging of a
flash memory, which then permits the storage of a "1". Just like an MIS diode, an MOS transistor
consists of a source, drain, and gate (floating gate), which then stores the electrical charge
(Boscke, 2010). Additionally, an MIS diode comprises an n-p-n junction. Accordingly, a positive
voltage has to be applied for electrons to flow and ultimately move to the floating gate. In this
regard, the electrical charging mechanism in flash memory can be explained by an MIS diode
(Nowozin, 2013).
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The area enclosed by C-V curves for a memory device for C-V measured at different
frequencies.
The areas of C-V curves at various frequencies were calculated as follows
Table 1
Varying enclosed area values for C-V curves at different frequencies
C-V Frequency (kHz)
Area (unit2)
1
2.45907*10-11
10
4.79359* 1012
50
1.5448*1012
300
6.57917*1013
1000
4.97078E*1013
Variations are observed in the enclosed areas of the memory device measured at a different
frequency. According to the calculated values in Table 1, the area decreases with increasing
frequency. The reduction in the area could be attributed to the use of an MOS capacitor, whereby
the frequency of a signal affects the ultimate C-V curve. Specifically, at low frequencies, the rate
of generation for holes/electrons in the silicon surface layer is significantly fast, and a sheet of
charge is formed, which maximizes the capacitance. Conversely, in the case of high frequency, a
low charge is generated and, as a result, the capacitance is at a minimum (Pinna & Knez, 2012).
FABRICATION AND ELECTRICAL MEASUREMENTS OF MEMORY
CV data to calculate the charge storage
Since charge, Q can be expressed as Q= C*V, then the charge corresponds to the areas
obtained in Table 1 above.
The retention data for "0" and "1" states
C-T
3.00E-10
2.50E-10
2.00E-10
1.50E-10
C-T
1.00E-10
5.00E-11
0.00E+00
-20
0
20
40
60
80
100
120
Figure 1: Retention test results done for 100 seconds
C-T
3.00E-10
2.50E-10
2.00E-10
1.50E-10
C-T
1.00E-10
5.00E-11
0.00E+00
0
200
400
600
800
1000
1200
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FABRICATION AND ELECTRICAL MEASUREMENTS OF MEMORY
Figure 2: Retention test results done for 1000 seconds
In both figures 1 and 2, the device has an erased state (“0”), while only figure 1 has a
programmed state (“2”). In this regard, the device is observed to have leaked charged at 1000
seconds, thus implying the absence of a programmed state.
Working principle of flash memory
Flash memory is a non-volatile form of computer storage that can be erased and rewritten over
and over again. Usually, computer memory works with the help of transistors that are turned on
by the presence of electricity and off when there is no electricity. In the case of flash memory,
the transistors resemble MOSFETs and have two gates on top that are known as floating and
control gates. Further. The two gates are divided by oxide layers that prevent current from
passing through.
Figure 3: Transistor when switched off (storing a "0") (Pinna & Knez, 2012).
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Electrons have to flow from a source to a drain to turn on the transistor and store a "1". A
movement of electrons is achieved by applying a positive voltage to a bit line and word line as
shown in figure 3. In this manner, electrons move from source to drain and others manage to
tunnel to the floating gate. The presence of electrons at the floating gate is the storage of a “1”.
Figure 4: Transistor when switched on (storing a “1”) (Zhao et al., 2014).
Problems associated with flash technology
In spite of the many benefits, flash technology also faces some limitations. Firstly, flash
memory cells tend to have a limited number of write and erase cycles before failure. In turn, this
means that flash drives have short life cycles (Zhao, Zhao, Taylor, & Chalker, 2014). Secondly,
flash drives lack a mechanism for write-protection. Moreover, in the current flash technology,
the cost per gigabyte is much higher than in regular hard drives for large capacity storage. Lastly,
with flash technology, storage devices become smaller have over time, which makes them easier
to lose.
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The Use of nanostructures to eliminate problems associated with the Flash memory
The use of nanostructures as a storage element reduces the problems related to flash
memory. For one, nanostructures allow for much faster capture times for holes and electrons,
which, in turn, lead to faster write times. Additionally, the use of nanostructured storage
elements results in longer storage times due to the use of holes as information carriers (Nowozin,
2013).
References
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Böscke, T. S. (2010). Crystalline Hafnia and Zirconia Based Dielectrics for Memory
Applications. Cuvillier.
Nowozin, T. (2013). Self-Organized Quantum Dots for Memories: Electronic Properties and
Carrier Dynamics. Springer Science & Business Media.
Pinna, N., & Knez, M. (Eds.). (2012). Atomic layer deposition of nanostructured materials. John
Wiley & Sons.
Singh, B., Marjanovic, N., Sariciftci, N. S., Schwodiauer, R., & Bauer, S. (2006). Electrical
characteristics of metal-insulator-semiconductor diodes and transistors with space charge
electret insulators: towards nonvolatile organic memories. IEEE transactions on
dielectrics and electrical insulation, 13(5), 1082-1086..
Zhao, C., Zhao, C. Z., Taylor, S., & Chalker, P. R. (2014). Review on Non-Volatile Memory
with High-k dielectrics: Flash for Generation beyond 32 nm. Materials, 7(7), 5117-5145.