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Slic-dc - Pef 4268 Ringing Slic With
Integrated Dc/dc Converter
Part No :
PEF4268 pinout
File Size : 34 KB
Pages : 2 Pages
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PEF4268 Pinout
1. limited to warranties of non-infringement, regarding
circuits, Application Circuit
find PEF4268 datasheet
Other Part Numbers in this pdf file
SLIC-DC PEF4268T PEF4268F
The ringing SLIC-DC with integrated DC/DC converter, is the latest
addition to Infineon’s family of SLIC products. The SLIC-DC provides cost
optimized solutions for CPE applications and requires only a single power
supply voltage. All POTS supply voltages are generated by the on-chip
DC/DC converter using only a few external components.
Additional SLIC-DC features include a patented ring mode that significantly
lowers power consumption of the chip, with a corresponding lower heat
dissipation and total system power consumption. The SLIC-DC is also
offered in two packages to provide maximum design flexibility.
In combination with Infineon’s DuSLIC Codec the SLIC-DC can be used to
create xDSL or ISDN CPEs. The SLIC-DC is also highly suited for Analog
Telephone Adapter (ATA) and VoIP gateway solutions, when combined with
Infineon's VINETIC analog Voice Processor and the ADM5120SP CPU.
Features
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Applications
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Customer Premises Equipment (CPE)
ISDN CPE
xDSL CPE
Analog Telephone Adapter
VoIP Gateways
Cable modems
Small PABX
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Applications
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Customer Premises Equipment (CPE)
ISDN CPE
xDSL CPE
Analog Telephone Adapter
VoIP Gateways
Cable modems
Small PABX
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Balanced ringing SLIC with integrated DC/DC
converter
Patented ring mode allows significant power
reduction
Uses robust technology based on Infineon’s
popular SLIC-E, PEB 4265
New Interface towards VINETIC-2CPE.
Backward compatible to standard Infineon
Codec-SLIC Interface known from SLIC-S,
SLIC-E and SLIC-P
Minimized external component count in order to
enable high board density design
DC/DC output voltage up to -150 V
Single unregulated power supply voltage
between 9 V and 40 V. All other voltages are
generated internally.
Up to 85 Vrms sinusodial ringing
Fully programmable DC feed characteristic
Sensing of transversal line currents
Supports Integrated Test and Diagnostic
Function (ITDF), e.g. GR-909
Synchronization of up to 8 SLIC-DC’s
Low-cost BOM
Slic-dc - Pef 4268 Ringing Slic With
Integrated Dc/dc Converter
The ringing SLIC-DC with integrated DC/DC converter, is the latest addition to Infineon’s family
of SLIC products. The SLIC-DC provides cost optimized solutions for CPE applications and
requires only a single power supply voltage. All POTS supply voltages are generated by the onchip DC/DC converter using only a few external components. Additional SLIC-DC features
include a patented ring mode that significantly lowers power consumption of the chip, with a
corresponding lower heat dissipation and total system power consumption. The SLIC-DC is also
offered in two packages to provide maximum design flexibility. In combination with Infineon’s
DuSLIC Codec the SLIC-DC can be used to create xDSL or ISDN CPEs. The SLIC-DC is also
highly suited for Analog Telephone Adapter (ATA) and VoIP gateway solutions, when combined
with Infineon's VINETIC analog Voice Processor and the ADM5120SP CPU.
Description
VOUT: Main output voltage (3.3V, 5V or adjustable) which has highest priority in the multiplexing scheme, as long as VGD is above the critical level of 7.5V.
Loads over 150mA are achievable at 1V input voltage. This output will startup with 1V input at full load.
Applications
Features
APPLICATION HINTS The PEF4268FV1.1, PEF4268FV1.1 voltage references are easier to use than
The low-cost PEF4268FV1.1 is a 14-bit, 10MH
zener diodes. Their low impedance and wide current range facilitate biasing in any cir- cuits. Besides, the
full-scale input signals up to Nyquist frequenc
breakdown voltage or the tem- perature coefficient can be adjusted so as to opti- mize the performance of
error (DNL), signal-to-noise ratio (SNR), and t
the circuit. Figure 1 represents a PEF4268FV1.1 with a 10kΩ potenti- ometer to adjust the reverse
ideal choice for both time-domain (CCD/FPA
breakdown voltage which can be adjusted without altering the temper- ature coefficient of the circuit. The
(radar, telecommunications, spectrum analysi
adjustment range is generally sufficient to adjust the initial tol- erance of the circuit and the inaccuracy of
the am- plifier circuit. To obtain a lower temperature coefficient two di- odes can be connected in series as
indicated in Figure 2. When the circuit is adjusted to 2.49V the tempera- ture coefficient is minimized. For
a correct temperature coefficient, the diodes should be at the same ambient temperature as the
PEF4268FV1.1. The value of R1 is not critical (2-20kΩ).
Description
The HYM72V16M736B(L)T6 Series are 16Mx72bits Synchronous DRAM Modules. The modules are composed of five 16Mx16bits CMOS Synchronous DRAM
in 400mil 54pin TSOP-II package, one 2Kbit EEPROM in 8pin TSSOP package on a 144 pin glass-epoxy printed circuit board.
Applications
THD+N levels of 0.06%(1kHz, 1Wrms). Efficiency is greater than 80% typical, which eliminates the need
Features
Current Limit (Input): A resistor (RSET) conne
for heatsinks in most applications. The AudioMAX™ solution requires a single supply voltage, simplifying
as ILIMIT = CLF/RSET. CLF is the current lim
input power requirements where a dual supply may not be available. To minimize potential environmental
the PEF4268TV1.14/45, the continuous outpu
noise issues and ease the integration of the amplifier into a variety of applications, features such as a
balanced/differential audio input and a high power supply rejection ratio help reduce the effects of noise
from the audio signal or power supply.
Description
via an RF or an infrared transmission medium upon receipt of a trigger signal. The capability to select a TE trigger on the HT12E or a DATA trigger on the HT12
further enhances the ap- plication flexibility of the 212 series of encoders. The HT12A additionally provides a 38kHz car- rier for infrared systems.
Applications
Features
(UART or clock synchronous) x 3 Clock synchronous 10 bits x (8 + 8 + 8 + 2) inputs 8 bits x 2 channels
PEF4268TV1.25985-01-178-4406 PEF4268T
CRC-CCITT 2 channels (trigger: 23 sources) 2 channels, 2.0B active 15 bits x 1 (with prescaler) 29
PEF4268TV1.25895-01-389-9497 PEF4268T
internal and 9 external sources, 4 software sources, 7 priority levels
PEF4268TV1.245895-01-394-6080 PEF4268
PEF4268TV1.25985-01-457-7382 PEF4268T
Description
Programmable undervoltage and overvoltage detectors disconnect the load whenever the input supply exceeds the desired operating range. The LTC4252s
supply input is shunt regulated, allowing safe operation with very high supply voltages. A multifunction timer delays initial start- up and controls the circuit
breakers response time. The circuit breakers response time is accelerated by sensing excessive MOSFET drain voltage, keeping the MOSFET within its safe
operating area (SOA). A programmable soft-start circuit controls MOSFET inrush current at start- up. A power good status output can enable a power module a
start-up or disable it if the circuit breaker trips.
Applications
Features
In addition to ISR capability, a new feature called bus-hold has been added to all FLASH370i I/Os and
Xilinx offers a TotalCMOS CPLD, both in proc
dedicated input pins. Bus-hold, which is an improved version of the popular internal pull-up resistor, is a
cascade of CMOS gates to implement its sum
weak latch connected to the pin that does not degrade the devices performance. As a latch, bus-hold
This CMOS gate imple- mentation allows Xilin
recalls the last state of a pin when it is three-stated, thus reducing system noise in bus-interface
power, breaking the paradigm that to have low
applications. Bus-hold additionally allows unused device pins to remain unconnected on the board, which
and Table 1 showing the ICC vs. Frequency o
is particularly useful during prototyping as designers can route new signals to the device without cutting
up/down, loadable 16-bit counters at 3.3V, 25
trace connections to VCC or GND.