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[ECEN 1400]
Introduction to Digital and Analog Electronics
R. McLeod
HW #6: Counters and Binary Math
1
Conversion Practice (5pts)
• Fill in the table by writing the same number in each row using the bases specified.
• Use a subscript indicates the base.
• For example 102 = 210 = 216 and 100002 = 1610 = 1016
Binary
11000112
1110112
111001112
110000112
101010102
Decimal
9910
5910
23110
19510
17010
Hexadecimal
6316
3B16
E716
C316
AA16
Grading:
• (0.5 pts per) Solve each blank space correctly
2
Same Problem, Two Bases (5pts)
Square the number 110011002 by doing long multiplication in binary. That is, multiply each element in one number
by a single digit in the other number and write the result shifted left by the position of the digit, then add the
columns with appropriate carry. (3 pts).
Then convert the original number and the answer to decimal (2 pts) and check the result.
The tricky part here is figuring out how to carry more than a single 1. Go back to what you know about
decimal to figure out how to do this.
110011002 = 20410
20410 × 20410 = 4161610 = 10100010100100002
Grading:
• (5 pts) Solve the final results
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[ECEN 1400]
3
Introduction to Digital and Analog Electronics
R. McLeod
Mixed Base Multiplication and Division (5pts)
Perform the specified operation and write the result in the specified base.
a
100110102
10102
10102
3210
101100102
Operation
÷
×
×
÷
×
b
210
410
1016
1016
1610
=
10011012
1010002
A016
102
B216
In Base
2
2
16
2
16
Grading:
• (5 pts) Solve each row correctly
4
Cascaded 74161 Counters (35pts)
Create a 4 bit counter in multisim using the 74HC163N 4V counter (CMOS → 74HC 4V → 74HC163N 4V).
This is not precisely the chip we will use the in the lab, but has sufficiently similar processes. Look at the datasheet
and the lecture notes to understand the function of the chip. Connect pins 7, 10, 9 and 1 to +5V and a function
generator (Simulate → Instruments → Function generator) to pin 2, the clock. Set the function generator
to a 32 KHz square wave with 2.5 Vp (not peak to peak) amplitude and 2.5 V offset such that the voltage is
swinging from 0 to 5V. Wire Common to ground and + to the counter clock input. Your function generator dialog
box should look like:
Show your circuit with a screen shot. Examine the outputs of QA, QB, QC, QD with a scope (Simulate →
Instuments, then pick your favorite; The Tek scope has 4 inputs, which is nice) to confirm that they are at the
expected frequencies relative to the clock input. Examine the input clock, QA, QD and RCO. Can you write a
logic expression for RCO? Is this chip triggered on the falling or rising edge of the clock?
Now copy and paste a second counter to the right of the first, wiring pints 1,9,10 and 7 the same way. Connect
QD from counter 1 to CLK (pin 2) of the new counter. Now examine the outputs QA, QB, QC, QD of counter 2
and again confirm that they are at the expected frequencies. The simulation will run a bit slowly give the large
range of time-scales in the circuit.
How many effective bits are in your combined counter? How many clock cycles occur before RCO on the
second counter signals that this counter has rolled over?
Version 3.1, October 15, 2014
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[ECEN 1400]
Introduction to Digital and Analog Electronics
R. McLeod
Solution:
Figure 1: Screen capture of single counter circuit with function generator and scope
Figure 2: Tek scope screen capture showing QA to QD as traces 1 to 4 (top to bottom). The measurement shows
that QA is at 16 KHz, down a factor of 2 since it is the least-significant bit of the counter that is driven
at 32 KHz by the clock. The other 3 lines are each a factor of two lower in frequency or 8 KHz, 4 KHz
and 2 KHz, respectively.
Version 3.1, October 15, 2014
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[ECEN 1400]
Introduction to Digital and Analog Electronics
R. McLeod
Figure 3: Tek scope screen capture showing the clock, QA, QD and RCO on traces 1-4 (top to bottom). RCO is
high when all of QA to QD are high, so RCO = QA AND QB AND QC AND QD. Transitions occur
on the rising edge of the clock.
Figure 4: Tek scope screen capture showing QA to QD as traces 1 to 4 (top to bottom). The measurement shows
that QA is at 1 KHz, down a factor of 16 from the 32 KHz function generator due to the first counter
and another factor of 2 since it is the least-significant bit of the second counter. The other 3 lines are
each a factor of two lower in frequency or 500 Hz, 250 Hz and 125 Hz, respectively.
The counter effectively has 8 bits split between the two counters for 28 = 162 = 256 states before roll over of
the second counter. The first counter rolls over every 16 states.
Grading:
• (5 pts) Schematic including power supply, 74161, function generator, oscilloscope, and wired correctly
• (5 pts) Tracing the clock, QA, QD, and RCO
• (4 pts) Write the logic expression for RCO
• (4 pts) Get the conclusion that the chip is trigger on the rising edge of the clock
• (5 pts) Schematic for the second counter correctly
• (5 pts) Examine the output of QA, QB, QC, and QD on counter 2
• (4 pts) Get the result of effectively 8 bits with the counter
• (3 pts) Get the result of 256 states of clock cycles
Version 3.1, October 15, 2014
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